mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 03:00:54 +07:00
916f562fb2
side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1 -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAl0uBEERHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSWucw/9ELKlfvdxrc8mdIuzt+CpKdNiSG88shXY hF+vnuE6Jhv5hmlbA/DbplPTAnHT/FQF65/GPQMAYy2wYO6CjleNxQyepiVv4h8/ tWoXu5vYZXubtQyMnYTffREzjYFPBNAscLUhXNwJKRno7nT0qKCk62WgOMfaW/KN lP5dKmrL7rdJDUvxHEStrwP515Lg5Wkhj3+XzgbgFUKGuGlvHfwUOEZucT++kqhu Z1vMjPv2ksHQf3r15BsbX/6jMIONEt2Xd6jA3Lm7ebDXJl2hjX4Gq0Kkl5pmkj2w F0V7Tw4XYk6DkSl7HQaOBgQ8KV0Mw2L8Vj6eEDhUwx6wPGlQ5YTKkUCJkjs0mUyb UpO3TuPFN2W0hsTNDzwYpjqcfodDn159XJcduv1/ZpIanUvHgx0uVzQ7iwwYwW+l VR4SipY5AEn9hpief30X7TAUSKsE4do58imYeoGBrq78zdsJaEcDAMX7AcYdXVQ9 ahBS8ME/d1JEBNdRsSW7eTAfu8dZdI08uR8/T37GRG59XyZSjsyVmZ6kHCYrBygF AyLNMsXMCbW1rOoIpWkuGMD86XZy40laLg8T7WWTaq28t1VQ0BaBTGM4/eEexs3p FhZ1M7aH+PsDLrI2IGTBt/4xAMv+dhDS7HnxRlOONbWnLWVqmR+tYzF0aCkqJCmd O2zWCGffeYs= =mK0C -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This round of clk driver and framework updates is heavy on the driver update side. The two main highlights in the core framework are the addition of an bulk clk_get API that handles optional clks and an extra debugfs file that tells the developer about the current parent of a clk. The driver updates are dominated by i.MX in the diffstat, but that is mostly because that SoC has started converting to the clk_hw style of clk registration. The next big update is in the Amlogic meson clk driver that gained some support for audio, cpu, and temperature clks while fixing some PLL issues. Finally, the biggest thing that stands out is the conversion of a large part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses less strings and more pointer comparisons to match clk parents and children up. In general, it looks like we have a lot of little fixes and tweaks here and there to clk data along with the normal addition of a handful of new drivers and a couple new core framework features. Core: - Add a 'clk_parent' file in clk debugfs - Add a clk_bulk_get_optional() API (with devm too) New Drivers: - Support gated clk controller on MIPS based BCM63XX SoCs - Support SiLabs Si5341 and Si5340 chips - Support for CPU clks on Raspberry Pi devices - Audsys clock driver for MediaTek MT8516 SoCs Updates: - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme - Small frequency support for SiLabs Si544 chips - Slow clk support for AT91 SAM9X60 SoCs - Remove dead code in various clk drivers (-Wunused) - Support for Marvell 98DX1135 SoCs - Get duty cycle of generic pwm clks - Improvement in mmc phase calculation and cleanup of some rate defintions - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs - Add GPIO, SNVS and GIC clocks for i.MX8 drivers - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting - Add clks for new Exynos5422 Dynamic Memory Controller driver - Clock definition for Exynos4412 Mali - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3 - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs - TI clock probing done from DT by default instead of firmware - Fix Amlogic Meson mpll fractional part and spread sprectrum issues - Add Amlogic meson8 audio clocks - Add Amlogic g12a temperature sensors clocks - Add Amlogic g12a and g12b cpu clocks - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W - Add Clock Domain support on Renesas RZ/N1" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits) clk: consoldiate the __clk_get_hw() declarations clk: sprd: Add check for return value of sprd_clk_regmap_init() clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK clk: Add Si5341/Si5340 driver dt-bindings: clock: Add silabs,si5341 clk: clk-si544: Implement small frequency change support clk: add BCM63XX gated clock controller driver devicetree: document the BCM63XX gated clock bindings clk: at91: sckc: use dedicated functions to unregister clock clk: at91: sckc: improve error path for sama5d4 sck registration clk: at91: sckc: remove unnecessary line clk: at91: sckc: improve error path for sam9x5 sck register clk: at91: sckc: add support to free slow clock osclillator clk: at91: sckc: add support to free slow rc oscillator clk: at91: sckc: add support to free slow oscillator clk: rockchip: export HDMIPHY clock on rk3228 clk: rockchip: add watchdog pclk on rk3328 clk: rockchip: add clock id for hdmi_phy special clock on rk3228 clk: rockchip: add clock id for watchdog pclk on rk3328 clk: at91: sckc: add support for SAM9X60 ...
288 lines
6.5 KiB
C
288 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
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* Author: Jeffy Chen <jeffy.chen@rock-chips.com>
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*/
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#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
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#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
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/* core clocks */
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#define PLL_APLL 1
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#define PLL_DPLL 2
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#define PLL_CPLL 3
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#define PLL_GPLL 4
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#define ARMCLK 5
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/* sclk gates (special clocks) */
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#define SCLK_SPI0 65
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#define SCLK_NANDC 67
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#define SCLK_SDMMC 68
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#define SCLK_SDIO 69
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#define SCLK_EMMC 71
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#define SCLK_TSADC 72
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#define SCLK_UART0 77
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#define SCLK_UART1 78
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#define SCLK_UART2 79
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#define SCLK_I2S0 80
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#define SCLK_I2S1 81
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#define SCLK_I2S2 82
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#define SCLK_SPDIF 83
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#define SCLK_TIMER0 85
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#define SCLK_TIMER1 86
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#define SCLK_TIMER2 87
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#define SCLK_TIMER3 88
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#define SCLK_TIMER4 89
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#define SCLK_TIMER5 90
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#define SCLK_I2S_OUT 113
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#define SCLK_SDMMC_DRV 114
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#define SCLK_SDIO_DRV 115
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#define SCLK_EMMC_DRV 117
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#define SCLK_SDMMC_SAMPLE 118
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#define SCLK_SDIO_SAMPLE 119
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#define SCLK_SDIO_SRC 120
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#define SCLK_EMMC_SAMPLE 121
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#define SCLK_VOP 122
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#define SCLK_HDMI_HDCP 123
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#define SCLK_MAC_SRC 124
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#define SCLK_MAC_EXTCLK 125
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#define SCLK_MAC 126
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#define SCLK_MAC_REFOUT 127
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#define SCLK_MAC_REF 128
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#define SCLK_MAC_RX 129
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#define SCLK_MAC_TX 130
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#define SCLK_MAC_PHY 131
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#define SCLK_MAC_OUT 132
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#define SCLK_VDEC_CABAC 133
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#define SCLK_VDEC_CORE 134
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#define SCLK_RGA 135
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#define SCLK_HDCP 136
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#define SCLK_HDMI_CEC 137
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#define SCLK_CRYPTO 138
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#define SCLK_TSP 139
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#define SCLK_HSADC 140
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#define SCLK_WIFI 141
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#define SCLK_OTGPHY0 142
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#define SCLK_OTGPHY1 143
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#define SCLK_HDMI_PHY 144
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/* dclk gates */
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#define DCLK_VOP 190
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#define DCLK_HDMI_PHY 191
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/* aclk gates */
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#define ACLK_DMAC 194
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#define ACLK_CPU 195
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#define ACLK_VPU_PRE 196
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#define ACLK_RKVDEC_PRE 197
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#define ACLK_RGA_PRE 198
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#define ACLK_IEP_PRE 199
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#define ACLK_HDCP_PRE 200
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#define ACLK_VOP_PRE 201
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#define ACLK_VPU 202
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#define ACLK_RKVDEC 203
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#define ACLK_IEP 204
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#define ACLK_RGA 205
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#define ACLK_HDCP 206
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#define ACLK_PERI 210
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#define ACLK_VOP 211
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#define ACLK_GMAC 212
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#define ACLK_GPU 213
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/* pclk gates */
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#define PCLK_GPIO0 320
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#define PCLK_GPIO1 321
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#define PCLK_GPIO2 322
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#define PCLK_GPIO3 323
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#define PCLK_VIO_H2P 324
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#define PCLK_HDCP 325
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#define PCLK_EFUSE_1024 326
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#define PCLK_EFUSE_256 327
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#define PCLK_GRF 329
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#define PCLK_I2C0 332
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#define PCLK_I2C1 333
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#define PCLK_I2C2 334
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#define PCLK_I2C3 335
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#define PCLK_SPI0 338
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#define PCLK_UART0 341
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#define PCLK_UART1 342
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#define PCLK_UART2 343
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#define PCLK_TSADC 344
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#define PCLK_PWM 350
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#define PCLK_TIMER 353
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#define PCLK_CPU 354
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#define PCLK_PERI 363
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#define PCLK_HDMI_CTRL 364
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#define PCLK_HDMI_PHY 365
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#define PCLK_GMAC 367
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/* hclk gates */
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#define HCLK_I2S0_8CH 442
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#define HCLK_I2S1_8CH 443
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#define HCLK_I2S2_2CH 444
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#define HCLK_SPDIF_8CH 445
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#define HCLK_VOP 452
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#define HCLK_NANDC 453
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#define HCLK_SDMMC 456
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#define HCLK_SDIO 457
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#define HCLK_EMMC 459
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#define HCLK_CPU 460
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#define HCLK_VPU_PRE 461
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#define HCLK_RKVDEC_PRE 462
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#define HCLK_VIO_PRE 463
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#define HCLK_VPU 464
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#define HCLK_RKVDEC 465
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#define HCLK_VIO 466
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#define HCLK_RGA 467
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#define HCLK_IEP 468
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#define HCLK_VIO_H2P 469
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#define HCLK_HDCP_MMU 470
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#define HCLK_HOST0 471
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#define HCLK_HOST1 472
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#define HCLK_HOST2 473
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#define HCLK_OTG 474
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#define HCLK_TSP 475
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#define HCLK_M_CRYPTO 476
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#define HCLK_S_CRYPTO 477
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#define HCLK_PERI 478
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#define CLK_NR_CLKS (HCLK_PERI + 1)
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/* soft-reset indices */
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#define SRST_CORE0_PO 0
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#define SRST_CORE1_PO 1
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#define SRST_CORE2_PO 2
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#define SRST_CORE3_PO 3
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#define SRST_CORE0 4
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#define SRST_CORE1 5
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#define SRST_CORE2 6
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#define SRST_CORE3 7
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#define SRST_CORE0_DBG 8
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#define SRST_CORE1_DBG 9
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#define SRST_CORE2_DBG 10
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#define SRST_CORE3_DBG 11
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#define SRST_TOPDBG 12
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#define SRST_ACLK_CORE 13
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#define SRST_NOC 14
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#define SRST_L2C 15
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#define SRST_CPUSYS_H 18
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#define SRST_BUSSYS_H 19
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#define SRST_SPDIF 20
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#define SRST_INTMEM 21
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#define SRST_ROM 22
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#define SRST_OTG_ADP 23
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#define SRST_I2S0 24
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#define SRST_I2S1 25
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#define SRST_I2S2 26
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#define SRST_ACODEC_P 27
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#define SRST_DFIMON 28
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#define SRST_MSCH 29
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#define SRST_EFUSE1024 30
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#define SRST_EFUSE256 31
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#define SRST_GPIO0 32
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#define SRST_GPIO1 33
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#define SRST_GPIO2 34
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#define SRST_GPIO3 35
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#define SRST_PERIPH_NOC_A 36
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#define SRST_PERIPH_NOC_BUS_H 37
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#define SRST_PERIPH_NOC_P 38
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#define SRST_UART0 39
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#define SRST_UART1 40
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#define SRST_UART2 41
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#define SRST_PHYNOC 42
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#define SRST_I2C0 43
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#define SRST_I2C1 44
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#define SRST_I2C2 45
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#define SRST_I2C3 46
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#define SRST_PWM 48
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#define SRST_A53_GIC 49
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#define SRST_DAP 51
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#define SRST_DAP_NOC 52
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#define SRST_CRYPTO 53
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#define SRST_SGRF 54
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#define SRST_GRF 55
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#define SRST_GMAC 56
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#define SRST_PERIPH_NOC_H 58
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#define SRST_MACPHY 63
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#define SRST_DMA 64
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#define SRST_NANDC 68
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#define SRST_USBOTG 69
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#define SRST_OTGC 70
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#define SRST_USBHOST0 71
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#define SRST_HOST_CTRL0 72
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#define SRST_USBHOST1 73
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#define SRST_HOST_CTRL1 74
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#define SRST_USBHOST2 75
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#define SRST_HOST_CTRL2 76
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#define SRST_USBPOR0 77
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#define SRST_USBPOR1 78
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#define SRST_DDRMSCH 79
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#define SRST_SMART_CARD 80
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#define SRST_SDMMC 81
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#define SRST_SDIO 82
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#define SRST_EMMC 83
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#define SRST_SPI 84
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#define SRST_TSP_H 85
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#define SRST_TSP 86
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#define SRST_TSADC 87
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#define SRST_DDRPHY 88
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#define SRST_DDRPHY_P 89
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#define SRST_DDRCTRL 90
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#define SRST_DDRCTRL_P 91
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#define SRST_HOST0_ECHI 92
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#define SRST_HOST1_ECHI 93
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#define SRST_HOST2_ECHI 94
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#define SRST_VOP_NOC_A 95
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#define SRST_HDMI_P 96
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#define SRST_VIO_ARBI_H 97
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#define SRST_IEP_NOC_A 98
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#define SRST_VIO_NOC_H 99
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#define SRST_VOP_A 100
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#define SRST_VOP_H 101
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#define SRST_VOP_D 102
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#define SRST_UTMI0 103
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#define SRST_UTMI1 104
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#define SRST_UTMI2 105
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#define SRST_UTMI3 106
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#define SRST_RGA 107
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#define SRST_RGA_NOC_A 108
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#define SRST_RGA_A 109
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#define SRST_RGA_H 110
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#define SRST_HDCP_A 111
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#define SRST_VPU_A 112
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#define SRST_VPU_H 113
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#define SRST_VPU_NOC_A 116
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#define SRST_VPU_NOC_H 117
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#define SRST_RKVDEC_A 118
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#define SRST_RKVDEC_NOC_A 119
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#define SRST_RKVDEC_H 120
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#define SRST_RKVDEC_NOC_H 121
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#define SRST_RKVDEC_CORE 122
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#define SRST_RKVDEC_CABAC 123
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#define SRST_IEP_A 124
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#define SRST_IEP_H 125
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#define SRST_GPU_A 126
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#define SRST_GPU_NOC_A 127
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#define SRST_CORE_DBG 128
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#define SRST_DBG_P 129
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#define SRST_TIMER0 130
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#define SRST_TIMER1 131
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#define SRST_TIMER2 132
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#define SRST_TIMER3 133
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#define SRST_TIMER4 134
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#define SRST_TIMER5 135
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#define SRST_VIO_H2P 136
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#define SRST_HDMIPHY 139
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#define SRST_VDAC 140
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#define SRST_TIMER_6CH_P 141
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#endif
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