mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 03:00:54 +07:00
5c1a96935f
The current ipq4019 clock driver does not have the node for PCNOC so this patch adds and registers the PCNOC clock nodes. This PCNOC clock is critical and should not be turned off so setting CRITICAL flag also. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
170 lines
5.7 KiB
C
170 lines
5.7 KiB
C
/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef __QCOM_CLK_IPQ4019_H__
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#define __QCOM_CLK_IPQ4019_H__
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#define GCC_DUMMY_CLK 0
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#define AUDIO_CLK_SRC 1
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 2
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 3
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 4
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 5
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#define BLSP1_UART1_APPS_CLK_SRC 6
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#define BLSP1_UART2_APPS_CLK_SRC 7
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#define GCC_USB3_MOCK_UTMI_CLK_SRC 8
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#define GCC_APPS_CLK_SRC 9
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#define GCC_APPS_AHB_CLK_SRC 10
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#define GP1_CLK_SRC 11
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#define GP2_CLK_SRC 12
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#define GP3_CLK_SRC 13
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#define SDCC1_APPS_CLK_SRC 14
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#define FEPHY_125M_DLY_CLK_SRC 15
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#define WCSS2G_CLK_SRC 16
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#define WCSS5G_CLK_SRC 17
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#define GCC_APSS_AHB_CLK 18
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#define GCC_AUDIO_AHB_CLK 19
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#define GCC_AUDIO_PWM_CLK 20
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#define GCC_BLSP1_AHB_CLK 21
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 22
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 23
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 24
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 25
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#define GCC_BLSP1_UART1_APPS_CLK 26
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#define GCC_BLSP1_UART2_APPS_CLK 27
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#define GCC_DCD_XO_CLK 28
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#define GCC_GP1_CLK 29
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#define GCC_GP2_CLK 30
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#define GCC_GP3_CLK 31
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#define GCC_BOOT_ROM_AHB_CLK 32
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#define GCC_CRYPTO_AHB_CLK 33
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#define GCC_CRYPTO_AXI_CLK 34
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#define GCC_CRYPTO_CLK 35
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#define GCC_ESS_CLK 36
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#define GCC_IMEM_AXI_CLK 37
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#define GCC_IMEM_CFG_AHB_CLK 38
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#define GCC_PCIE_AHB_CLK 39
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#define GCC_PCIE_AXI_M_CLK 40
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#define GCC_PCIE_AXI_S_CLK 41
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#define GCC_PCNOC_AHB_CLK 42
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#define GCC_PRNG_AHB_CLK 43
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#define GCC_QPIC_AHB_CLK 44
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#define GCC_QPIC_CLK 45
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#define GCC_SDCC1_AHB_CLK 46
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#define GCC_SDCC1_APPS_CLK 47
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#define GCC_SNOC_PCNOC_AHB_CLK 48
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#define GCC_SYS_NOC_125M_CLK 49
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#define GCC_SYS_NOC_AXI_CLK 50
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#define GCC_TCSR_AHB_CLK 51
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#define GCC_TLMM_AHB_CLK 52
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#define GCC_USB2_MASTER_CLK 53
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#define GCC_USB2_SLEEP_CLK 54
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#define GCC_USB2_MOCK_UTMI_CLK 55
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#define GCC_USB3_MASTER_CLK 56
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#define GCC_USB3_SLEEP_CLK 57
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#define GCC_USB3_MOCK_UTMI_CLK 58
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#define GCC_WCSS2G_CLK 59
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#define GCC_WCSS2G_REF_CLK 60
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#define GCC_WCSS2G_RTC_CLK 61
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#define GCC_WCSS5G_CLK 62
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#define GCC_WCSS5G_REF_CLK 63
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#define GCC_WCSS5G_RTC_CLK 64
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#define GCC_APSS_DDRPLL_VCO 65
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#define GCC_SDCC_PLLDIV_CLK 66
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#define GCC_FEPLL_VCO 67
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#define GCC_FEPLL125_CLK 68
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#define GCC_FEPLL125DLY_CLK 69
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#define GCC_FEPLL200_CLK 70
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#define GCC_FEPLL500_CLK 71
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#define GCC_FEPLL_WCSS2G_CLK 72
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#define GCC_FEPLL_WCSS5G_CLK 73
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#define GCC_APSS_CPU_PLLDIV_CLK 74
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#define GCC_PCNOC_AHB_CLK_SRC 75
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#define WIFI0_CPU_INIT_RESET 0
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#define WIFI0_RADIO_SRIF_RESET 1
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#define WIFI0_RADIO_WARM_RESET 2
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#define WIFI0_RADIO_COLD_RESET 3
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#define WIFI0_CORE_WARM_RESET 4
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#define WIFI0_CORE_COLD_RESET 5
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#define WIFI1_CPU_INIT_RESET 6
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#define WIFI1_RADIO_SRIF_RESET 7
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#define WIFI1_RADIO_WARM_RESET 8
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#define WIFI1_RADIO_COLD_RESET 9
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#define WIFI1_CORE_WARM_RESET 10
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#define WIFI1_CORE_COLD_RESET 11
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#define USB3_UNIPHY_PHY_ARES 12
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#define USB3_HSPHY_POR_ARES 13
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#define USB3_HSPHY_S_ARES 14
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#define USB2_HSPHY_POR_ARES 15
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#define USB2_HSPHY_S_ARES 16
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#define PCIE_PHY_AHB_ARES 17
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#define PCIE_AHB_ARES 18
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#define PCIE_PWR_ARES 19
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#define PCIE_PIPE_STICKY_ARES 20
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#define PCIE_AXI_M_STICKY_ARES 21
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#define PCIE_PHY_ARES 22
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#define PCIE_PARF_XPU_ARES 23
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#define PCIE_AXI_S_XPU_ARES 24
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#define PCIE_AXI_M_VMIDMT_ARES 25
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#define PCIE_PIPE_ARES 26
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#define PCIE_AXI_S_ARES 27
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#define PCIE_AXI_M_ARES 28
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#define ESS_RESET 29
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#define GCC_BLSP1_BCR 30
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#define GCC_BLSP1_QUP1_BCR 31
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#define GCC_BLSP1_UART1_BCR 32
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#define GCC_BLSP1_QUP2_BCR 33
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#define GCC_BLSP1_UART2_BCR 34
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#define GCC_BIMC_BCR 35
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#define GCC_TLMM_BCR 36
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#define GCC_IMEM_BCR 37
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#define GCC_ESS_BCR 38
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#define GCC_PRNG_BCR 39
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#define GCC_BOOT_ROM_BCR 40
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#define GCC_CRYPTO_BCR 41
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#define GCC_SDCC1_BCR 42
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#define GCC_SEC_CTRL_BCR 43
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#define GCC_AUDIO_BCR 44
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#define GCC_QPIC_BCR 45
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#define GCC_PCIE_BCR 46
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#define GCC_USB2_BCR 47
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#define GCC_USB2_PHY_BCR 48
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#define GCC_USB3_BCR 49
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#define GCC_USB3_PHY_BCR 50
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#define GCC_SYSTEM_NOC_BCR 51
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#define GCC_PCNOC_BCR 52
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#define GCC_DCD_BCR 53
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#define GCC_SNOC_BUS_TIMEOUT0_BCR 54
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#define GCC_SNOC_BUS_TIMEOUT1_BCR 55
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#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
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#define GCC_SNOC_BUS_TIMEOUT3_BCR 57
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#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
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#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
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#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
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#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
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#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
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#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
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#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
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#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
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#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
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#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
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#define GCC_TCSR_BCR 68
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#define GCC_QDSS_BCR 69
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#define GCC_MPM_BCR 70
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#define GCC_SPDM_BCR 71
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#endif
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