mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 02:06:43 +07:00
294 lines
6.6 KiB
C
294 lines
6.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Realtek PCIe MMIO Translate driver
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*
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* Copyright (c) 2017 Realtek Semiconductor Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#define PCIE_IO_64K_MASK 0xFFFF0000
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struct regmap *pcie0_base;
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struct regmap *pcie1_base;
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struct regmap *pcie2_base;
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struct pcie_info {
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struct regmap *base;
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spinlock_t spinlock;
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void __iomem *mmio_base;
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struct device *dev;
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};
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struct pcie_info *pcie0_info;
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struct pcie_info *pcie1_info;
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struct pcie_info *pcie2_info;
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u32 rtk_pcie_ctrl_read(struct pcie_info *info, u32 offset)
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{
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u32 val;
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regmap_read(info->base, offset, &val);
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return val;
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}
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void rtk_pcie_ctrl_write(struct pcie_info *info, u32 offset, u32 val)
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{
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regmap_write(info->base, offset, val);
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}
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u32 rtk_pcie_mmio_read(struct pcie_info *info, u32 offset, u32 size)
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{
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u32 val;
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switch (size) {
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case 1:
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val = readb(info->mmio_base + offset);
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break;
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case 2:
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val = readw(info->mmio_base + offset);
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break;
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case 4:
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val = readl(info->mmio_base + offset);
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break;
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default:
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dev_err(info->dev, "RTD13xx: %s: wrong size %d\n", __func__, size);
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val = 0;
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break;
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}
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return val;
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}
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void rtk_pcie_mmio_write(struct pcie_info *info, u32 offset, u32 val, u32 size)
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{
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switch (size) {
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case 1:
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writeb(val, info->mmio_base + offset);
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break;
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case 2:
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writew(val, info->mmio_base + offset);
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break;
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case 4:
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writel(val, info->mmio_base + offset);
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break;
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default:
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dev_err(info->dev, "RTD13xx: %s: wrong size %d\n", __func__, size);
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break;
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}
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}
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u32 rtk_pcie_read(struct pcie_info *info, u32 addr, u8 size)
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{
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u32 rval = 0;
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u32 mask;
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u32 translate_val = 0;
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unsigned long irqL;
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u32 pci_error_status = 0;
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int retry_cnt = 0;
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u8 retry = 5;
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spin_lock_irqsave(&info->spinlock, irqL);
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if (addr >= 0x10000) {
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mask = PCIE_IO_64K_MASK;
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translate_val = rtk_pcie_ctrl_read(info, 0xD04);
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rtk_pcie_ctrl_write(info, 0xD04, translate_val | (addr & mask));
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} else
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mask = 0x0;
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pci_read_13xx_retry:
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rval = rtk_pcie_mmio_read(info, addr & ~mask, size);
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//DLLP error patch
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pci_error_status = rtk_pcie_ctrl_read(info, 0xc7c);
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if (pci_error_status & 0x1F) {
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rtk_pcie_ctrl_write(info, 0xc7c, pci_error_status);
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dev_err(info->dev, "RTD13xx: %s: DLLP(#%d) 0x%x reg=0x%x val=0x%x\n",
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__func__, retry_cnt, pci_error_status, addr, rval);
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if (retry_cnt < retry) {
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retry_cnt++;
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goto pci_read_13xx_retry;
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}
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}
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if (addr >= 0x10000)
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rtk_pcie_ctrl_write(info, 0xD04, translate_val);
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spin_unlock_irqrestore(&info->spinlock, irqL);
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return rval;
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}
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void rtk_pcie_write(struct pcie_info *info, u32 addr, u8 size, u32 wval)
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{
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u32 mask;
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u32 translate_val = 0;
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unsigned long irqL;
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spin_lock_irqsave(&info->spinlock, irqL);
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if (addr >= 0x10000) {
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mask = PCIE_IO_64K_MASK;
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translate_val = rtk_pcie_ctrl_read(info, 0xD04);
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rtk_pcie_ctrl_write(info, 0xD04, translate_val | (addr & mask));
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} else
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mask = 0x0;
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rtk_pcie_mmio_write(info, addr & ~mask, wval, size);
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if (addr >= 0x10000)
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rtk_pcie_ctrl_write(info, 0xD04, translate_val);
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spin_unlock_irqrestore(&info->spinlock, irqL);
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}
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u32 rtk_pcie_13xx_read(u32 addr, u8 size)
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{
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return rtk_pcie_read(pcie0_info, addr, size);
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}
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EXPORT_SYMBOL(rtk_pcie_13xx_read);
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void rtk_pcie_13xx_write(u32 addr, u8 size, u32 wval)
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{
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rtk_pcie_write(pcie0_info, addr, size, wval);
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}
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EXPORT_SYMBOL(rtk_pcie_13xx_write);
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u32 rtk_pcie2_13xx_read(u32 addr, u8 size)
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{
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return rtk_pcie_read(pcie1_info, addr, size);
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}
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EXPORT_SYMBOL(rtk_pcie2_13xx_read);
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void rtk_pcie2_13xx_write(u32 addr, u8 size, u32 wval)
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{
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rtk_pcie_write(pcie1_info, addr, size, wval);
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}
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EXPORT_SYMBOL(rtk_pcie2_13xx_write);
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u32 rtk_pcie3_13xx_read(u32 addr, u8 size)
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{
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return rtk_pcie_read(pcie2_info, addr, size);
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}
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EXPORT_SYMBOL(rtk_pcie3_13xx_read);
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void rtk_pcie3_13xx_write(u32 addr, u8 size, u32 wval)
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{
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rtk_pcie_write(pcie2_info, addr, size, wval);
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}
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EXPORT_SYMBOL(rtk_pcie3_13xx_write);
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static int rtd_pcie_trans_probe(struct platform_device *pdev)
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{
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struct device_node *syscon_np;
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syscon_np = of_parse_phandle(pdev->dev.of_node, "syscon", 0);
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if (IS_ERR_OR_NULL(syscon_np))
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return -ENODEV;
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pcie0_info = devm_kzalloc(&pdev->dev, sizeof(*pcie0_info), GFP_KERNEL);
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pcie0_info->dev = &pdev->dev;
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pcie0_info->base = syscon_node_to_regmap(syscon_np);
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if (IS_ERR_OR_NULL(pcie0_info->base)) {
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of_node_put(syscon_np);
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return -EINVAL;
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}
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pcie0_info->mmio_base = of_iomap(pdev->dev.of_node, 0);
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if (!pcie0_info->mmio_base) {
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dev_err(&pdev->dev, "failed to get pcie0 mmio address\n");
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return -EINVAL;
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}
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spin_lock_init(&pcie0_info->spinlock);
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syscon_np = of_parse_phandle(pdev->dev.of_node, "syscon", 1);
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if (IS_ERR_OR_NULL(syscon_np))
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return -ENODEV;
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pcie1_info = devm_kzalloc(&pdev->dev, sizeof(*pcie1_info), GFP_KERNEL);
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pcie1_info->dev = &pdev->dev;
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pcie1_info->base = syscon_node_to_regmap(syscon_np);
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if (IS_ERR_OR_NULL(pcie1_info->base)) {
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of_node_put(syscon_np);
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return -EINVAL;
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}
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pcie1_info->mmio_base = of_iomap(pdev->dev.of_node, 1);
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if (!pcie1_info->mmio_base) {
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dev_err(&pdev->dev, "failed to get pcie1 mmio address\n");
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return -EINVAL;
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}
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spin_lock_init(&pcie1_info->spinlock);
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syscon_np = of_parse_phandle(pdev->dev.of_node, "syscon", 2);
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if (IS_ERR_OR_NULL(syscon_np))
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return -ENODEV;
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pcie2_info = devm_kzalloc(&pdev->dev, sizeof(*pcie2_info), GFP_KERNEL);
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pcie2_info->dev = &pdev->dev;
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pcie2_info->base = syscon_node_to_regmap(syscon_np);
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if (IS_ERR_OR_NULL(pcie2_info->base)) {
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of_node_put(syscon_np);
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return -EINVAL;
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}
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pcie2_info->mmio_base = of_iomap(pdev->dev.of_node, 2);
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if (!pcie2_info->mmio_base) {
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dev_err(&pdev->dev, "failed to get pcie2 mmio address\n");
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return -EINVAL;
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}
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spin_lock_init(&pcie2_info->spinlock);
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dev_info(&pdev->dev, "\n===========rtd13xx pcie mmio translate ready\n");
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return 0;
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}
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static const struct of_device_id rtd_pcie_trans_match_table[] = {
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{.compatible = "realtek,rtd13xx-pcie-trans"},
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{},
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};
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static struct platform_driver rtd_pcie_trans_driver = {
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.driver = {
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.name = "Realtek DHC PCIe mmio translate",
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.of_match_table = of_match_ptr(rtd_pcie_trans_match_table),
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},
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.probe = rtd_pcie_trans_probe,
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};
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module_platform_driver(rtd_pcie_trans_driver);
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MODULE_AUTHOR("TYChang <tychang@realtek.com>");
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MODULE_DESCRIPTION("Realtek PCIe MMIO translate driver");
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MODULE_LICENSE("GPL v2");
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