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89d449867c
[ Upstream commit f6ea568f0ddcdfad52807110ed8983e610f0e03b ]
We shouldn't need to hold this spinlock here around the entire SCM call
into the firmware and back. Instead, we should be able to query the
firmware, potentially in parallel with other CPUs making the same
convention detection firmware call, and then grab the lock to update the
calling convention detected. The convention doesn't change at runtime so
calling into firmware more than once is possibly wasteful but simpler.
Besides, this is the slow path, not the fast path where we've already
detected the convention used.
More importantly, this allows us to add more logic here to workaround
the case where the firmware call to check for availability isn't
implemented in the firmware at all. In that case we can check the
firmware node compatible string and force a calling convention.
Note that we remove the 'has_queried' logic that is repeated twice. That
could lead to the calling convention being printed multiple times to the
kernel logs if the bool is true but __query_convention() is running on
multiple CPUs. We also shorten the time where the lock is held, but we
keep the lock held around the printk because it doesn't seem hugely
important to drop it for that.
Cc: Elliot Berman <eberman@codeaurora.org>
Cc: Brian Masney <masneyb@onstation.org>
Cc: Stephan Gerhold <stephan@gerhold.net>
Cc: Jeffrey Hugo <jhugo@codeaurora.org>
Cc: Douglas Anderson <dianders@chromium.org>
Fixes: 9a434cee77 ("firmware: qcom_scm: Dynamically support SMCCC and legacy conventions")
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lore.kernel.org/r/20210223214539.1336155-3-swboyd@chromium.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
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*/
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#ifndef __QCOM_SCM_INT_H
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#define __QCOM_SCM_INT_H
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enum qcom_scm_convention {
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SMC_CONVENTION_UNKNOWN,
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SMC_CONVENTION_LEGACY,
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SMC_CONVENTION_ARM_32,
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SMC_CONVENTION_ARM_64,
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};
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extern enum qcom_scm_convention qcom_scm_convention;
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#define MAX_QCOM_SCM_ARGS 10
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#define MAX_QCOM_SCM_RETS 3
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enum qcom_scm_arg_types {
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QCOM_SCM_VAL,
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QCOM_SCM_RO,
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QCOM_SCM_RW,
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QCOM_SCM_BUFVAL,
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};
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#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
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(((a) & 0x3) << 4) | \
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(((b) & 0x3) << 6) | \
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(((c) & 0x3) << 8) | \
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(((d) & 0x3) << 10) | \
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(((e) & 0x3) << 12) | \
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(((f) & 0x3) << 14) | \
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(((g) & 0x3) << 16) | \
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(((h) & 0x3) << 18) | \
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(((i) & 0x3) << 20) | \
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(((j) & 0x3) << 22) | \
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((num) & 0xf))
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#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
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/**
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* struct qcom_scm_desc
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* @arginfo: Metadata describing the arguments in args[]
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* @args: The array of arguments for the secure syscall
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*/
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struct qcom_scm_desc {
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u32 svc;
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u32 cmd;
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u32 arginfo;
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u64 args[MAX_QCOM_SCM_ARGS];
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u32 owner;
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};
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/**
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* struct qcom_scm_res
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* @result: The values returned by the secure syscall
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*/
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struct qcom_scm_res {
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u64 result[MAX_QCOM_SCM_RETS];
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};
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#define SCM_SMC_FNID(s, c) ((((s) & 0xFF) << 8) | ((c) & 0xFF))
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extern int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
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enum qcom_scm_convention qcom_convention,
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struct qcom_scm_res *res, bool atomic);
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#define scm_smc_call(dev, desc, res, atomic) \
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__scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))
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#define SCM_LEGACY_FNID(s, c) (((s) << 10) | ((c) & 0x3ff))
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extern int scm_legacy_call_atomic(struct device *dev,
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const struct qcom_scm_desc *desc,
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struct qcom_scm_res *res);
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extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
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struct qcom_scm_res *res);
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#define QCOM_SCM_SVC_BOOT 0x01
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#define QCOM_SCM_BOOT_SET_ADDR 0x01
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#define QCOM_SCM_BOOT_TERMINATE_PC 0x02
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#define QCOM_SCM_BOOT_SET_DLOAD_MODE 0x10
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#define QCOM_SCM_BOOT_SET_REMOTE_STATE 0x0a
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#define QCOM_SCM_FLUSH_FLAG_MASK 0x3
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#define QCOM_SCM_SVC_PIL 0x02
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#define QCOM_SCM_PIL_PAS_INIT_IMAGE 0x01
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#define QCOM_SCM_PIL_PAS_MEM_SETUP 0x02
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#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
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#define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06
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#define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07
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#define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a
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#define QCOM_SCM_SVC_IO 0x05
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#define QCOM_SCM_IO_READ 0x01
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#define QCOM_SCM_IO_WRITE 0x02
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#define QCOM_SCM_SVC_INFO 0x06
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#define QCOM_SCM_INFO_IS_CALL_AVAIL 0x01
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#define QCOM_SCM_SVC_MP 0x0c
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#define QCOM_SCM_MP_RESTORE_SEC_CFG 0x02
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE 0x03
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#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT 0x04
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#define QCOM_SCM_MP_VIDEO_VAR 0x08
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#define QCOM_SCM_MP_ASSIGN 0x16
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#define QCOM_SCM_SVC_OCMEM 0x0f
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#define QCOM_SCM_OCMEM_LOCK_CMD 0x01
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#define QCOM_SCM_OCMEM_UNLOCK_CMD 0x02
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#define QCOM_SCM_SVC_ES 0x10 /* Enterprise Security */
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#define QCOM_SCM_ES_INVALIDATE_ICE_KEY 0x03
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#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY 0x04
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#define QCOM_SCM_SVC_HDCP 0x11
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#define QCOM_SCM_HDCP_INVOKE 0x01
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#define QCOM_SCM_SVC_SMMU_PROGRAM 0x15
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1 0x03
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#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
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extern void __qcom_scm_init(void);
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/* common error codes */
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#define QCOM_SCM_V2_EBUSY -12
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#define QCOM_SCM_ENOMEM -5
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#define QCOM_SCM_EOPNOTSUPP -4
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#define QCOM_SCM_EINVAL_ADDR -3
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#define QCOM_SCM_EINVAL_ARG -2
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#define QCOM_SCM_ERROR -1
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#define QCOM_SCM_INTERRUPTED 1
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static inline int qcom_scm_remap_error(int err)
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{
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switch (err) {
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case QCOM_SCM_ERROR:
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return -EIO;
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case QCOM_SCM_EINVAL_ADDR:
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case QCOM_SCM_EINVAL_ARG:
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return -EINVAL;
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case QCOM_SCM_EOPNOTSUPP:
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return -EOPNOTSUPP;
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case QCOM_SCM_ENOMEM:
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return -ENOMEM;
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case QCOM_SCM_V2_EBUSY:
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return -EBUSY;
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}
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return -EINVAL;
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}
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#endif
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