/* SPDX-License-Identifier: GPL-2.0 */ /* * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2018 Xilinx * * Michal Simek * Davorin Mista * Jolly Shah * Rajan Vaja */ #ifndef __FIRMWARE_ZYNQMP_H__ #define __FIRMWARE_ZYNQMP_H__ #define ZYNQMP_PM_VERSION_MAJOR 1 #define ZYNQMP_PM_VERSION_MINOR 0 #define ZYNQMP_PM_VERSION ((ZYNQMP_PM_VERSION_MAJOR << 16) | \ ZYNQMP_PM_VERSION_MINOR) #define ZYNQMP_TZ_VERSION_MAJOR 1 #define ZYNQMP_TZ_VERSION_MINOR 0 #define ZYNQMP_TZ_VERSION ((ZYNQMP_TZ_VERSION_MAJOR << 16) | \ ZYNQMP_TZ_VERSION_MINOR) /* SMC SIP service Call Function Identifier Prefix */ #define PM_SIP_SVC 0xC2000000 #define PM_GET_TRUSTZONE_VERSION 0xa03 /* Number of 32bits values in payload */ #define PAYLOAD_ARG_CNT 4U enum pm_api_id { PM_GET_API_VERSION = 1, PM_RESET_ASSERT = 17, PM_RESET_GET_STATUS, PM_GET_CHIPID = 24, PM_IOCTL = 34, PM_QUERY_DATA, PM_CLOCK_ENABLE, PM_CLOCK_DISABLE, PM_CLOCK_GETSTATE, PM_CLOCK_SETDIVIDER, PM_CLOCK_GETDIVIDER, PM_CLOCK_SETRATE, PM_CLOCK_GETRATE, PM_CLOCK_SETPARENT, PM_CLOCK_GETPARENT, }; /* PMU-FW return status codes */ enum pm_ret_status { XST_PM_SUCCESS = 0, XST_PM_INTERNAL = 2000, XST_PM_CONFLICT, XST_PM_NO_ACCESS, XST_PM_INVALID_NODE, XST_PM_DOUBLE_REQ, XST_PM_ABORT_SUSPEND, }; enum pm_ioctl_id { IOCTL_SET_PLL_FRAC_MODE = 8, IOCTL_GET_PLL_FRAC_MODE, IOCTL_SET_PLL_FRAC_DATA, IOCTL_GET_PLL_FRAC_DATA, }; enum pm_query_id { PM_QID_INVALID, PM_QID_CLOCK_GET_NAME, PM_QID_CLOCK_GET_TOPOLOGY, PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS, PM_QID_CLOCK_GET_PARENTS, PM_QID_CLOCK_GET_ATTRIBUTES, PM_QID_CLOCK_GET_NUM_CLOCKS = 12, }; enum zynqmp_pm_reset_action { PM_RESET_ACTION_RELEASE, PM_RESET_ACTION_ASSERT, PM_RESET_ACTION_PULSE, }; enum zynqmp_pm_reset { ZYNQMP_PM_RESET_START = 1000, ZYNQMP_PM_RESET_PCIE_CFG = ZYNQMP_PM_RESET_START, ZYNQMP_PM_RESET_PCIE_BRIDGE, ZYNQMP_PM_RESET_PCIE_CTRL, ZYNQMP_PM_RESET_DP, ZYNQMP_PM_RESET_SWDT_CRF, ZYNQMP_PM_RESET_AFI_FM5, ZYNQMP_PM_RESET_AFI_FM4, ZYNQMP_PM_RESET_AFI_FM3, ZYNQMP_PM_RESET_AFI_FM2, ZYNQMP_PM_RESET_AFI_FM1, ZYNQMP_PM_RESET_AFI_FM0, ZYNQMP_PM_RESET_GDMA, ZYNQMP_PM_RESET_GPU_PP1, ZYNQMP_PM_RESET_GPU_PP0, ZYNQMP_PM_RESET_GPU, ZYNQMP_PM_RESET_GT, ZYNQMP_PM_RESET_SATA, ZYNQMP_PM_RESET_ACPU3_PWRON, ZYNQMP_PM_RESET_ACPU2_PWRON, ZYNQMP_PM_RESET_ACPU1_PWRON, ZYNQMP_PM_RESET_ACPU0_PWRON, ZYNQMP_PM_RESET_APU_L2, ZYNQMP_PM_RESET_ACPU3, ZYNQMP_PM_RESET_ACPU2, ZYNQMP_PM_RESET_ACPU1, ZYNQMP_PM_RESET_ACPU0, ZYNQMP_PM_RESET_DDR, ZYNQMP_PM_RESET_APM_FPD, ZYNQMP_PM_RESET_SOFT, ZYNQMP_PM_RESET_GEM0, ZYNQMP_PM_RESET_GEM1, ZYNQMP_PM_RESET_GEM2, ZYNQMP_PM_RESET_GEM3, ZYNQMP_PM_RESET_QSPI, ZYNQMP_PM_RESET_UART0, ZYNQMP_PM_RESET_UART1, ZYNQMP_PM_RESET_SPI0, ZYNQMP_PM_RESET_SPI1, ZYNQMP_PM_RESET_SDIO0, ZYNQMP_PM_RESET_SDIO1, ZYNQMP_PM_RESET_CAN0, ZYNQMP_PM_RESET_CAN1, ZYNQMP_PM_RESET_I2C0, ZYNQMP_PM_RESET_I2C1, ZYNQMP_PM_RESET_TTC0, ZYNQMP_PM_RESET_TTC1, ZYNQMP_PM_RESET_TTC2, ZYNQMP_PM_RESET_TTC3, ZYNQMP_PM_RESET_SWDT_CRL, ZYNQMP_PM_RESET_NAND, ZYNQMP_PM_RESET_ADMA, ZYNQMP_PM_RESET_GPIO, ZYNQMP_PM_RESET_IOU_CC, ZYNQMP_PM_RESET_TIMESTAMP, ZYNQMP_PM_RESET_RPU_R50, ZYNQMP_PM_RESET_RPU_R51, ZYNQMP_PM_RESET_RPU_AMBA, ZYNQMP_PM_RESET_OCM, ZYNQMP_PM_RESET_RPU_PGE, ZYNQMP_PM_RESET_USB0_CORERESET, ZYNQMP_PM_RESET_USB1_CORERESET, ZYNQMP_PM_RESET_USB0_HIBERRESET, ZYNQMP_PM_RESET_USB1_HIBERRESET, ZYNQMP_PM_RESET_USB0_APB, ZYNQMP_PM_RESET_USB1_APB, ZYNQMP_PM_RESET_IPI, ZYNQMP_PM_RESET_APM_LPD, ZYNQMP_PM_RESET_RTC, ZYNQMP_PM_RESET_SYSMON, ZYNQMP_PM_RESET_AFI_FM6, ZYNQMP_PM_RESET_LPD_SWDT, ZYNQMP_PM_RESET_FPD, ZYNQMP_PM_RESET_RPU_DBG1, ZYNQMP_PM_RESET_RPU_DBG0, ZYNQMP_PM_RESET_DBG_LPD, ZYNQMP_PM_RESET_DBG_FPD, ZYNQMP_PM_RESET_APLL, ZYNQMP_PM_RESET_DPLL, ZYNQMP_PM_RESET_VPLL, ZYNQMP_PM_RESET_IOPLL, ZYNQMP_PM_RESET_RPLL, ZYNQMP_PM_RESET_GPO3_PL_0, ZYNQMP_PM_RESET_GPO3_PL_1, ZYNQMP_PM_RESET_GPO3_PL_2, ZYNQMP_PM_RESET_GPO3_PL_3, ZYNQMP_PM_RESET_GPO3_PL_4, ZYNQMP_PM_RESET_GPO3_PL_5, ZYNQMP_PM_RESET_GPO3_PL_6, ZYNQMP_PM_RESET_GPO3_PL_7, ZYNQMP_PM_RESET_GPO3_PL_8, ZYNQMP_PM_RESET_GPO3_PL_9, ZYNQMP_PM_RESET_GPO3_PL_10, ZYNQMP_PM_RESET_GPO3_PL_11, ZYNQMP_PM_RESET_GPO3_PL_12, ZYNQMP_PM_RESET_GPO3_PL_13, ZYNQMP_PM_RESET_GPO3_PL_14, ZYNQMP_PM_RESET_GPO3_PL_15, ZYNQMP_PM_RESET_GPO3_PL_16, ZYNQMP_PM_RESET_GPO3_PL_17, ZYNQMP_PM_RESET_GPO3_PL_18, ZYNQMP_PM_RESET_GPO3_PL_19, ZYNQMP_PM_RESET_GPO3_PL_20, ZYNQMP_PM_RESET_GPO3_PL_21, ZYNQMP_PM_RESET_GPO3_PL_22, ZYNQMP_PM_RESET_GPO3_PL_23, ZYNQMP_PM_RESET_GPO3_PL_24, ZYNQMP_PM_RESET_GPO3_PL_25, ZYNQMP_PM_RESET_GPO3_PL_26, ZYNQMP_PM_RESET_GPO3_PL_27, ZYNQMP_PM_RESET_GPO3_PL_28, ZYNQMP_PM_RESET_GPO3_PL_29, ZYNQMP_PM_RESET_GPO3_PL_30, ZYNQMP_PM_RESET_GPO3_PL_31, ZYNQMP_PM_RESET_RPU_LS, ZYNQMP_PM_RESET_PS_ONLY, ZYNQMP_PM_RESET_PL, ZYNQMP_PM_RESET_PS_PL0, ZYNQMP_PM_RESET_PS_PL1, ZYNQMP_PM_RESET_PS_PL2, ZYNQMP_PM_RESET_PS_PL3, ZYNQMP_PM_RESET_END = ZYNQMP_PM_RESET_PS_PL3 }; /** * struct zynqmp_pm_query_data - PM query data * @qid: query ID * @arg1: Argument 1 of query data * @arg2: Argument 2 of query data * @arg3: Argument 3 of query data */ struct zynqmp_pm_query_data { u32 qid; u32 arg1; u32 arg2; u32 arg3; }; struct zynqmp_eemi_ops { int (*get_api_version)(u32 *version); int (*get_chipid)(u32 *idcode, u32 *version); int (*query_data)(struct zynqmp_pm_query_data qdata, u32 *out); int (*clock_enable)(u32 clock_id); int (*clock_disable)(u32 clock_id); int (*clock_getstate)(u32 clock_id, u32 *state); int (*clock_setdivider)(u32 clock_id, u32 divider); int (*clock_getdivider)(u32 clock_id, u32 *divider); int (*clock_setrate)(u32 clock_id, u64 rate); int (*clock_getrate)(u32 clock_id, u64 *rate); int (*clock_setparent)(u32 clock_id, u32 parent_id); int (*clock_getparent)(u32 clock_id, u32 *parent_id); int (*ioctl)(u32 node_id, u32 ioctl_id, u32 arg1, u32 arg2, u32 *out); int (*reset_assert)(const enum zynqmp_pm_reset reset, const enum zynqmp_pm_reset_action assert_flag); int (*reset_get_status)(const enum zynqmp_pm_reset reset, u32 *status); }; #if IS_REACHABLE(CONFIG_ARCH_ZYNQMP) const struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void); #else static inline struct zynqmp_eemi_ops *zynqmp_pm_get_eemi_ops(void) { return NULL; } #endif #endif /* __FIRMWARE_ZYNQMP_H__ */