/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
	};


	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		pll6: clk@01c20028 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6";
		};

		cpu: cpu@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20050 0x4>;

			/*
			 * PLL1 is listed twice here.
			 * While it looks suspicious, it's actually documented
			 * that way both in the datasheet and in the code from
			 * Allwinner.
			 */
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
			clock-output-names = "cpu";
		};

		axi: axi@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-axi-clk";
			reg = <0x01c20050 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		ahb1_mux: ahb1_mux@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
			clock-output-names = "ahb1_mux";
		};

		ahb1: ahb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1_mux>;
			clock-output-names = "ahb1";
		};

		ahb1_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb1>;
			clock-output-names = "ahb1_mipidsi", "ahb1_ss",
					"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
					"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
					"ahb1_nand0", "ahb1_sdram",
					"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
					"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
					"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
					"ahb1_ehci1", "ahb1_ohci0",
					"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
					"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
					"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
					"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
					"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
					"ahb1_drc0", "ahb1_drc1";
		};

		apb1: apb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1>;
			clock-output-names = "apb1";
		};

		apb1_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb1-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_codec", "apb1_digital_mic",
					"apb1_pio", "apb1_daudio0",
					"apb1_daudio1";
		};

		apb2_mux: apb2_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
			clock-output-names = "apb2_mux";
		};

		apb2: apb2@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-apb2-div-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb2_mux>;
			clock-output-names = "apb2";
		};

		apb2_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb2-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb2>;
			clock-output-names = "apb2_i2c0", "apb2_i2c1",
					"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
					"apb2_uart1", "apb2_uart2", "apb2_uart3",
					"apb2_uart4", "apb2_uart5";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi2";
		};

		spi3_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi3";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		nmi_intc: interrupt-controller@01f00c0c {
			compatible = "allwinner,sun6i-a31-sc-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x01f00c0c 0x38>;
			interrupts = <0 32 4>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun6i-a31-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 11 4>,
				     <0 15 4>,
				     <0 16 4>,
				     <0 17 4>;
			clocks = <&apb1_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PH20", "PH21";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PH14", "PH15";
				allwinner,function = "i2c0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PH16", "PH17";
				allwinner,function = "i2c1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PH18", "PH19";
				allwinner,function = "i2c2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		ahb1_rst: reset@01c202c0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-ahb1-reset";
			reg = <0x01c202c0 0xc>;
		};

		apb1_rst: reset@01c202d0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d0 0x4>;
		};

		apb2_rst: reset@01c202d8 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d8 0x4>;
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <0 18 4>,
				     <0 19 4>,
				     <0 20 4>,
				     <0 21 4>,
				     <0 22 4>;
			clocks = <&osc24M>;
		};

		wdt1: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 0 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 16>;
			resets = <&apb2_rst 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 1 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 17>;
			resets = <&apb2_rst 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 2 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 18>;
			resets = <&apb2_rst 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 3 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 19>;
			resets = <&apb2_rst 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 4 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 20>;
			resets = <&apb2_rst 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <0 5 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 21>;
			resets = <&apb2_rst 21>;
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <0 6 4>;
			clocks = <&apb2_gates 0>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 0>;
			status = "disabled";
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <0 7 4>;
			clocks = <&apb2_gates 1>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 1>;
			status = "disabled";
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <0 8 4>;
			clocks = <&apb2_gates 2>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 2>;
			status = "disabled";
		};

		i2c3: i2c@01c2b800 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b800 0x400>;
			interrupts = <0 9 4>;
			clocks = <&apb2_gates 3>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 3>;
			status = "disabled";
		};

		timer@01c60000 {
			compatible = "allwinner,sun6i-a31-hstimer", "allwinner,sun7i-a20-hstimer";
			reg = <0x01c60000 0x1000>;
			interrupts = <0 51 4>,
				     <0 52 4>,
				     <0 53 4>,
				     <0 54 4>;
			clocks = <&ahb1_gates 19>;
			resets = <&ahb1_rst 19>;
		};

		spi0: spi@01c68000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c68000 0x1000>;
			interrupts = <0 65 4>;
			clocks = <&ahb1_gates 20>, <&spi0_clk>;
			clock-names = "ahb", "mod";
			resets = <&ahb1_rst 20>;
			status = "disabled";
		};

		spi1: spi@01c69000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c69000 0x1000>;
			interrupts = <0 66 4>;
			clocks = <&ahb1_gates 21>, <&spi1_clk>;
			clock-names = "ahb", "mod";
			resets = <&ahb1_rst 21>;
			status = "disabled";
		};

		spi2: spi@01c6a000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c6a000 0x1000>;
			interrupts = <0 67 4>;
			clocks = <&ahb1_gates 22>, <&spi2_clk>;
			clock-names = "ahb", "mod";
			resets = <&ahb1_rst 22>;
			status = "disabled";
		};

		spi3: spi@01c6b000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c6b000 0x1000>;
			interrupts = <0 68 4>;
			clocks = <&ahb1_gates 23>, <&spi3_clk>;
			clock-names = "ahb", "mod";
			resets = <&ahb1_rst 23>;
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};

		cpucfg@01f01c00 {
			compatible = "allwinner,sun6i-a31-cpuconfig";
			reg = <0x01f01c00 0x300>;
		};

		prcm@01f01c00 {
			compatible = "allwinner,sun6i-a31-prcm";
			reg = <0x01f01400 0x200>;
		};
	};
};