/* * SAMSUNG EXYNOS5410 SoC device tree source * * Copyright (c) 2013 Samsung Electronics Co., Ltd. * http://www.samsung.com * * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file. * EXYNOS5410 based board files can include this file and provide * values for board specfic bindings. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include "skeleton.dtsi" #include "exynos-syscon-restart.dtsi" #include / { compatible = "samsung,exynos5410", "samsung,exynos5"; interrupt-parent = <&gic>; aliases { pinctrl0 = &pinctrl_0; pinctrl1 = &pinctrl_1; pinctrl2 = &pinctrl_2; pinctrl3 = &pinctrl_3; serial0 = &uart0; serial1 = &uart1; serial2 = &uart2; }; cpus { #address-cells = <1>; #size-cells = <0>; CPU0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x0>; clock-frequency = <1600000000>; }; CPU1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x1>; clock-frequency = <1600000000>; }; CPU2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x2>; clock-frequency = <1600000000>; }; CPU3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a15"; reg = <0x3>; clock-frequency = <1600000000>; }; }; soc: soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; combiner: interrupt-controller@10440000 { compatible = "samsung,exynos4210-combiner"; #interrupt-cells = <2>; interrupt-controller; samsung,combiner-nr = <32>; reg = <0x10440000 0x1000>; interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>, <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>, <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>, <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>, <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>, <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>, <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>, <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>; }; gic: interrupt-controller@10481000 { compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic"; #interrupt-cells = <3>; interrupt-controller; reg = <0x10481000 0x1000>, <0x10482000 0x1000>, <0x10484000 0x2000>, <0x10486000 0x2000>; interrupts = <1 9 0xf04>; }; chipid@10000000 { compatible = "samsung,exynos4210-chipid"; reg = <0x10000000 0x100>; }; sromc: memory-controller@12250000 { compatible = "samsung,exynos4210-srom"; reg = <0x12250000 0x14>; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0x04000000 0x20000 1 0 0x05000000 0x20000 2 0 0x06000000 0x20000 3 0 0x07000000 0x20000>; }; pmu_system_controller: system-controller@10040000 { compatible = "samsung,exynos5410-pmu", "syscon"; reg = <0x10040000 0x5000>; clock-names = "clkout16"; clocks = <&fin_pll>; #clock-cells = <1>; }; mct: mct@101C0000 { compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0xB00>; interrupt-parent = <&interrupt_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>; clocks = <&fin_pll>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; interrupt_map: interrupt-map { #interrupt-cells = <1>; #address-cells = <0>; #size-cells = <0>; interrupt-map = <0 &combiner 23 3>, <1 &combiner 23 4>, <2 &combiner 25 2>, <3 &combiner 25 3>, <4 &gic 0 120 0>, <5 &gic 0 121 0>, <6 &gic 0 122 0>, <7 &gic 0 123 0>, <8 &gic 0 128 0>, <9 &gic 0 129 0>, <10 &gic 0 130 0>, <11 &gic 0 131 0>; }; }; sysram@02020000 { compatible = "mmio-sram"; reg = <0x02020000 0x54000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x02020000 0x54000>; smp-sysram@0 { compatible = "samsung,exynos4210-sysram"; reg = <0x0 0x1000>; }; smp-sysram@53000 { compatible = "samsung,exynos4210-sysram-ns"; reg = <0x53000 0x1000>; }; }; clock: clock-controller@10010000 { compatible = "samsung,exynos5410-clock"; reg = <0x10010000 0x30000>; #clock-cells = <1>; }; mmc_0: mmc@12200000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12200000 0x1000>; interrupts = <0 75 0>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; status = "disabled"; }; mmc_1: mmc@12210000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12210000 0x1000>; interrupts = <0 76 0>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; status = "disabled"; }; mmc_2: mmc@12220000 { compatible = "samsung,exynos5250-dw-mshc"; reg = <0x12220000 0x1000>; interrupts = <0 77 0>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>; clock-names = "biu", "ciu"; fifo-depth = <0x80>; status = "disabled"; }; pinctrl_0: pinctrl@13400000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x13400000 0x1000>; interrupts = <0 45 0>; wakeup-interrupt-controller { compatible = "samsung,exynos4210-wakeup-eint"; interrupt-parent = <&gic>; interrupts = <0 32 0>; }; }; pinctrl_1: pinctrl@14000000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x14000000 0x1000>; interrupts = <0 46 0>; }; pinctrl_2: pinctrl@10d10000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x10d10000 0x1000>; interrupts = <0 50 0>; }; pinctrl_3: pinctrl@03860000 { compatible = "samsung,exynos5410-pinctrl"; reg = <0x03860000 0x1000>; interrupts = <0 47 0>; }; uart0: serial@12C00000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C00000 0x100>; interrupts = <0 51 0>; clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; uart1: serial@12C10000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C10000 0x100>; interrupts = <0 52 0>; clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; uart2: serial@12C20000 { compatible = "samsung,exynos4210-uart"; reg = <0x12C20000 0x100>; interrupts = <0 53 0>; clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; }; }; #include "exynos5410-pinctrl.dtsi"