/* * Copyright (C) 2016 BayLibre, SAS * Author: Neil Armstrong * Copyright (C) 2015 Amlogic, Inc. All rights reserved. * Copyright (C) 2014 Endless Mobile * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of the * License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, but * WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU * General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, see . * * Written by: * Jasper St. Pierre */ #include #include #include #include #include #include #include #include #include #include #include #include "meson_plane.h" #include "meson_vpp.h" #include "meson_viu.h" #include "meson_canvas.h" #include "meson_registers.h" struct meson_plane { struct drm_plane base; struct meson_drm *priv; }; #define to_meson_plane(x) container_of(x, struct meson_plane, base) static int meson_plane_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) { struct drm_crtc_state *crtc_state; if (!state->crtc) return 0; crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); return drm_atomic_helper_check_plane_state(state, crtc_state, DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING, true, true); } /* Takes a fixed 16.16 number and converts it to integer. */ static inline int64_t fixed16_to_int(int64_t value) { return value >> 16; } static void meson_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { struct meson_plane *meson_plane = to_meson_plane(plane); struct drm_plane_state *state = plane->state; struct drm_framebuffer *fb = state->fb; struct meson_drm *priv = meson_plane->priv; struct drm_gem_cma_object *gem; struct drm_rect src = { .x1 = (state->src_x), .y1 = (state->src_y), .x2 = (state->src_x + state->src_w), .y2 = (state->src_y + state->src_h), }; struct drm_rect dest = { .x1 = state->crtc_x, .y1 = state->crtc_y, .x2 = state->crtc_x + state->crtc_w, .y2 = state->crtc_y + state->crtc_h, }; unsigned long flags; u8 canvas_id_osd1; /* * Update Coordinates * Update Formats * Update Buffer * Enable Plane */ spin_lock_irqsave(&priv->drm->event_lock, flags); /* Enable OSD and BLK0, set max global alpha */ priv->viu.osd1_ctrl_stat = OSD_ENABLE | (0xFF << OSD_GLOBAL_ALPHA_SHIFT) | OSD_BLK0_ENABLE; if (priv->canvas) canvas_id_osd1 = priv->canvas_id_osd1; else canvas_id_osd1 = MESON_CANVAS_ID_OSD1; /* Set up BLK0 to point to the right canvas */ priv->viu.osd1_blk0_cfg[0] = ((canvas_id_osd1 << OSD_CANVAS_SEL) | OSD_ENDIANNESS_LE); /* On GXBB, Use the old non-HDR RGB2YUV converter */ if (meson_vpu_is_compatible(priv, "amlogic,meson-gxbb-vpu")) priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB; switch (fb->format->format) { case DRM_FORMAT_XRGB8888: /* For XRGB, replace the pixel's alpha by 0xFF */ writel_bits_relaxed(OSD_REPLACE_EN, OSD_REPLACE_EN, priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | OSD_COLOR_MATRIX_32_ARGB; break; case DRM_FORMAT_ARGB8888: /* For ARGB, use the pixel's alpha */ writel_bits_relaxed(OSD_REPLACE_EN, 0, priv->io_base + _REG(VIU_OSD1_CTRL_STAT2)); priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 | OSD_COLOR_MATRIX_32_ARGB; break; case DRM_FORMAT_RGB888: priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 | OSD_COLOR_MATRIX_24_RGB; break; case DRM_FORMAT_RGB565: priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 | OSD_COLOR_MATRIX_16_RGB565; break; }; /* * When the output is interlaced, the OSD must switch between * each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0 * at each vsync. * But the vertical scaler can provide such funtionnality if * is configured for 2:1 scaling with interlace options enabled. */ if (state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) { priv->viu.osd1_interlace = true; dest.y1 /= 2; dest.y2 /= 2; priv->viu.osd_sc_ctrl0 = BIT(3) | /* Enable scaler */ BIT(2); /* Select OSD1 */ /* 2:1 scaling */ priv->viu.osd_sc_i_wh_m1 = ((drm_rect_width(&dest) - 1) << 16) | (drm_rect_height(&dest) - 1); priv->viu.osd_sc_o_h_start_end = (dest.x1 << 16) | dest.x2; priv->viu.osd_sc_o_v_start_end = (dest.y1 << 16) | dest.y2; /* 2:1 vertical scaling values */ priv->viu.osd_sc_v_ini_phase = BIT(16); priv->viu.osd_sc_v_phase_step = BIT(25); priv->viu.osd_sc_v_ctrl0 = (4 << 0) | /* osd_vsc_bank_length */ (4 << 3) | /* osd_vsc_top_ini_rcv_num0 */ (1 << 8) | /* osd_vsc_top_rpt_p0_num0 */ (6 << 11) | /* osd_vsc_bot_ini_rcv_num0 */ (2 << 16) | /* osd_vsc_bot_rpt_p0_num0 */ BIT(23) | /* osd_prog_interlace */ BIT(24); /* Enable vertical scaler */ /* No horizontal scaling */ priv->viu.osd_sc_h_ini_phase = 0; priv->viu.osd_sc_h_phase_step = 0; priv->viu.osd_sc_h_ctrl0 = 0; } else { priv->viu.osd1_interlace = false; priv->viu.osd_sc_ctrl0 = 0; priv->viu.osd_sc_h_ctrl0 = 0; priv->viu.osd_sc_v_ctrl0 = 0; } /* * The format of these registers is (x2 << 16 | x1), * where x2 is exclusive. * e.g. +30x1920 would be (1919 << 16) | 30 */ priv->viu.osd1_blk0_cfg[1] = ((fixed16_to_int(src.x2) - 1) << 16) | fixed16_to_int(src.x1); priv->viu.osd1_blk0_cfg[2] = ((fixed16_to_int(src.y2) - 1) << 16) | fixed16_to_int(src.y1); priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1; priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1; /* Update Canvas with buffer address */ gem = drm_fb_cma_get_gem_obj(fb, 0); priv->viu.osd1_addr = gem->paddr; priv->viu.osd1_stride = fb->pitches[0]; priv->viu.osd1_height = fb->height; spin_unlock_irqrestore(&priv->drm->event_lock, flags); } static void meson_plane_atomic_disable(struct drm_plane *plane, struct drm_plane_state *old_state) { struct meson_plane *meson_plane = to_meson_plane(plane); struct meson_drm *priv = meson_plane->priv; /* Disable OSD1 */ writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, priv->io_base + _REG(VPP_MISC)); } static const struct drm_plane_helper_funcs meson_plane_helper_funcs = { .atomic_check = meson_plane_atomic_check, .atomic_disable = meson_plane_atomic_disable, .atomic_update = meson_plane_atomic_update, }; static const struct drm_plane_funcs meson_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, .destroy = drm_plane_cleanup, .reset = drm_atomic_helper_plane_reset, .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, }; static const uint32_t supported_drm_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB8888, DRM_FORMAT_RGB888, DRM_FORMAT_RGB565, }; int meson_plane_create(struct meson_drm *priv) { struct meson_plane *meson_plane; struct drm_plane *plane; meson_plane = devm_kzalloc(priv->drm->dev, sizeof(*meson_plane), GFP_KERNEL); if (!meson_plane) return -ENOMEM; meson_plane->priv = priv; plane = &meson_plane->base; drm_universal_plane_init(priv->drm, plane, 0xFF, &meson_plane_funcs, supported_drm_formats, ARRAY_SIZE(supported_drm_formats), NULL, DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane"); drm_plane_helper_add(plane, &meson_plane_helper_funcs); priv->primary_plane = plane; return 0; }