/*
 * Device Tree Source for the r8a73a4 SoC
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Magnus Damm
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/ {
	compatible = "renesas,r8a73a4";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1500000000>;
		};
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0xf1001000 0 0x1000>,
			<0 0xf1002000 0 0x1000>,
			<0 0xf1004000 0 0x2000>,
			<0 0xf1006000 0 0x2000>;
		interrupts = <1 9 0xf04>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 0xf08>,
				<1 14 0xf08>,
				<1 11 0xf08>,
				<1 10 0xf08>;
	};

	irqc0: interrupt-controller@e61c0000 {
		compatible = "renesas,irqc";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0 0xe61c0000 0 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <0 0 4>, <0 1 4>, <0 2 4>,	<0 3 4>,
				<0 4 4>, <0 5 4>, <0 6 4>, <0 7 4>,
				<0 8 4>, <0 9 4>, <0 10 4>, <0 11 4>,
				<0 12 4>, <0 13 4>, <0 14 4>, <0 15 4>,
				<0 16 4>, <0 17 4>, <0 18 4>, <0 19 4>,
				<0 20 4>, <0 21 4>, <0 22 4>, <0 23 4>,
				<0 24 4>, <0 25 4>, <0 26 4>, <0 27 4>,
				<0 28 4>, <0 29 4>, <0 30 4>, <0 31 4>;
	};

	irqc1: interrupt-controller@e61c0200 {
		compatible = "renesas,irqc";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0 0xe61c0200 0 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <0 32 4>, <0 33 4>, <0 34 4>, <0 35 4>,
				<0 36 4>, <0 37 4>, <0 38 4>, <0 39 4>,
				<0 40 4>, <0 41 4>, <0 42 4>, <0 43 4>,
				<0 44 4>, <0 45 4>, <0 46 4>, <0 47 4>,
				<0 48 4>, <0 49 4>, <0 50 4>, <0 51 4>,
				<0 52 4>, <0 53 4>, <0 54 4>, <0 55 4>,
				<0 56 4>, <0 57 4>;
	};

	thermal@e61f0000 {
		compatible = "renesas,rcar-thermal";
		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
			 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
		interrupt-parent = <&gic>;
		interrupts = <0 69 4>;
	};

	i2c0: i2c@e6500000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,rmobile-iic";
		reg = <0 0xe6500000 0 0x428>;
		interrupt-parent = <&gic>;
		interrupts = <0 174 0x4>;
	};

	i2c1: i2c@e6510000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,rmobile-iic";
		reg = <0 0xe6510000 0 0x428>;
		interrupt-parent = <&gic>;
		interrupts = <0 175 0x4>;
	};

	i2c2: i2c@e6520000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,rmobile-iic";
		reg = <0 0xe6520000 0 0x428>;
		interrupt-parent = <&gic>;
		interrupts = <0 176 0x4>;
	};

	i2c3: i2c@e6530000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,rmobile-iic";
		reg = <0 0xe6530000 0 0x428>;
		interrupt-parent = <&gic>;
		interrupts = <0 177 0x4>;
	};

	i2c4: i2c@e6540000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,rmobile-iic";
		reg = <0 0xe6540000 0 0x428>;
		interrupt-parent = <&gic>;
		interrupts = <0 178 0x4>;
	};

	i2c5: i2c@e60b0000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,rmobile-iic";
		reg = <0 0xe60b0000 0 0x428>;
		interrupt-parent = <&gic>;
		interrupts = <0 179 0x4>;
	};

	i2c6: i2c@e6550000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,rmobile-iic";
		reg = <0 0xe6550000 0 0x428>;
		interrupt-parent = <&gic>;
		interrupts = <0 184 0x4>;
	};

	i2c7: i2c@e6560000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,rmobile-iic";
		reg = <0 0xe6560000 0 0x428>;
		interrupt-parent = <&gic>;
		interrupts = <0 185 0x4>;
	};

	i2c8: i2c@e6570000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,rmobile-iic";
		reg = <0 0xe6570000 0 0x428>;
		interrupt-parent = <&gic>;
		interrupts = <0 173 0x4>;
	};
};