The legacy S3C-DMA API required every period of a cyclic buffer to be
queued separately. After conversion of Samsung ASoC to Samsung DMA
wrappers somebody made an assumption that the same is needed for DMA
engine API, which is not true.
In effect, Samsung ASoC DMA code was queuing the whole cyclic buffer
multiple times with a shift of one period per iteration, leading to:
a) severe memory waste - up to 13x times more DMA transfer descriptors
are allocated than needed,
b) possible memory corruption, because further cyclic buffers were out
of the original buffers, due to the offset.
This patch fixes this problem by making the legacy S3C-DMA API use the
same semantics as DMA engine (the whole cyclic buffer is enqueued at
once) and modifying users of Samsung DMA wrappers in cyclic mode to
behave appropriately.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
The DPI and SDI platform devices are currently created with the ID of
-1. The ID doesn't currently affect anything.
However, we have added regulator supply entries for "omapdss_dpi.0" and
"omapdss_sdi.0" to the board files, although these supply entries are
not yet used. As the ID used for the devices is -1, these regulator
supply entries will not work.
To fix the issue, assign ID of 0 to the devices. In the future there may
be more than one DPI or SDI output, so it makes sense to have a proper
ID for them.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Reviewed-by: Archit Taneja <archit@ti.com>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.19 (GNU/Linux)
iQEcBAABAgAGBQJSGqS5AAoJEHm+PkMAQRiGFxEH/3VrqF6WAkcviNiW/0DCdO8k
v6Wi7Sp5LxVkwzmOCHCV1tTHwLRlH3cB9YmJlGQ0kHCREaAuEQAB0xJXIW7dnyYj
Qq7KoRZEMe3wizmjEsj8qsrhfMLzHjBw67hBz2znwW/4P7YdgzwD7KRiEat+yRC9
ON3nNL2zIqpfk92RXvVrSVl4KMEM+WNbOfiffgBiEP24Ja1MJMFH1d4i6hNOaB0x
9Pb3Lw8let92x+8Ao5jnjKdKMgVsoZWbN/TgQR8zZOHM38AGGiDgk18vMz+L+hpS
jqfjckxj1m30jGq0qZ9ZbMZx3IGif4KccVr30MqNHJpwi6Q24qXvT3YfA3HkstM=
=nAab
-----END PGP SIGNATURE-----
Merge tag 'v3.11-rc7' into devel
Merged in this to avoid conflicts with the big locking fixes
from upstream.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Conflicts:
drivers/pinctrl/pinctrl-sunxi.c
Let's follow the ratified DT binding and use uartdm instead of
hsuart. This does break backwards compatibility but this
shouldn't be a problem because the uart driver isn't probing on
these devices without adding clock support (which isn't merged so
far).
Cc: David Brown <davidb@codeaurora.org>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
From Lorenzo Pieralisi:
This patch series contains:
- GIC driver update to add a method to disable the GIC CPU IF
- TC2 MCPM update to add GIC CPU disabling to suspend method
- TC2 CPU idle big.LITTLE driver
* cpuidle/biglittle:
cpuidle: big.LITTLE: vexpress-TC2 CPU idle driver
ARM: vexpress: tc2: disable GIC CPU IF in tc2_pm_suspend
drivers: irq-chip: irq-gic: introduce gic_cpu_if_down()
ARM: vexpress/TC2: implement PM suspend method
ARM: vexpress/TC2: basic PM support
ARM: vexpress: Add SCC to V2P-CA15_A7's device tree
ARM: vexpress/TC2: add Serial Power Controller (SPC) support
ARM: vexpress/dcscb: fix cache disabling sequences
Signed-off-by: Olof Johansson <olof@lixom.net>
To prevent cores from exiting wfi when they are about to be shut down
the GIC CPU IF must be disabled so that the GIC CPU IF IRQ output line
is not asserted to the cores. wfi completion must be prevented since,
in absence of coordinating HW logic, if the power controller receives
a standbywfi signal but in the meantime the processor restarts executing
owing to a pending IRQ, the core might be reset when running in a
non-quiescent state (eg with pending load/store transactions)
Raw GIC distributor IRQ signals are routed to the power controller, that
is capable of taking core out of reset on pending IRQs even if their GIC
CPU IF is disabled, thus keeping the normal wfi behaviour.
GIC CPU IF is restored upon CPU wake-up by the respective MCPM API
consumers (ie CPU idle driver and suspend to RAM thread).
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
* Per-CPU SMP boot and sleep code on SoCs that use SCU
* Shared SCU CPU Hotplug code on r8a7779 and sh73a0 SoCs
* Shared SCU CPU boot code on emev2, r8a7779 and sh73a0 SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJSAawzAAoJENfPZGlqN0++MRgP/0TDYa+QhVd6h43a6tZ7OBGp
+sln2YQOrQFSSSVxnqIwFAfISoG0Fb0upvlalvPueLSUP4NCNDAIgNVilUMkOwZq
qkDr3QAIcp+tJq/jzI+y7gK0T6DWAIgutLX8n/GbR9ZAGl4huRZiM1kRnRotUA89
mhK0I8B2xNFeqdqhFm9UqslCctuQDxCdFSJhDl+mV+cM6cQyXfbP4XFXI53x5i7d
91YDa6/zVeGGL9sqVFthEESXmZMpjWgO3Rnw0QByp/hvXDRF+AsMxUQx2B+65zm7
SsUEBdUTXTtarqVr5oiqYOzMiFQ8tJXNXUxghRcN5RET5KsdHye/uwWzV01qtcBj
d917baHS3Po5EQ6TxOseaRLSHmNVfeDn00esxRz+KywnTjZzhKh3AcZq640a0UPf
ljjKLAiQvWLcdawG6rp24TA4nOS3jwIyALvgrRL0k74oie5O/yV307+n/m46iJvA
d08+mBNkKTWV+uZQXo9cxyRITD/b3Wv27AXS+hPdRwCX3BtA81Y2w7u5LnlskuZr
H3HvvJ3G9OzkvXZTdqolntqBUn9Fr++ptJjzZG+WYPM8KGngKeSBR9a3NrwSCa2v
xprAEXb8hg1h3E721xGckIk7b6IJbGdN7euSEy4T/XNaj2wI4jLfGE/5adZk54+H
MxumRYYdhJqudCJs0lhy
=6QVN
-----END PGP SIGNATURE-----
Merge tag 'renesas-smp-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/renesas
From Simon Horman:
Renesas ARM based SoC SMP updates for v3.12
* Per-CPU SMP boot and sleep code on SoCs that use SCU
* Shared SCU CPU Hotplug code on r8a7779 and sh73a0 SoCs
* Shared SCU CPU boot code on emev2, r8a7779 and sh73a0 SoCs
* tag 'renesas-smp-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: Per-CPU SMP boot / sleep code for SCU SoCs
ARM: shmobile: Introduce per-CPU SMP boot / sleep code
ARM: shmobile: Use shared SCU CPU Hotplug code on r8a7779
ARM: shmobile: Use shared SCU CPU Hotplug code on sh73a0
ARM: shmobile: Add shared SCU CPU Hotplug code
ARM: shmobile: Use shared SCU SMP boot code on emev2
ARM: shmobile: Use shared SCU SMP boot code on r8a7779
ARM: shmobile: Use shared SCU SMP boot code on sh73a0
ARM: shmobile: Introduce shared SCU SMP boot code
Signed-off-by: Olof Johansson <olof@lixom.net>
* Remove global GPIO_NR definition from sh73a0 SoC
* Remove unnecessary nfsroot settings from bootargs of
kzm9d and armadillo800eva
* Rename irq initialisation functions of r8a7779 SoC
to make them consistent with other SoCs
* Simplify irq initialisation of r8a7740 SoC
* Add missing __initdata annotations to bockw board, and
r8a7790 and r8a7779 SoCs
* Refactor time initialisation and remove shmobile_init_time.
- This affects the following boards: kzm9g, marzen, ape6evm,
armadillo800eva and bockw
- This affects the following SoCs: r8a7790, r8a7779, r7a7740, r7a73a4
* Cleanup device registration code of r8a7778 SoC
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJSAaigAAoJENfPZGlqN0++6dIQAJmaeKd/6QsHXy1Yc0h6knMk
J2Jf1gL4lHM9FrsmFKVLqY6W6b0ctRPxBJXhpLEr2nfNnml924LHVKaxMXSnqvea
Bn5U44L6X/Tpx04+I1KLkWRcLmej+1xULra15yZvb1YgtCueJcgzxAaZN+6vgIle
NHK+gQsGqGnIIXAXawXF7p6v4SwSoUrcuqYd6IekmIKGYhxTNFKpyLZd6MY6I+Tp
F14ulRnewAJWG5HrXbtLJlE2MOcd5IAvsRtMEizZO+3vmzf8esM+Fw9s39+2v0zg
8+lpucb68vaovjaP9TPgDTT9ddELL/0xrzfWnPFYWtaGiLOV//BEZYkOUhRqZy5I
P55PZnlpjacSLDeJpsQxQGOx8RERhVKrNVycr1+XN0RnalLXI7lNepV7+j4cXUZw
kFr2hEzRKwJ820rZNKmzGQEVLWypLtFxVdA9JBX3SP3vPe4QvuK1IWfb0VSs5L5s
7h8Cwvshb1jnULM1LhNobpQzQ2WTljghUiZU1omGOvQh8qzPn0+Iy9POVa5wBwCk
PPYUJaL+aJYeikWMrxX757X1SYWKvuQ6pnNSEZSJm35HY4ESRg7gO/M56Ns1L62z
lrcIf2OKbN8wUyqp1lZSg2HgJ+Du9N5mlSBVVw4sZBPN/Iukl+Jb0MznWhttEq2P
dCb+bon+o5CS1+9xPGjI
=Sbjt
-----END PGP SIGNATURE-----
Merge tag 'renesas-cleanup3-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/renesas
From Simon Horman:
Third round of Renesas ARM based SoC cleanups for v3.12
* Remove global GPIO_NR definition from sh73a0 SoC
* Remove unnecessary nfsroot settings from bootargs of
kzm9d and armadillo800eva
* Rename irq initialisation functions of r8a7779 SoC
to make them consistent with other SoCs
* Simplify irq initialisation of r8a7740 SoC
* Add missing __initdata annotations to bockw board, and
r8a7790 and r8a7779 SoCs
* Refactor time initialisation and remove shmobile_init_time.
- This affects the following boards: kzm9g, marzen, ape6evm,
armadillo800eva and bockw
- This affects the following SoCs: r8a7790, r8a7779, r7a7740, r7a73a4
* Cleanup device registration code of r8a7778 SoC
* tag 'renesas-cleanup3-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (45 commits)
ARM: shmobile: sh73a0: Remove global GPIO_NR definition
ARM: shmobile: kzm9d: remove nfsroot settings from bootargs
ARM: shmobile: armadillo800eva: remove nfsroot settings from bootargs
ARM: shmobile: r8a7779: move r8a7779_init_irq_xxx() to setup
ARM: shmobile: r8a7740: move r8a7740_init_irq_of() to setup
ARM: shmobile: bockw: add missing __initdata
ARM: shmobile: r8a7790: add missing __initdata
ARM: shmobile: r8a7779: add missing __initdata
ARM: shmobile: Remove unused shmobile_init_time()
ARM: shmobile: Use clocksource_of_init() on r8a7790
ARM: shmobile: Use default ->init_time() on KZM9G DT ref
ARM: shmobile: Use default ->init_time() on Marzen DT ref
ARM: shmobile: Use default ->init_time() on APE6EVM DT ref
ARM: shmobile: Use default ->init_time() on APE6EVM
ARM: shmobile: Use default ->init_time() on Armadillo DT ref
ARM: shmobile: Use default ->init_time() on Bockw DT ref
ARM: shmobile: Use default ->init_time() on Bockw
ARM: shmobile: Use default ->init_time() on r8a7779
ARM: shmobile: Use default ->init_time() on r8a7778
ARM: shmobile: Use default ->init_time() on r8a7740
...
Signed-off-by: Olof Johansson <olof@lixom.net>
* Remove mach/hardware.h which has no useful contents
* Remove ag5evm board support
* Remove kota2 board support
* Use pm-rmobile on sh7372 and r8a7740 SoCs only, it is otherwise unneeded
* Remove use of INTC header on r8a7779 and r8a7740 SoCs
* Cleanup registration of usb phy in r8a7779 SoC
* Remove '0x's from R8A7779 DTS file for r8a7779 SoC
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.12 (GNU/Linux)
iQIcBAABAgAGBQJR+hf1AAoJENfPZGlqN0+++0gP/2hSp6T9qQAmriOeOTE9NrOu
fLx/d35Q70u5p14NfjKKs0vDIc/II8YqHizHlF5+mW1getnhBDNDS761f6nypmUw
LE19YgBE/idDEyz4WBbr+YFrXVS1Mq494UzN4esePtTrG2joQIv6krE6SX1shsLz
yCmUk+zPXEvhv/oVJLahm0pe+UjJHqWbST6gbscL5WTNnfQM3JhQQIJwGruge2Ui
c0ja+irLphCVgFgVvn1YwgtuvDaoL/qSxqGgESISL2awPEUoF/nQExTQ3U/DjBZN
VWAYpy6DFyYl5B8ZZh5UUowA7ed/trVVbblsrbu9Z93GxRRgNal/rU1pCS/uPoyw
Giw3f51VGWrvw5Vrb/Fpl8OsMRn7rpcnWROsR0glkn/DHlNJkw5b60g2lLtYaL4m
33rNH18l2B+rmzbhsF+kwDR2JxYXyaE+iyfMXGBkhLsRfhCCiUq4iP3+u0hpsnPw
FB0+ngnlsjypYVLgkkYSUOzvnDHmB3uz+bH+5psDD6+L5+mp7H4KhhTrQXCBqdVZ
Up2qKT7lJz+T0nnzJQZtXS+n+I4O06ewtghwG3MxtQ/NbwS6mUrqE18YMRj/21Af
d91bhBnMpWX251T5LRqUlqHQCmVn9F8EuO7VK1qEX0GavxT+71ChlBDSXlGK/uqY
wZbyX/n24e9B50AeyNVv
=ujiw
-----END PGP SIGNATURE-----
Merge tag 'renesas-cleanup2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/renesas
From Simon Horman:
Second round of Renesas ARM based SoC cleanups for v3.12
* Remove mach/hardware.h which has no useful contents
* Remove ag5evm board support
* Remove kota2 board support
* Use pm-rmobile on sh7372 and r8a7740 SoCs only, it is otherwise unneeded
* Remove use of INTC header on r8a7779 and r8a7740 SoCs
* Cleanup registration of usb phy in r8a7779 SoC
* Remove '0x's from R8A7779 DTS file for r8a7779 SoC
* tag 'renesas-cleanup2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (74 commits)
ARM: shmobile: r8a7779: Remove '0x's from R8A7779 DTS file
ARM: shmobile: r8a7779: cleanup registration of usb phy
ARM: shmobile: No need to use INTC header on r8a7779
ARM: shmobile: No need to use INTC demux on r8a7740
ARM: shmobile: Use pm-rmobile on sh7372 and r8a7740 only
ARM: shmobile: r8a73a4: Remove ->init_machine() special case
ARM: shmobile: Remove include <mach/hardware.h>
ARM: shmobile: Remove Marzen use of <mach/hardware.h>
ARM: shmobile: Remove r8a7779 use of <mach/hardware.h>
ARM: shmobile: Remove EMEV2 use of <mach/hardware.h>
ARM: shmobile: Remove sh7372 use of <mach/hardware.h>
ARM: shmobile: Remove sh73a0 use of <mach/hardware.h>
ARCH: ARM: shmobile: Remove ag5evm board support
ARCH: ARM: shmobile: Remove kota2 board support
leds: Remove leds-renesas-tpu driver
ARM: shmobile: sh73a0: Remove all GPIOs
ARM: shmobile: kota2: Use leds-pwm + pwm-rmob
ARM: shmobile: armadillo800eva: Add backlight support
ARM: shmobile: Setup r8a7790 arch timer based on MD pins
ARM: shmobile: Introduce r8a7790_read_mode_pins()
...
Signed-off-by: Olof Johansson <olof@lixom.net>
The old display drivers are no longer used, and will be phased out. So
remove them from the omap2plus_defconfig.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for AM3517EVM board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Note: the management of LCD GPIOs is unclear. They were originally muxed
as inputs, and LCD_PANEL_PWR was labelled as "dvi enable".
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for Zoom board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for OMAP3 Pandora board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: Grazvydas Ignotas <notasas@gmail.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for OMAP3EVM board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for 3430SDP board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for H4 board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for cm-t35 board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for igep0020 board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for OMAP3 Stalker board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for LDP board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for 2430SDP board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use new display drivers for devkit8000 board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use the new display drivers for Beagleboard.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use the new display drivers for RX51 board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Tested-by: Aaro Koskinen <aaro.koskinen@iki.fi>
Acked-by: Tony Lindgren <tony@atomide.com>
Use the new display drivers for OMAP3 Overo board.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Note that the LCD add-on boards for lcd43 and lcd35 use the same GPIOs
for the panels. This means that both panel devices cannot be probed at
the same time.
DT will handle this correctly, i.e. the DT data will contain the panel
device only for the add-on board that is attached. However, for the
board file we need a hackish solution: We parse the kernel boot command
line, and see whether lcd43 or lcd35 is set as a default display, and
add the given one. Or, if neither is given, default to lcd43.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
4430SDP board has an option for a PicoDLP mini-projector. PicoDLP cannot
be used at the same time as the second LCD, and there are GPIOs that
need to be set/unset when changing the used display.
Managing that kind of board specific setup is not simple without board
file callbacks. As only some 4430SDP boards actually have the PicoDLP
installed, and 4430SDP boards are not that common in the first place,
let's remove PicoDLP data from the board file.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Use the new display drivers for OMAP4 Panda and OMAP4 SDP boards.
The new OMAP display drivers were merged for 3.11, and we can now change
the board files to use the new ones and phase out the old ones.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Add some of the most common new display drivers to omap2plus_defconfig
to be built as modules.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
This is no longer needed as omap4 is now booted using device tree.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
In downstream kernel we've standardized the clock consumer names
that MSM device drivers use. Replace the uart specific clock
names in this driver with the more standard 'core' and 'iface'
names. Also simplify the code by assuming that clk_prepare_enable
and clk_disable_unprepare() will properly check for NULL pointers
(it will because MSM uses the common clock framework).
Cc: David Brown <davidb@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
So I assumed that Beagle bone has only one USB port in host mode because
the micro USB connector had an USB-UART there. I was wrong a little. The
second port runs on host mode, but the micro USB plug is connected to an
internal HUB with two ports: one to the USB-UART and one to musb
instance one.
For that reason, this patch enables both ports: the primary in device
mode only and the second in host mode only.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This is what I observe:
On the first connect, the musb starts with DEVCTL.Session set. On
disconnect, musb_core calls try_idle. That functions removes the Session
bit signalizing that the session is over (something that only in OTG is
required). A new device, that is plugged, is no longer recognized.
I've setup a timer and checked the DEVCTL register and I haven't seen a
change in VBus and I saw the B-Device bit set. After setting the IDDIG
into A mode and forcing the device to behave like a A device, I didn't
see a change.
Neither VBUS goes to 0b11 nor does a session start request comes.
In the TI-v3.2 kernel they skip to call musb_platform_try_idle() in the
OTG_STATE_A_WAIT_BCON state while not in OTG mode.
Since the second port hast a standard A plug the patch changes the port
to run in host mode only and skips the timer which would remove
DEVCTL.Session so we can reconnect to another device later.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This relfects the code and dts requires changes due to recent .dts
binding updates:
- use mg prefix for the Metor Graphics specific attributes
- use power in mA not in mA/2 as specifed in the USB2.0 specification
- remove the child node for USB. This is driver specific on won't be
reflected in the device tree
- use the "mentor" prefix instead of "mg".
- use "dr_mode" istead of "mg,port-mode" for the port mode. The former
is used by a few other drivers.
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>
I forgot to separete the different names in the reg-names property. This
didn't cause anything to fail because the driver does not use the names
and simply relies on the order of the memory offsets in reg.
This patch fixes this in case it is used later.
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This patch skips the deep C1(AFTR -Arm off top running) state for
exynos5440 SoC as this soc does not support this state. The cpu's
only allows the basic C0 state.
The C1 state is filtered by re-initialising the driver state_count
value to 1.
Suggested-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Currently PM domains support will be enabled for EXYNOS4X12 SoCs
only if EXYNOS4210 SoC or EXYNOS5250 SoC support is also enabled.
Fix it by explicitly selecting PM domains support (if PM support
is enabled) by SOC_EXYNOS4212 and SOC_EXYNOS4412 config options.
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable reserved memory initialization from device tree.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Michal Nazarewicz <mina86@mina86.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
This patch cleans the initialization of dma contiguous framework. The
all-in-one dma_declare_contiguous() function is now separated into
dma_contiguous_reserve_area() which only steals the the memory from
memblock allocator and dma_contiguous_add_device() function, which
assigns given device to the specified reserved memory area. This improves
the flexibility in defining contiguous memory areas and assigning device
to them, because now it is possible to assign more than one device to
the given contiguous memory area. Such split in initialization procedure
is also required for upcoming device tree support.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Michal Nazarewicz <mina86@mina86.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
* pm-cpufreq: (60 commits)
cpufreq: pmac32-cpufreq: remove device tree parsing for cpu nodes
cpufreq: pmac64-cpufreq: remove device tree parsing for cpu nodes
cpufreq: maple-cpufreq: remove device tree parsing for cpu nodes
cpufreq: arm_big_little: remove device tree parsing for cpu nodes
cpufreq: kirkwood-cpufreq: remove device tree parsing for cpu nodes
cpufreq: spear-cpufreq: remove device tree parsing for cpu nodes
cpufreq: highbank-cpufreq: remove device tree parsing for cpu nodes
cpufreq: cpufreq-cpu0: remove device tree parsing for cpu nodes
cpufreq: imx6q-cpufreq: remove device tree parsing for cpu nodes
drivers/bus: arm-cci: avoid parsing DT for cpu device nodes
ARM: mvebu: remove device tree parsing for cpu nodes
ARM: topology: remove hwid/MPIDR dependency from cpu_capacity
of/device: add helper to get cpu device node from logical cpu index
driver/core: cpu: initialize of_node in cpu's device struture
ARM: DT/kernel: define ARM specific arch_match_cpu_phys_id
of: move of_get_cpu_node implementation to DT core library
powerpc: refactor of_get_cpu_node to support other architectures
openrisc: remove undefined of_get_cpu_node declaration
microblaze: remove undefined of_get_cpu_node declaration
cpufreq: fix bad unlock balance on !CONFIG_SMP
...
* pm-cpuidle: (25 commits)
cpuidle: Change struct menu_device field types
cpuidle: Add a comment warning about possible overflow
cpuidle: Fix variable domains in get_typical_interval()
cpuidle: Fix menu_device->intervals type
cpuidle: CodingStyle: Break up multiple assignments on single line
cpuidle: Check called function parameter in get_typical_interval()
cpuidle: Rearrange code and comments in get_typical_interval()
cpuidle: Ignore interval prediction result when timer is shorter
cpuidle-kirkwood.c: simplify use of devm_ioremap_resource()
cpuidle: kirkwood: Make kirkwood_cpuidle_remove function static
cpuidle: calxeda: Add missing __iomem annotation
SH: cpuidle: Add missing parameter for cpuidle_register()
ARM: ux500: cpuidle: Move ux500 cpuidle driver to drivers/cpuidle
ARM: ux500: cpuidle: Remove pointless include
ARM: ux500: cpuidle: Instantiate the driver from platform device
ARM: davinci: cpuidle: Fix target residency
cpuidle: Add Kconfig.arm and move calxeda, kirkwood and zynq
cpuidle: Check if device is already registered
cpuidle: Introduce __cpuidle_device_init()
cpuidle: Introduce __cpuidle_unregister_device()
...
* pci/yinghai-assign-unassigned-v6:
PCI: Assign resources for hot-added host bridge more aggressively
PCI: Move resource reallocation code to non-__init
PCI: Delay enabling bridges until they're needed
PCI: Assign resources on a per-bus basis
PCI: Enable unassigned resource reallocation on per-bus basis
PCI: Turn on reallocation for unassigned resources with host bridge offset
PCI: Look for unassigned resources on per-bus basis
PCI: Drop temporary variable in pci_assign_unassigned_resources()
Conflicts:
drivers/net/wireless/iwlwifi/pcie/trans.c
include/linux/inetdevice.h
The inetdevice.h conflict involves moving the IPV4_DEVCONF values
into a UAPI header, overlapping additions of some new entries.
The iwlwifi conflict is a context overlap.
Signed-off-by: David S. Miller <davem@davemloft.net>
This patch describe the phy used on atmel sama5d3 mother board:
- phy address
- phy interrupt pin
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Now that the sdma driver holds the address tables for i.MX25/5 they
are no longer needed in platform_data. Remove them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Now that the clock driver knows about the available clocks found on the
A20, we can build up the clock tree from the device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Now that the clock driver has support for the A31 clocks, we can add
them to the DTSI and start using them in the relevant hardware blocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The A10s has only a subset of the A10 gates. Now that the clock driver
has support for this gates set, switch to it in the DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Pull ARM fixes from Russell King:
"This round of fixes is smaller than previous: a couple more updates
for the security fixes, and a one-liner kexec fix"
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: 7816/1: CONFIG_KUSER_HELPERS: fix help text
ARM: 7815/1: kexec: offline non panic CPUs on Kdump panic
ARM: 7819/1: fiq: Cast the first argument of flush_icache_range()
Add ADC device tree node for exynos5420 and exynos5250
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Moves the RTC DT node's "status" property from exynos5250 board
(arndale & snow) dts files to exynos5250.dtsi, since the bindings
in exynos5250.dtsi depicts the RTC h/w completely.
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Fixes the RTC DT node name for Exynos5250 as per the DT node naming
convention.
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
DEBUG_UNCOMPRESS was previously disallowed for Tegra due to tegra.S's
use of global data that was not linked into the decompressor. Solve this
by declaring this symbol in tegra.S when it is being built into the
decompressor. For the kernel proper, leave the declaration in
mach-tegra/common.c as explained in the comment.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The generic option DEBUG_LL_UART_PL01X is now used to select the UART
type for the kernel low-level debugging on the ep93xx platform. This
enables two config options to provide the physical and virtual base
address of the debug UART.
Use the generic options instead of providing platform specific options
to select the debug UART.
UART1 is selected with: DEBUG_UART_PHYS = 0x808c0000
DEBUG_UART_VIRT = 0xfedc0000
UART2 is selected with: DEBUG_UART_PHYS = 0x808d0000
DEBUG_UART_VIRT = 0xfedd0000
UART3 is selected with: DEBUG_UART_PHYS = 0x808e0000
DEBUG_UART_VIRT = 0xfede0000
The selected UART must already be initialized by the bootloader. If it
isn't setup nothing will appear (which might be desired).
Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Cc: Ryan Mallon <rmallon@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The SPEAr debug code is a copy of the PL01x debugging code, so rather
than have this pointless code duplication, lets just use the standard
implementation instead.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Davinci's debugging is just a copy of the old 8250_32 code with a
different base address. Incorporate this into the generic 8250
debug code.
Acked-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Keystone's debugging is just a copy of the old 8250_32 code with a
different base address. Incorporate this into the generic 8250
debug code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Provide generic option choices for 8250 and PL01x UART ports; these can
now be selected by UART type rather than asking about the platform.
This means that a kernel configuration user can manually choose the
various parameters of the debug UART without resorting to the platform
having to encode the possible settings.
These two generic options are preferred over further debug entries for
these ports; the existing options which refer back to the 8250 and PL01x
ports are now considered deprecated.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that the PL01X debug include can mostly stand alone without
requiring platforms to provide any macros, move it into the debug
directory so it can be directly included. This allows us to get rid of
a lot of debug-macros include files.
The autodetect case for Versatile Express and the ux500 are left alone;
these are more complicated implementations.
Acked-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Ryan Mallon <rmallon@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the definition of the UART register addresses out of the platform
specific header files into the Kconfig files.
Acked-by: Ryan Mallon <rmallon@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Now that the 8250 debug include can stand alone without requiring
platforms to provide any macros, move it into the debug directory
so it can be directly included. This allows us to get rid of a lot
of debug-macros include files.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the definition of the UART register addresses out of the platform
specific header file into the Kconfig files.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Move the definition of the UART register shift out of the platform
specific header file into the Kconfig files.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
It is silly to bury UART selection under multiple levels of choice
statements, where the top level choice statement will only list
about four entries when a single SoC is selected. Move the UART
selection up into the top level choice statement as it was always
intended to be.
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The DEBUG_LL_UART_NONE option was moved from the top of the list to
the bottom - unfortunately, it still referred to the options "below"
rather than "above".
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The C99 types uintXX_t that are usually defined in 'stdint.h' are not as
unambiguous on ARM as you would expect. For the types below, there is a
difference on ARM between GCC built for bare metal ARM, GCC built for glibc
and the kernel itself, which results in build errors if you try to build with
-ffreestanding and include 'stdint.h' (such as when you include 'arm_neon.h'
in order to use NEON intrinsics)
As the typedefs for these types in 'stdint.h' are based on builtin defines
supplied by GCC, we can tweak these to align with the kernel's idea of those
types, so 'linux/types.h' and 'stdint.h' can be safely included from the same
source file (provided that -ffreestanding is used).
int32_t uint32_t uintptr_t
bare metal GCC long unsigned long unsigned int
glibc GCC int unsigned int unsigned int
kernel int unsigned int unsigned long
Acked by: Dave Martin <dave.martin@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add the VIN and ADV7180 drivers to 'marzen_defconfig'.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Add ADV7180 platform devices on the Marzen board, configure VIN1/3 pins, and
register VIN1/3 devices with the ADV7180 specific platform data.
[Sergei: removed superfluous tabulation and inserted empty lines in the macro
definition, updated the copyrights, annotated VIN platform data as '__initdata']
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Add VIN clocks and platform devices for R8A7779 SoC; add function to register
the VIN platform devices.
[Sergei: added 'id' parameter check to r8a7779_add_vin_device(), used '*pdata'
in *sizeof* operator there, renamed some variables, annotated vin[0-3]_resources
[] and 'vin[0-3]_info' as '__initdata'.]
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Pass the CD and RO GPIO numbers to the MMC SPI driver and remove the
custom .get_cd() and .get_ro() callback functions.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
pxa910_set_wake() & mmp2_set_wake() are both declared in head files
of arch/arm/mach-mmp/include/mach directory. If we include these
head files in irq-mmp driver, it blocks the multiplatform build.
So adjust the code.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Support IRQCHIP & CONFIG_MULTI_IRQ_HANDLER in irq-mmp driver.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Reviewed-by: Daniel Drake <dsd@laptop.org>
Move irq-mmp driver from mach-mmp directory into irqchip directory.
It's used to support multiple platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Add the VIN and ML86V7667 drivers to 'bockw_defconfig'.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Add ML86V7667 platform devices on BOCK-W board, configure VIN0/1 pins, and
register VIN0/1 devices with the ML86V7667 specific platform data.
[Sergei: some macro/comment cleanup; updated the copyrights, removed duplicate
'sh_eth' driver being enabled before registering VIN1 due to a pin conflict,
removed superfluous semicolon after iclink[01]_ml86v7667' initializer.]
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Add VIN clocks and platform devices on R8A7778 SoC; add function to register
the VIN platform devices.
[Sergei: added 'id' parameter check to r8a7778_add_vin_device(), used '*pdata'
in *sizeof* operator, and added an empty line there; renamed some variables,
annotated 'vin[01]_info' and vin[01]_resources[] as '__initdata'.]
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
- Run savedefconfig on mxs_defconfig to clean it up
- Fix on mxs_restart() routine for interrupt context calling
- A few other random updates and cleanups
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJSEIhdAAoJEFBXWFqHsHzObxIH/01oTAU3W66NS6sS587KFlqD
x9SBjFuPqskU41+JumSHD/bi+N969jO4sEBSDg0VG5yM5GM7r0QAlsucNsyrSMqb
k+Kt2K/dGAVTmvUuHZoT+dgwzPdwRD1Vr1ROpxHFEt9JKhZ6wUR3tTuLEYMmIf9a
hGweLqQO3Xtv1jCuFvaqsGsxbnkE9fP9LLreaMnd4/bDnsIYgCgKt1hd5hOFawzx
zvjXC3c0HqSAuB6fISRVPMII640MgNFp3s+UWB8ImMtiL7sdGTwIPq+/viSlgG5C
iWuaYRgbqqbUZyOn6epEZI304pYy0d7eo6J7wcnnNhGwdrUqyaCV7hLMrs7v9S0=
=JFhU
-----END PGP SIGNATURE-----
Merge tag 'mxs-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
It contains mxs soc changes for 3.12.
- Run savedefconfig on mxs_defconfig to clean it up
- Fix on mxs_restart() routine for interrupt context calling
- A few other random updates and cleanups
* tag 'mxs-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs: pm: Include "pm.h"
ARM: mxs: Simplify detection of CrystalFontz boards
ARM: mach-mxs: Remove "TO" string from revision field
ARM: mxs: Fix BUG() when invoking mxs_restart() from interrupt context
ARM: mxs: Allow DT clock providers
ARM: mxs_defconfig: Cleanup mxs_defconfig
- New pinctrl entry additions for various peripherals
- Devices enabling for imx6, imx5 and imx27 boards
- Add missing device nodes like iim, owire, audmux and sram, etc.
- Various updates on boards like phytec, wandboard and sabresd
- Consolidate pad macros between imx6q and imx6dl
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJSFjFkAAoJEFBXWFqHsHzOjkcH/3c2IqXrZ/1GAQ8r4fkN1D7h
eOOiQ8hZriBxgbw72xeYAHTeMx3xZphW9n+fLHjrtqJNDI4yz/XWn2mdf55fFanm
jQb6bssbRHG4VgHaMuEjzKK4zQDrlSZgcVkOT2Aj0y+Mg7L21xUh9zRW3p2xh33x
Cg1NDLzFDChQBK/IIA0sHVOtmgn7lflfwlBbR2zvSHE4U4HNheqMCuxb3gB3aWXZ
VdxDbzQUukIwHrNlTTIV2CN2UOXfUi1Xgk7Xd/PvfAyywWpQnr7KMl9RdK4pxGo9
6G+Y984sh92jf43cF3uSCWN3+Y1bEQwmfQThoJCDV7sATG6yqblyo2X/cmUwK/c=
=llVa
-----END PGP SIGNATURE-----
Merge tag 'imx-dt-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
It contains the imx device tree updates for 3.12.
- New pinctrl entry additions for various peripherals
- Devices enabling for imx6, imx5 and imx27 boards
- Add missing device nodes like iim, owire, audmux and sram, etc.
- Various updates on boards like phytec, wandboard and sabresd
- Consolidate pad macros between imx6q and imx6dl
* tag 'imx-dt-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6: (92 commits)
ARM: dts: vf610-twr: enable i2c0 device
ARM: dts: i.MX51: Add one more I2C2 pinmux entry
ARM: dts: i.MX51: Move pins configuration under "iomuxc" label
ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog
ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator
ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX
ARM: dts: i.MX27: Disable AUDMUX in the template
ARM: dts: wandboard: Add support for SDIO bcm4329
ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template
ARM: dts: imx53-qsb: Make USBH1 functional
ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module
ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module
ARM: dts: imx6qdl-sabresd: Add touchscreen support
ARM: imx: add ocram clock for imx53
ARM: dts: imx: ocram size is different between imx6q and imx6dl
ARM: dts: imx27-phytec-phycore-som: Fix regulator settings
ARM: dts: i.MX27: Remove clock name from CPU node
ARM: dts: i.MX27: Increase "clock-latency" value
ARM: dts: i.MX27: Add label to CPU node
ARM: dts: i.MX27: Remove optional "ptp" clock source for FEC
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- Add more ethernet phy fixups for imx6 boards
- Add some missing imx6q clocks into clock driver
- Add new clock types fixup mux and div to work around some ugly
hardware defect
- Consolidate L2 cache initialization function, so that it can be used
on more i.MX SoCs
- Replace magic numbers in mach-imx6q.c with well defined macros
- Small fixes for imx6q and pllv3 clock drivers
- Some random updates on imx defconfig files
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJSFi1LAAoJEFBXWFqHsHzOpdgIAKegIwrpKKLnTQI7AunLSi5N
gOhaR4gu0BcsPejFeqCUh5Hs1zun8+MLoc/ZUtg8CQ7PkpkWSHYFOwfefldG0fLC
9Xt4SsiVNiOEsYRwtoDdEw5JGykSO0htoPOKJ0q+kIuko8mBeAm8r3J2PldF8XxX
FnHPndXnt6XYuDTOIjyfMtqDfZYAzT1ClZE1dgm7xnsXexT6fT9hdNyrqZidf4Fq
sWGxgFc3vQVUCJoO8kGQrlFcrH1BbHH0QtrzvMOvdqBmQw2HFdGS52RC83mymeyi
gcF3edsYF/fxWUoL1omV7K93TakBA5LWDHmCvDUn626fnbinYr+EIhRPomBEC1Y=
=wgVh
-----END PGP SIGNATURE-----
Merge tag 'imx-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
It contains a bunch of imx soc updates for 3.12.
- Add more ethernet phy fixups for imx6 boards
- Add some missing imx6q clocks into clock driver
- Add new clock types fixup mux and div to work around some ugly
hardware defect
- Consolidate L2 cache initialization function, so that it can be used
on more i.MX SoCs
- Replace magic numbers in mach-imx6q.c with well defined macros
- Small fixes for imx6q and pllv3 clock drivers
- Some random updates on imx defconfig files
* tag 'imx-soc-3.12' of git://git.linaro.org/people/shawnguo/linux-2.6: (33 commits)
phy: micrel: Add definitions for common Micrel PHY registers
ARM: imx: Re-select CONFIG_SND_SOC_IMX_MC13783 option
ARM: imx: Move anatop related from board file to anatop driver
ARM: imx_v6_v7_defconfig: Enable wireless support
ARM: imx_v4_v5_defconfig: Cleanup imx_v4_v5_defconfig
ARM: imx_v6_v7_defconfig: Add SATA support
ARM: imx_v6_v7_defconfig: Cleanup imx_v6_v7_defconfig
ARM: mx53: Allow suspend/resume
ARM: mach-imx: Select ARM_CPU_SUSPEND at ARCH_MXC level
ARM: imx_v6_v7_defconfig: Select CONFIG_TOUCHSCREEN_EGALAX
ARM: imx6q: add vdoa gate clock
ARM: imx6q: add the missing cko output selection
ARM: imx6q: add cko2 clocks
ARM: imx6q: add spdif gate clock
ARM: imx: clk-pllv3: improve the timeout waiting method
ARM: imx6: change some clocks to fixup clocks
ARM: imx: add common clock support for fixup mux
ARM: imx: add common clock support for fixup div
ARM: imx: Select MIGHT_HAVE_CACHE_L2X0
ARM: imx: fix imx_init_l2cache storage class
...
This patch adds alwon powerdomain support for TI81XX, which is required
for stable functioning of a big number of TI81XX subsystems.
Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
On OMAP4 we have clk_set_rate()s being done for a few
DPLL clock nodes, as part of the clock init code, since
the bootloaders no longer locks these DPLLs.
So we have a clk_set_rate() done for a ABE DPLL node (which
inturn locks it) followed by a clk_set_rate() for the USB DPLL.
With USB DPLL being in bypass, we have this parent->child
relationship thats formed while the clocks get registered.
dpll_abe_ck
|
V
dpll_abe_x2_ck
|
V
dpll_abe_m3x2_ck
|
V
usb_hs_clk_div_ck
|
V
dpll_usb_ck
This is because usb_hs_clk_div_ck is bypass clock for dpll_usb_ck.
So with this parent->child relationship in place, a clk_set_rate()
on ABE DPLL results eventually in a clk_set_rate() call on USB DPLL,
because CCF does a clk_change_rate() (as part of clk_set_rate()) on
all downstream clocks resulting from a rate change on the top clock.
So its important that we lock USB DPLL before we lock ABE DPLL.
Without which we see these error logs at boot.
[These error logs will not be seen if using a bootloader that locks
USB DPLL]
[ 0.000000] clock: dpll_usb_ck failed transition to 'locked'
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] Division by zero in kernel.
[ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7
[ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14)
[ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10)
[ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114)
[ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8)
[ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8)
[ 0.000000] clock: trace_clk_div_ck: could not find divisor for target rate 0 for parent pmd_trace_clk_mux_ck
[ 0.000000] Division by zero in kernel.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
In the original hwmod data file, DebugSS entry was disabled,
since we didn't (and do not) have SW to control it.
This patch enables it back with right data, so that it can be
controlled by different ways; and the suggested method it to
have modular driver for debugSS as well.
Refer to the link for more discussion on handling of debugSS -
https://patchwork.kernel.org/patch/2212111/
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Currently, whenever we idle a device _idle_sysc() is called and writes to the
devices SYSCONFIG register to set the idle mode. A lot devices are using the
smart-idle mode and so the write to the SYSCONFIG register is programming the
same value that is already stored in the register.
Writes to the devices SYSCONFIG register can be slow, for example, writing to
the DMTIMER SYSCONFIG register takes 3 interface clock cycles and 3 functional
clock cycles. If the DMTIMER is using the slow 32kHz functional clock this can
take ~100us.
Furthermore, during boot on an OMAP4430 panda board, I see that there are 100
calls to _idle_sysc(), however, only 3 out of the 100 calls actually write
the SYSCONFIG register with a new value.
Therefore, to avoid unnecessary writes to device SYSCONFIG registers when
idling the device, only write the value if the value has changed. It should be
safe to do this on idle as the context of the register will never be lost while
the device is active.
Verified that suspend, CORE off and retention states are working with this
change on OMAP3430 Beagle board.
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
[paul@pwsan.com: updated to apply]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Adding the hwmod data for DRA7XX platforms.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The omap44xx_restart used on omap4 and omap5 devices can be reused
on dra7 devices as well. The device instance however is different
across omap5 and dra7 as compared to omap4. So fix this for omap5
as well as dra7.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
DRA7 belongs to the omap4plus devices which reuse the omap4_pwrdm_operations
ops for powerdomain control. DRA7 however has no VC/VP while all the
earlier omap4plus devices did.
So use the .pwrdm_has_voltdm() ops to pass this info on to the core.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add the data file to describe all power domains inside the DRA7XX SoC.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation to comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add the data file to describe all clock domains inside the DRA7XX SoC
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation to comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add the PRCM MPU registers for DRA7XX platforms
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation to comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
This header contains minimal regbits that are currently used in code.
This header has traditionally been autogenerated on OMAP4+ devices but
the autogenerated contents are largely (95%) unused and hence to reduce
unsued data in the kernel this header has been cut down (from the autogen
output) to whatever is currently needed. This is done by running a cleanup
script on top of the existing autogen script.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Ambresh K <ambresh@ti.com>
[paul@pwsan.com: added generation notation in the comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add the new defines for DRA7XX CM registers.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation in comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add the new defines for DRA7xx prm module registers.
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[paul@pwsan.com: added generation notation in the comments]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
the old codes defined uart0_nostreamctrl_pins, but missed pingroup
and padmux definition for it. this patch fixes it.
Signed-off-by: Qipan Li <Qipan.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
While Midway firmware handles L2 smc calls as nops, the custom smc calls
present a problem when running virtualized Midway guest. They aren't
needed so just avoid calling them.
In the process, cleanup the L2X0 ifdefs and use IS_ENABLED instead.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Move the outer_cache declaration of the CONFIG_OUTER_CACHE ifdef so that
outer_cache can be used inside IS_ENABLED condition.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
commit 40b313608a ("Finally eradicate
CONFIG_HOTPLUG") removed remaining references to CONFIG_HOTPLUG, but missed
a few plain English references in the CONFIG_KEXEC help texts.
Remove them, too.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Acked-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----------------------------
This set of patches add ethernet DT nodes
for DA850 and also remove now unneeded
specification of UART clock frequency so
kernel can now boot irrespective of what
the bootloader setting of UART frequency is.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJSFRjpAAoJEGFBu2jqvgRN0n8P/iHP7wG0dp1O4JOgGYWQoSN7
SXT+cCnwzQoSzuuhHH40ZfGPz+UMiBuvzC77U8gwj77ZMCj0a3thBpTU4MuZKSG3
ePJL+9571FUH6erAybeCvwAew/3lFYbXcnatRDCyZ6drGv3be02uaYqAtYe6xXdJ
lO7rS903M/8eIXzlVVwMNr4zC+//EfbpfGtRyibpemN2rwO1EtPYM/Hr7GKjnxRm
AJ/Z0ODk0Atc/ThSWPzifjEaYnlVh+5VEioVk3HESWTBzWxx0JP+yzK0iWkzRb6g
rnpFPWTz4doKlqO2nUIFFeqL+nrNGzLD8a/TEncvMQP3seFo/rrqf/5mM4M9zxkB
rHAA8MHHHElqSsMOvJLBZ81eUhDVj0SnIihZmzKgJF/EzF+My9c4/BQfwSfbogdw
RaN3/vbdjWenlqWW19tvMqrWiPsHecsolc6kUpRknJhpfk/f5pJjCEGBiWdHHTYh
qX9yjtwXvxQR2jM/UOTZIIR+En9thWffzeJSo6p9rEr+bPuK+N2U05t8O/KsLom1
i7FvMFQA5Jg3vHfMZo6gSMgPzFrsPm7yxECllwXbuBs2xYTAXgzSXwttqsGgH8pE
iUyAGnHgi5ke2b9qTsy5iyWO/1VDFLaY+ohoR7AVKx126wQAkCx4XNz/7yl2YArZ
10dBn4oxPi+6Zcwk9gbT
=7jwl
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v3.12/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc
From Sekhar Nori:
DaVinci DT updates for v3.12
----------------------------
This set of patches add ethernet DT nodes
for DA850 and also remove now unneeded
specification of UART clock frequency so
kernel can now boot irrespective of what
the bootloader setting of UART frequency is.
* tag 'davinci-for-v3.12/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: da850: do not specify clock_frequency for UART DT node
ARM: davinci: da850: add DT node for ethernet
ARM: davinci: da850: add OF_DEV_AUXDATA entry for davinci_emac
ARM: davinci: da850: add OF_DEV_AUXDATA entry for mdio.
ARM: davinci: da850: add DT node for mdio device
Signed-off-by: Kevin Hilman <khilman@linaro.org>
-----------------------------
This set of SoC updates contains changes to the
way UART clock is handled to enabled DT-boot to
obtain UART clock frequency instead of relying
on DT-binding being supplied. Similarly handling
of MDIO clock is fixed to make it easier to support
MDIO in DT-boot. Finally there is patch to remove
now unnecessary setting of wake-up capable flag for
RTC.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iQIcBAABAgAGBQJSFRb7AAoJEGFBu2jqvgRNEqMP/A60R4Zuj5sW7WAnAqySMTzH
nPFwkuDTelDP1s2TdXgHHN7X6IeIiG0LjH0s/qdoYQbFA9FIoZFxBJ10G/P7hXWe
R6mFLQFFP/EpdHelw5EGDnsxCrG+7GG68taACqxKdw+gz7FgbLjfpBveCf0+cGD2
otpLBHa8ohqDwsWj+uxLm4rJaZhZMHZRUsp/omXnRxBLIO8IX1f80P31pM4wx1Mq
7V2oUs7cv2jMGb/kQ6+bRRKCcLNVBbJ2hRh7fFQ+WWt1nhwURljkNfuw4S31a20t
IBF4ODVL+LBW3qLiikWcCTZAfHlFUzVAh9LV64ECsJQO+9p/GZYWNAYG6/ylylAU
W3vpppeuDTEj5/UqVcp71uR4D0wD5L0sD8bYvP4sAoHZ+0peEJxs5oek1SAQ+QiF
1q+YbTJjWcvQsBEQpw9bXC/oc/fFwpY0TaUHX4GTFfTOV0yueOUnv9wQJQ6WUvfW
3FjVLLZFFrA0Cgbuk0P6alIED4shzX92vUdnuVGoydeBdBtYCYjAoTend1hGNVzk
GR1gJUK2lPGSAAytxIkWRIe7zKYRZYfHQAQ0TriWt93JGVdEXASP5d1qI2m+a2Gb
qWaFlfMVDzaKh35XfquwDE7nL6tHo8Pn9ft1avjeqTStb6ep/DzAg1EEfPtN3Ms3
X8660xNwOKSYgpJrYRIS
=e6I8
-----END PGP SIGNATURE-----
Merge tag 'davinci-for-v3.12/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc
From Sekhar Nori:
DaVinci SoC updates for v3.12
-----------------------------
This set of SoC updates contains changes to the
way UART clock is handled to enabled DT-boot to
obtain UART clock frequency instead of relying
on DT-binding being supplied. Similarly handling
of MDIO clock is fixed to make it easier to support
MDIO in DT-boot. Finally there is patch to remove
now unnecessary setting of wake-up capable flag for
RTC.
* tag 'davinci-for-v3.12/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
ARM: davinci: fix clock lookup for mdio device
ARM: davinci: da8xx: remove hard coding of rtc device wakeup
ARM: davinci: serial: remove davinci_serial_setup_clk()
ARM: davinci: serial: get rid of davinci_uart_config
ARM: davinci: da8xx: remove da8xx_uart_clk_enable
ARM: davinci: uart: move to devid based clk_get
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- sound support for at91sam9x5 family
- at91sam9n12: touch button, i2c and gpio-keys
- adding missing pinctrl-names to MCI on at91rm9200 and at91sam9260/9g20
- adding ARM Performance Monitor Unit (PMU) on sama5d3
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJSFNWxAAoJEAf03oE53VmQRHQH/Rh/nMykzGwgOX71gHW1SPkc
ShM7Pu5OdCXeQc0wdLlWcxyPyynhCxgLaO+GPEzDeVVw18SArMX+yqceiUSk521L
rOqIxtjCgJE9BTjdOfz2Xs9O0KdUxHuCH2sodoFlOppxN8HYBXCXwryjrqOXtImF
svFICn9yC3MvJppyYRfp4pmMZpjB2Ay2nqYnf/Uf59mzwGlHrMSdEC1HtpKGlCI1
DnVeF16TEoBeT0GL1tpv3G9vKxS13jxRuuMeIOcNfHxfINNfIlZO1EXibUpbS5Ed
pUZ+BlBLmz9xooilpSmJ7VSh1AcviixI5z2EcniVXcH7ajWsU4ZOuhf+YyqBmZY=
=gOB4
-----END PGP SIGNATURE-----
Merge tag 'at91-dt' of git://github.com/at91linux/linux-at91 into next/dt
From Nicolas Ferre:
More DT work on AT91:
- sound support for at91sam9x5 family
- at91sam9n12: touch button, i2c and gpio-keys
- adding missing pinctrl-names to MCI on at91rm9200 and at91sam9260/9g20
- adding ARM Performance Monitor Unit (PMU) on sama5d3
* tag 'at91-dt' of git://github.com/at91linux/linux-at91:
ARM: at91/dt: sam9x5ek: add sound configuration
ARM: at91/dt: sam9x5ek: enable SSC
ARM: at91/dt: sam9x5ek: add WM8731 codec
ARM: at91/dt: sam9x5: add SSC DMA parameters
ARM: at91/dt: add at91rm9200 PQFP package version
ARM: at91: at91rm9200: set default mmc0 pinctrl-names
ARM: at91: at91sam9n12: correct pin number of gpio-key
ARM: at91: at91sam9n12: add qt1070 support
ARM: at91: at91sam9n12: add pinctrl of TWI
ARM: at91: Add PMU support for sama5d3
ARM: at91: at91sam9260: add missing pinctrl-names on mmc
Signed-off-by: Kevin Hilman <khilman@linaro.org>
A handful of fixes for 3.11 are still trickling in. These are:
- A couple of fixes for older OMAP platforms
- Another few fixes for at91 (lateish due to European summer vacations)
- A late-found problem with USB on Tegra, fix is to keep VBUS regulator
on at all times
- One fix for Exynos 5440 dealing with CPU detection
- One MAINTAINERS update
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSFbbrAAoJEIwa5zzehBx3J3EP/3iaagsR0S9Ya8V+11tquVMQ
5S6xF7BQddJRiM1wVwkApDXHCVEiNfKs2AAh6aFQTZhHF+2hXFY80afFSCon52tx
same+gTJw5qsuxrDfFTfBwuyv/cAqGnfAx+EV8nHDPk3vcC62xfLbLemvBWFu+sz
jXwhmbGmqxOffHiAAaXEbz01YYq1BQeRvm9dTXStJGmcyUomG+73DV8CSs2gKUEU
vC7MRj1yYDRtuwkEKdHN3IDfyWpwzgYi5iS1nL1OI0MP+6Jt2dLa+j7uALXKV+f/
R3KOkJRXBQ1W+kCd0DbiyORd9sGOM1rzHPYQF0XqtgdoYGzcQ/2B53OlFaoPBkvs
Y+Z+B3OZZChLeZRy520x5hi5NkdVq3kcH377rND+w01ss4KFfttjb9Y0rpJ6kqaG
L61ElFF6TGiU5WVU079gR+zVGNKhG4hZrtPvkyfHA9wN7KX5lin0BUuvX7hmFu3o
bcF5TkcT30hIGSsvwa+DAsAsyirehuClu3QK0Val9OpZJ01Z8h/amFAjVXz/Y6N9
xQokQ1LsttwBG/rkniahEy00Vda2sE9PXlPzopHclytq5JyiUs6zdR7nUHhyTXIM
xpvnxV1CrGZGoNr3J9yzdKiGuw6q7kbjsOR7vwY9nH+BniFpG8YDm418UrhsN3cp
IRo0ZDIIXlcZCyKrRl5F
=NVob
-----END PGP SIGNATURE-----
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A handful of fixes for 3.11 are still trickling in. These are:
- A couple of fixes for older OMAP platforms
- Another few fixes for at91 (lateish due to European summer
vacations)
- A late-found problem with USB on Tegra, fix is to keep VBUS
regulator on at all times
- One fix for Exynos 5440 dealing with CPU detection
- One MAINTAINERS update"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: tegra: always enable USB VBUS regulators
ARM: davinci: nand: specify ecc strength
ARM: OMAP: rx51: change musb mode to OTG
ARM: OMAP2: fix musb usage for n8x0
MAINTAINERS: Update email address for Benoit Cousson
ARM: at91/DT: fix at91sam9n12ek memory node
ARM: at91: add missing uart clocks DT entries
ARM: SAMSUNG: fix to support for missing cpu specific map_io
ARM: at91/DT: at91sam9x5ek: fix USB host property to enable port C
- Add support for restart using the PRCMU
- Move secondary startup out of INIT section
- set coherent_dma_mask for DMA40
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.13 (GNU/Linux)
iQIcBAABAgAGBQJSEoUjAAoJEEEQszewGV1zDvQP/2wdMMY4Y89SgJEbik3laGTY
WYe2rDXaXomsmALRyyhjbfIa4qhEr70ij9pXw+aEisGVDxUmDPrUKcsUwIfASofQ
NWjnVDhRdfUPeIfXhMfCMJebuUqqggV/rpY3zsy+4ktBbsYDjqUTcCwWxmGDW/TM
HyJ6jx9Ifc24M8yW9r+4EheOb6rhKLOtx08QsPwf0S3mh2JoiHr5RM7XV8ng+LPS
3IcFAxLeNbPu7kgW9mwWaZuQ0G0SPFAT5oxzLJlfKbV94caz85UctP62seHlPdia
0iZnYj/s5cxj/hYGeRpLr8P55QPdZjgtNtx2+gm9raVxXeeB8PXdVZH8RLn65LQ6
dy0Fwl9kwL04r3CneUgWcAC9W1GkoBTXlWCrhwYTAHB6ir9TDnbWGoaQTBUYWPJN
rhPYKstCJqcqL1/OKTiPxSqypPJEeFSR9iyHqjCqVBgCVEZqa/rQ32BIIt/+HHoe
SoYWS0S4C5oQXcTKvtde3Fs7Zc4MPmF7QjgNaQm71uPtjrSPiiw/He+hTZCHZ2v8
Z/daPM2kwMIyc7ltTdn9wJNSUnFNc8V/e94L0NYcUDzkTTZz8U5VdOqfcfJJO6aX
DoOfroUzC9PTO2+QuuzzA6a3z6l79Ykaw8ggm8Mw/jUQn0JDhJ79SNpJbqqTL1a6
lhz/zV3FFJTGH7cLFyrI
=Yjww
-----END PGP SIGNATURE-----
Merge tag 'ux500-core-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson into next/soc
From Linus Walleij:
Core ux500 changes for v3.12:
- Add support for restart using the PRCMU
- Move secondary startup out of INIT section
- set coherent_dma_mask for DMA40
* tag 'ux500-core-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson:
ARM: ux500: set coherent_dma_mask for dma40
ARM: ux500: remove u8500_secondary_startup from INIT section.
ARM: ux500: add restart support via prcmu
on the original Nomadik instead of using a bit-banged
driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.13 (GNU/Linux)
iQIcBAABAgAGBQJSEeneAAoJEEEQszewGV1zNPcQAJCmBeQ6xmz5yD149f8EMsM/
9nI2/cDPpGfP4V/KoJREY45K4v4tsUlZsT28PksdIQHFw+ZjowIzIQQ6AeHrFKpl
AV1gTkQyXV/Lee4wSh0f7ELbA01+HAbz1P1komdGzHQU9maOtq43bwxlp+iVmxHs
J7GyF5saFKL124utoY8lhYll9rlTALZT6rV3pv5GnHrDBg8fGqLopzhmAlXkFf6i
pwwFYEMAUMcv431xEVa7eGAXCccNSIjrulRuJc0bnphMOyOHYTGKyv0dujdq8yQA
uwkn4eGLS0f+MCBgw3RamtZDl0lH5Rj5LsWk3ZIS23AmEpAnxAMA2/uxG207bHgV
jAbfgXTp/K7LfA0HfINJZZ1e2RhCpNReNR1ylcaHnlsVTGZJmEgtXauVE76nSRME
SBV2GPgMsZzU8Wm2K7OFaoxsT5ytL0gxxpOilyKvawxlDv6nSGrtyqYpUYIcWNCL
zW5/DuWwFGZc7IXmizSBArFhg67BLveO2qDsUrNI+4aQrNIvvaNDiUazAv6CCXAr
bN9xZ0IpdNKl8nKvuqAEBwrDoYNLNdLY7gaI8aBd5kacrWj0/LzukP+zVG6WqNIb
bM5oT/O7a4CJO7zZL5bVEnePg5GLPkz3+qGTRuWuaEJ8HW4BBrwlOR4TjocezRt6
y2c+ThrIWwTX1tq4Kv6W
=jQFd
-----END PGP SIGNATURE-----
Merge tag 'nomadik-i2c-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
From Linus Walleij:
Enables the standard Nomadik I2C driver for use
on the original Nomadik instead of using a bit-banged
driver.
* tag 'nomadik-i2c-for-arm-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: nomadik: switch to use the Nomadik I2C driver
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This unmix module/pin definitions and reduce indentation for pin
groups, so makes template a bit cleaner.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
USB OTG vbus pin needs to be configured as gpio function at
sabresd board.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We enabled USB host 1, so host 1's vbus should be on to let
host 1 work.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Patch adds AUDMUX routing for Phytec PCM-038 module.
This route i.MX SSI0 (Port 1) to the slave port 4 where MC13783
codec interface is connected.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
AUDMUX expects additional parameters to be configured correctly,
so turn it off into a template.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The wandboard has a Broadcom 4329 WiFi connected via SDIO. This patch
sets the required pins to enable the wifi module.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
External high frequency clock CKIH1 is optional for i.MX51, so move
it setup into boards where it is used.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
mx53qsb uses GPIO7_8 to turn on VBUS, so add support for it.
Also specify the PHY type in the device tree.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch enables I2C1 and adds device tree nodes for the EEPROM and the
DA9063 PMIC connected to this I2C bus.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
mx6 sabresd boards have a egalax touchscreen controller connected via I2C3.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The ocram on imx6q is 256 KiB while on imx6dl it's 128 KiB. Let's
have separate node for imx6q and imx6dl. It also changes imx6q size
0x3f000 to 0x40000 to match the hardware.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Liu Ying <Ying.Liu@freescale.com>
Outputs regulator SW1A and SW1A, SW2A and SW2B are connected together,
so it determined as "joined" operation for MC13783. Separate work of
these outputs in this case would be wrong, so we define only one of
the outputs.
Additionally, define the full range of voltages for the CPU (1.2v - 1.52v).
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Clock name is not needed for "cpufreq-cpu0".
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
i.MX27 CPU can be clocked with a 32 kHz quartz, and not just 32768 Hz,
so increase "clock-latency" value, which will ensure that we use two
clock cycles on frequency change.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add a label to i.MX27 CPU node. This change allows the reuse this node
in the upper levels of the DTS.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This is useful for testing suspend/resume sequence.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The CLKO is widely used by imx6q board designs to clock audio codec.
Since most codecs accept 24 MHz frequency, let's initially set up CLKO
with OSC24M (cko <-- cko2 <-- osc). Then those board specific CLKO
setup for audio codec can be removed.
The board dts files also need an update on cko reference in codec node.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add support for the imx6q wanboard variant.
Since imx6q/dl are pin to pin compatible, introduce the imx6qdl-wandboard.dtsi
file that contains the common peripheral nodes.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
After mxs-dma driver adopts generic DMA device tree binding, gpmi
channel interrupt number is defined in DMA controller node, and
channel ID is listed in "dmas" property. So the DMA channel interrupt
number in gpmi node "interrupts" property and fsl,gpmi-dma-channel which
are used by old customized DMA binding can be removed now.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Only imx6q has the ahci sata controller, enable
it on imx6q platforms.
Signed-off-by: Richard Zhu <r65037@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds core voltages for i.MX27 CPUs. Only 266 and 400 MHz modes
is documented in the datasheet, so we add a 266 MHz frequency for conform this.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Wandboard has a bluetooth device connected to UART3, so add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Wandboard has a SD card slot on the baseboard connected to SDHC1 and a
BCM4329 (Wifi + Bluetooth chip) connected to SDHC2.
Add support for these ports.
While at it, provide the card detect gpio on SDHC3 and also fix indentation on
MX6QDL_PAD_GPIO_0__CCM_CLKO1 hog pin.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add the dma property for all the uart.
Note: Add the dma property does not mean we enable the dma for this
uart.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add the a new pinctrl for uart3. In the imx6q{dl}-sabreauto boards,
the uart3 is used for Bluetooth.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add more imx6q/dl pin groups for those supported boards, e.g. sabresd,
sabreauto, arm2.
IPU2 pin groups are added into imx6q.dtsi, since the block is only
available on imx6q.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The imx6q and imx6dl are two pin-to-pin compatible SoCs. The same board
design can work with either chip plugged into the socket, e.g. sabresd
and sabreauto boards.
We currently define pin groups in imx6q.dtsi and imx6dl.dtsi
respectively because the pad macro names are different between two
chips. This brings a maintenance burden on having the same label point
to the same pin group defined in two places.
The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs
pad macro names. Then the pin groups becomes completely common between
imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the
long term maintenance of imx6q/dt pin settings becomes easier.
Unfortunately, the change brings some dramatic diff stat, but it's all
about DTS file, and the ultimate net diff stat is good.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
enable the uart2 for imx6q-arm2 board.
The uart2 works in the DTE mode, with the RTS/CTS and DMA enabled.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
In the arm2 board, the UART2 works in the dte mode.
So add a pinctrl for both the imx6q{dl} boards.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The uart2 in the imx6q-arm2 board is used as a DTE uart,
this patch adds the necessary DTE pads for uart2.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
In order to enable the DMA for some uart port in imx6sl, we add the
"fsl,imx6q-uart" to the uart's compatible property.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Both buses are not used on the phyCARD-S module. This patch moves them
to the rdk file. Remove ioexpander.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This sensor was introduced in the original pca100 board file, but
phyCARD-S SOM and RDK do not have a temperature sensor.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
To make it consistent with the other i.mx SoCs, let's add the cpus nodes.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Fixup of commit "ARM: dts: Add device tree support for phycard pca100".
Remove wrong I2C RTC node.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds CAN (NXP SJA1000) node for Phytec PCM-970 RDK.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch adds WEIM node for Phytec PCM-038 module.
Migrate existing on-module NOR-flash as children of WEIM CS0.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch moves IIM node under AIPI2 bus, since this is proper
location for this module.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add the #dma-cells property for all the sdma in all the imx platforms.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
i.MX6DL does not have the second IPU, but the LVDS multiplexers can connect
either LVDS channel of the LDB to IPU1 DI0 or IPU1 DI1.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
[shawn.guo: remove "crtcs" property from imx6qdl.dtsi]
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch enables the On-Chip SRAM (OCRAM) on i.MX53 and i.MX6 SoCs.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Board files for Phytec phyCARD-S "System on Module" and "Rapid
Development Kit".
Based on patches from:
Steffen Trumtrar <s.trumtrar@pengutronix.de>:
- Original patch
- ARM: dts: Set partition offsets for phycard
- ARM: dts: Use CSPI1 instead of CSPI2 on phycard pca100
- ARM: imx27-phytec-phycard-S.dts: resize nand partitions
Jan Luebbe <jlu@pengutronix.de>:
- ARM: dts: Enable bad block table in NAND
Cc: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Jan Luebbe <jlu@pengutronix.de>
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Set operating-points for imx27. There is no regulator support, so the
voltages are 0. The frequencies should be the same for all imx27 boards,
so it is defined here and can be overwritten if necessary.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
On the MX27 Reference Manual the interrupt controller is named AITC:
ARM926EJ-S Interrupt Controller
So use the AITC term instead of AVIC.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Origin: id:1334193132-18944-2-git-send-email-festevam@gmail.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The mc13892 driver knows that it needs spi-cs-high, so the mc13892
will work. The dataflash also connected to this bus though can only
be probed when the mc13892 is inactive. Due to driver potential
differences in the probe order we can only make sure the mc13892
is inactive when we put the information into the devicetree.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
For keeping the alphabetical order in the pinmux nodes.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6 gpt is handled by the i.MX31 gpt driver in the kernel,
so add a corresponding compatible entry.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The i.MX6Q and i.MX6DL are pin compatible, so the pinmux entries
should be in sync. This patch systematically adds the pinmux entries
missing from the imx6q to the imx6dl file.
Some name inconsistencies and whitespace damage is fixed along the
way.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
