Commit Graph

4259 Commits

Author SHA1 Message Date
Stephen Boyd
faa865f18c clk/samsung updates for v4.15
Overall clk/samsung clean up and fixes. Removed remaining unused code
 after removal of exynos4212 SoC support; dropped internal data structure
 fields and related code for registering clkdev lookup entry for each
 possible clock object, clkdev aliases could still be defined if needed
 in a separate table; other minor fixes of the clock tree definitions.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABCAAGBQJZ4K7OAAoJEE1bIKeAnHqLlFUP/12Mnb3KIeO4WvNewZupUETd
 2BWpPHMS/4Al216I+RAZIgBU5lxx9xv0lMUeSfOWXwPMh/xReCY3SQ3N11KTE6DW
 6PwZpXtkYUyJ9sakVMNonczljfuWKFleRBscqPy3DH2S1vzG611lmmE8QvMmie2O
 shKrRQOwN7lWIGSQFdu1aSa/9OsHM9xsmgGGcAWMcpXTm26/nZ4EZxd7OU3nB39G
 fBzqjIP8hrvDKUi4b4+5uQxaXTYN8HKTmteWJzlXtXglVR55Wu7DmXXK4eFDLsmh
 iE3lkUnFK2cgkQjANJeeF/GK19ZvIVjlzEGX66IrAUG8qTDSgLDCWJRxW6qwm9jl
 KrSyC4d1D6GfymcVWUe8drixdeimVpOxyg/FCzyJXA8jkWUfwJJvi4eqJ3inPbh7
 5fv84bTxm4xOhWYOLWu4r0Z9GvxDl/DyeW5tJhkGh7ZSWBWng9f2FDZp9aloJf4K
 DPopqAt5e+8NCe1jyKCNLdDrZxlHp7xyYu+n/xTAVOxS/BZJ+bKvuGIp6b39dzhB
 LMdTwwuwDCneEINROH09FqqH7y+HqyG2vR7cFaiShzP02OE0YGu20WlhRykzajFj
 XhXwfDiGzgTiLjuCS3BbtuYlgFxWAmjo81/3nuJ8MTZYDaXLWuaGCWHYvSc2+oFy
 AiNNDhap38/ed2cLdsgl
 =VHBX
 -----END PGP SIGNATURE-----

Merge tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

Overall clk/samsung clean up and fixes. Removed remaining unused code
after removal of exynos4212 SoC support; dropped internal data structure
fields and related code for registering clkdev lookup entry for each
possible clock object, clkdev aliases could still be defined if needed
in a separate table; other minor fixes of the clock tree definitions.

* tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: Remove obsolete clkdev alias support
  clk: samsung: Add explicit MPLL, EPLL clkdev aliases in S3C2443 driver
  clk: samsung: Rework clkdev alias handling in S3C2443 driver
  clk: samsung: Rework clkdev alias handling in Exynos5440 driver
  clk: samsung: Drop useless alias in Exynos5420 clk driver
  clk: samsung: Remove clkdev alias support in Exynos5250 clk driver
  clk: samsung: Remove double assignment of CLK_ARM_CLK in Exynos4 driver
  clk: samsung: Remove clkdev alias support in Exynos4 clk driver
  clk: samsung: Remove support for obsolete Exynos4212 CPU clock
  clk: samsung: Remove support for Exynos4212 SoCs in Exynos CLKOUT driver
  clk: samsung: Properly propagate flags in __PLL macro
  clk: samsung: Fix m2m scaler clock on Exynos542x
  clk: samsung: Delete a memory allocation error message in clk-cpu.c
2017-10-25 02:37:03 -07:00
Stephen Boyd
f09a6b86fd clk: renesas: Updates for v4.15
- Add support for the new R-Car V3M SoC,
   - Small fixes and cleanups.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJZ1KotAAoJEEgEtLw/Ve77AdgP/23DpYzhjEO4AhCjSqoYRnAM
 Z6OS0a2IaUxmdDgj6czlD0cbILFx75TCFP3byMCjBThd4rQ5P5R0TjY/b+cPicyq
 rWMJc6az2Yh7XzqV/FPTn6t67U8Kqn8du9e99gEnaNUF9GLOjB2BfyIUN8azGY+K
 MuEUwNBXFkw30z7G/iSSWAjQe0CnND8HlU+AHWgeK/4MS9axmyVbHFJyTkgoKgct
 2w3EnpQF+r3cb8whg/FpHF40rRdeU/KmgThPY5BkO+DaOfzDUxpYnZ5IsFY9zvUr
 dEaizgAN0D1Mw8k4peHyroM40Ju8o5t7o95NYNuvp38cfxYLWeox0bwblfJMNsrm
 l08u0NztjsgxGLUA/AAR78yMME0dr5MF/jk7UmIdhwL4KONUb7blCkVuKqWak9Hi
 uriUTO1velm7s7pMIlmLxdrLyE5UP2CtRO/973QsSS9lCjiVcLybJme8ICU0sklm
 2vaqguNm/XDFyTM75nv8yglM9Ksm6ZoEvmgkgtDGlwxzMni9shKsX1f8nEAsiI+T
 gAWXsd0Qz/kkgX0BJiUDa1FgCPCM5BdBAMcmJsT2+ukeUU1KKevcpE5moqEIMl6x
 QboI/2v0XJimxU7lJ8pX2TGNYdY3yO3WQJDhrdyud6pkijPkVNqQOZMtAhy7Xzj4
 pKTkswWsN9+ZSmXpWCs9
 =PTM+
 -----END PGP SIGNATURE-----

Merge tag 'clk-renesas-for-v4.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add support for the new R-Car V3M SoC,
  - Small fixes and cleanups.

* tag 'clk-renesas-for-v4.15-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: rcar-gen2: Delete error message for failed memory allocation
  clk: renesas: mstp: Delete error messages for failed memory allocations
  clk: renesas: cpg-mssr: Add R8A77970 support
  dt-bindings: clock: Add R8A77970 CPG core clock definitions
2017-10-25 02:34:15 -07:00
Marek Szyprowski
a4f21e9ceb clk: samsung: Remove obsolete clkdev alias support
Remove support for obsolete clkdev alias definition in generic helper
macros for MUX, DIV, GATE and PLL clocks. clkdev aliases can be still
created using samsung_clk_register_alias() function if given platform
still needs them. All current drivers have been converted not to use
*_A-style macros and checked if there are any clients for the PLL
clocks, which had aliases created unconditionally.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:34:03 +02:00
Marek Szyprowski
45d882daf8 clk: samsung: Add explicit MPLL, EPLL clkdev aliases in S3C2443 driver
S3C2443 platform still use non-dt based lookup in some of its drivers
to get MPLL and EPLL clocks. Till now it worked only because PLL()
macro implicitly created aliases for all instantiated clocks. This
feature will be removed, so explicitly create aliases for MPLL and
EPLL clocks.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:32:56 +02:00
Marek Szyprowski
cd05417f72 clk: samsung: Rework clkdev alias handling in S3C2443 driver
S3C2443 SoC still uses old, non-dt CPUfreq driver, which requires clkdev
aliases to get access to proper clocks. Create those aliases using
samsung_clk_register_alias() function instead of using *_A clock macros,
which will be removed soon.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:32:26 +02:00
Marek Szyprowski
efea8d3771 clk: samsung: Rework clkdev alias handling in Exynos5440 driver
Exynos5440 still uses old, non-dt CPUfreq driver, which requires clkdev
aliases to get access to proper clocks. Create those aliases using
samsung_clk_register_alias() function instead of using *_A clock macros,
which will be removed soon.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:32:09 +02:00
Marek Szyprowski
36ba48240b clk: samsung: Drop useless alias in Exynos5420 clk driver
Drop clkdev alias for "mout_aclk400_mscl" clock. It was not used at all
and it was probably committed by accident.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:31:49 +02:00
Marek Szyprowski
29964890f3 clk: samsung: Remove clkdev alias support in Exynos5250 clk driver
All Exynos5250 boards have been fully converted to device-tree and use
generic dt-based CPUfreq driver, so there is no need to create any clkdev
aliases for the clocks. Drop all the code related to aliases handling.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:31:29 +02:00
Marek Szyprowski
6de08891c8 clk: samsung: Remove double assignment of CLK_ARM_CLK in Exynos4 driver
CLK_ARM_CLK ("armclk") clock is provided by cpu-clk subdriver, which is
instantiated after creating all divider clocks from exynos4_div_clks
array. There is no point assigning this id to "div_core2" clock and later
overwrite with proper "armcpu" clock by cpu-clk subdriver.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:30:05 +02:00
Marek Szyprowski
58f4a5ff3a clk: samsung: Remove clkdev alias support in Exynos4 clk driver
All Exynos4 boards have been fully converted to device-tree and use generic
dt-based CPUfreq driver, so there is no need to create any clkdev aliases
for the clocks. Drop all the code related to aliases handling.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:29:41 +02:00
Marek Szyprowski
c9194fb623 clk: samsung: Remove support for obsolete Exynos4212 CPU clock
Support for Exynos 4212 SoC has been removed by commit bca9085e0a ("ARM:
dts: exynos: remove Exynos4212 support (dead code)"), so there is no need
to keep dead code.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:29:28 +02:00
Marek Szyprowski
d5cd103b06 clk: samsung: Remove support for Exynos4212 SoCs in Exynos CLKOUT driver
Support for Exynos4212 SoCs has been removed by commit bca9085e0a ("ARM:
dts: exynos: remove Exynos4212 support (dead code)"), so there is no need
to keep remaining dead code related to this SoC version.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-09 11:29:16 +02:00
Stephen Boyd
0a4e632b6f Merge branch 'clk-fixes' into clk-next
* clk-fixes:
  clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle
2017-10-05 16:52:59 -07:00
Marek Szyprowski
5dcbeca615 clk: samsung: exynos4: Enable VPLL and EPLL clocks for suspend/resume cycle
Commit 6edfa11cb3 ("clk: samsung: Add enable/disable operation for
PLL36XX clocks") added enable/disable operations to PLL clocks. Prior that
VPLL and EPPL clocks were always enabled because the enable bit was never
touched. Those clocks have to be enabled during suspend/resume cycle,
because otherwise board fails to enter sleep mode. This patch enables them
unconditionally before entering system suspend state. System restore
function will set them to the previous state saved in the register cache
done before that unconditional enable.

Fixes: 6edfa11cb3 ("clk: samsung: Add enable/disable operation for PLL36XX clocks")
CC: stable@vger.kernel.org # v4.13
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-10-04 09:19:13 -07:00
Marek Szyprowski
61a646e135 clk: samsung: Properly propagate flags in __PLL macro
All users of __PLL macro already provide flags parameter, so don't
overwrite it unconditionally with CLK_GET_RATE_NOCACHE.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-10-03 12:28:27 +02:00
Stephen Boyd
e7cc33358a Merge branch 'clk-pm-runtime' into clk-next
* clk-pm-runtime:
  clk: samsung: exynos-audss: Add support for runtime PM
  clk: samsung: exynos-audss: Use local variable for controller's device
  clk: samsung: exynos5433: Add support for runtime PM
  clk: samsung: Add support for runtime PM
  clk: Add support for runtime PM
2017-09-29 16:07:28 -07:00
Stephen Boyd
79765e9a3d Some smallish fixes for the rk3128 clock support including
some register errors and some clocks that should be critical
 for safe usage.
 -----BEGIN PGP SIGNATURE-----
 
 iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAlnBVUoQHGhlaWtvQHNu
 dGVjaC5kZQAKCRDzpnnJnNEdgTqVB/4p1YFdcTtegPRISCuxHxGo+82Mt4RANWnn
 S9ehHNQd2/WRTqFAdI16sjAxE+opzo9ORBEAsHnocsq7IRAokYvpHWR41d25QLdA
 dwCiwBPbNJbp8lpgir1x0d8WZ2KbeIP0KUVNvh2AHX2eRBpXcpXfpklC12v9dkVO
 JVFfPWKeiT57PKvdpaXkAdTfF/uBaCwe436jfZCy/HUTICuj9/uSYz1ssdFe1/Lj
 BuT2Gk+kSgv9b7bjTOmnDEWcloNRHi/2WrEThKQE4T2+QEMzsAhgAKNjQJyD0lWC
 WDxFMEi3b7oXuzgM7I33OwjnSDFn7BUXJ3yu1hXhCaTkAAiq4UsW
 =3tp4
 -----END PGP SIGNATURE-----

Merge tag 'v4.14-rockchip-clkfixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes

Pull Rockchip clk driver fixes from Heiko Stuebner:

Some smallish fixes for the rk3128 clock support including
some register errors and some clocks that should be critical
for safe usage.

* tag 'v4.14-rockchip-clkfixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  clk: rockchip: add sclk_timer5 as critical clock on rk3128
  clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error
  clk: rockchip: add pclk_pmu as critical clock on rk3128
2017-09-29 14:17:51 -07:00
Bjorn Andersson
9792bf5ad5 clk: Export clk_bulk_prepare()
Allow clk_bulk_prepare() to be referenced by kernel modules by adding
the missing EXPORT_SYMBOL_GPL().

Fixes: 266e4e9d91 ("clk: add clk_bulk_get accessories")
Reported-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-29 14:17:17 -07:00
Andrzej Pietrasiewicz
c07c1a0f68 clk: samsung: Fix m2m scaler clock on Exynos542x
The TOP "aclk400_mscl" clock should be kept enabled all the time
to allow proper access to power management control for MSC power
domain and devices that are a part of it. This change is required
for the scaler to work properly after domain power on/off sequence.

Fixes: 318fa46cc6 ("clk/samsung: exynos542x: mark some clocks as critical")
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-09-29 10:34:35 +02:00
Markus Elfring
b4021bbe10 clk: renesas: rcar-gen2: Delete error message for failed memory allocation
The script "checkpatch.pl" pointed information out like the following.

WARNING: Possible unnecessary 'out of memory' message

Thus fix affected source code places.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-09-28 17:57:34 +02:00
Markus Elfring
168bcbcb1c clk: renesas: mstp: Delete error messages for failed memory allocations
The script "checkpatch.pl" pointed information out like the following.

WARNING: Possible unnecessary 'out of memory' message

Thus fix affected source code places.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-09-28 17:57:34 +02:00
Markus Elfring
8834b09501 clk: samsung: Delete a memory allocation error message in clk-cpu.c
Omit an extra message for a memory allocation failure
in exynos_register_cpu_clock() function.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2017-09-27 17:06:18 +02:00
Sergei Shtylyov
8d46e28fb5 clk: renesas: cpg-mssr: Add R8A77970 support
Add R-Car V3M (R8A77970) Clock Pulse Generator / Module Standby and
Software Reset support, using the CPG/MSSR driver core and the common
R-Car Gen3 code.

Based on the original (and large) patch by Daisuke Matsushita
<daisuke.matsushita.ns@hitachi.com>.

Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2017-09-19 10:57:35 +02:00
Elaine Zhang
00e6751ffc clk: rockchip: add sclk_timer5 as critical clock on rk3128
sclk_timer5 is for arm arch counter, so need always on.
but no dts node to handle this clk, so make it as critical clock

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-17 01:55:36 +02:00
Elaine Zhang
a4eb286565 clk: rockchip: fix up rk3128 pvtm and mipi_24m gate regs error
A copy-paste error made them use the wrong bits in the register.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-17 01:55:36 +02:00
Elaine Zhang
e8620acc90 clk: rockchip: add pclk_pmu as critical clock on rk3128
pclk_pmu need always on, and no dts node to handle this clk,
so make it as critical clock

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2017-09-17 01:55:36 +02:00
Linus Torvalds
f60a2abfdb The diff is dominated by the Allwinner A10/A20 SoCs getting converted to
the sunxi-ng framework. Otherwise, the heavy hitters are various drivers
 for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are some other
 new clk drivers in here too but overall this is just a bunch of clk
 drivers for various different pieces of hardware and a collection of
 non-critical fixes for clk drivers.
 
 New Drivers:
  - Allwinner R40 SoCs
  - Renesas R-Car Gen3 USB 2.0 clock selector PHY
  - Atmel AT91 audio PLL
  - Uniphier PXs3 SoCs
  - ARC HSDK Board PLLs
  - AXS10X Board PLLs
  - STMicroelectronics STM32H743 SoCs
 
 Removed Drivers:
  - Non-compiling mb86s7x support
 
 Updates:
  - Allwinner A10/A20 SoCs converted to sunxi-ng framework
  - Allwinner H3 CPU clk fixes
  - Renesas R-Car D3 SoC
  - Renesas V2H and M3-W modules
  - Samsung Exynos5420/5422/5800 audio fixes
  - Rockchip fractional clk approximation fixes
  - Rockchip rk3126 SoC support within the rk3128 driver
  - Amlogic gxbb CEC32 and sd_emmc clks
  - Amlogic meson8b reset controller support
  - IDT VersaClock 5P49V5925/5P49V6901 support
  - Qualcomm MSM8996 SMMU clks
  - Various 'const' applications for struct clk_ops
  - si5351 PLL reset bugfix
  - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
  - Assorted Tegra clk driver fixes
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iQIcBAABCAAGBQJZuIAQAAoJEK0CiJfG5JUlUMQQAKFwCZRfTzz0m9jJ9s1XZSR/
 vldNAEUGm+Mz0W84xIzFqaT0UI1+SJK4e9Du+EN6phcCD5yVB0JS2EtRa84Bku/i
 Zy6AYSUNbGjx94HPwIq1hKt+UOIfBiNbJKMnkoCbEyYPA/TiWzr8JR5GyLjwYhPq
 IZHSvKqUKM3h2nr+MtpFJIIk8DlkLARRca4CCqa5i2Oqj6B8rjQQAq7TaLAM3ASN
 tSFIW2vdmWD+om2L57WHhwBgaYnUB4jBCRWkFZRsO4ZIRgm4VpePmosy2UTZ7fqb
 kEaW2bPuv65zUHpvjHG6yXo+yh0yk1fBsXG/joXgJ4oOmNzsIgnCZzPnGUC1ccms
 QdK/qhdIXsdgiR2DZtYuzUHji8+TNIPPjfAFyJjUwxDBXpqzXvsvltx2a1hg/rUP
 VDvTL2OnoGtrW2bXPufCkxBsyejJ4RqC5riMJws5xgMkqKKUajiLovPeuL6+8kU+
 ncqWYiIkEvHNKpmW511G/g+ClLk89zgXfxKFWWR+iDjSvA0hgaiRj1V3C2HIyS8f
 CLpalf6ao2+O008rUiaiqJyxWuwLujcdYokay2HXvTYc45rXrVwvlaDajxqs2eer
 lekUA4ZbX2g6qvB0lna6PNlv8JLQ1XPdzhWD2eeQIi7JgVSgwg++kUJqglsuai56
 eg5zNo6891GL9zFW10/A
 =0JbT
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "The diff is dominated by the Allwinner A10/A20 SoCs getting converted
  to the sunxi-ng framework. Otherwise, the heavy hitters are various
  drivers for SoCs like AT91, Amlogic, Renesas, and Rockchip. There are
  some other new clk drivers in here too but overall this is just a
  bunch of clk drivers for various different pieces of hardware and a
  collection of non-critical fixes for clk drivers.

  New Drivers:
   - Allwinner R40 SoCs
   - Renesas R-Car Gen3 USB 2.0 clock selector PHY
   - Atmel AT91 audio PLL
   - Uniphier PXs3 SoCs
   - ARC HSDK Board PLLs
   - AXS10X Board PLLs
   - STMicroelectronics STM32H743 SoCs

  Removed Drivers:
   - Non-compiling mb86s7x support

  Updates:
   - Allwinner A10/A20 SoCs converted to sunxi-ng framework
   - Allwinner H3 CPU clk fixes
   - Renesas R-Car D3 SoC
   - Renesas V2H and M3-W modules
   - Samsung Exynos5420/5422/5800 audio fixes
   - Rockchip fractional clk approximation fixes
   - Rockchip rk3126 SoC support within the rk3128 driver
   - Amlogic gxbb CEC32 and sd_emmc clks
   - Amlogic meson8b reset controller support
   - IDT VersaClock 5P49V5925/5P49V6901 support
   - Qualcomm MSM8996 SMMU clks
   - Various 'const' applications for struct clk_ops
   - si5351 PLL reset bugfix
   - Uniphier audio on LD11/LD20 and ethernet support on LD11/LD20/Pro4/PXs2
   - Assorted Tegra clk driver fixes"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (120 commits)
  clk: si5351: fix PLL reset
  ASoC: atmel-classd: remove aclk clock
  ASoC: atmel-classd: remove aclk clock from DT binding
  clk: at91: clk-generated: make gclk determine audio_pll rate
  clk: at91: clk-generated: create function to find best_diff
  clk: at91: add audio pll clock drivers
  dt-bindings: clk: at91: add audio plls to the compatible list
  clk: at91: clk-generated: remove useless divisor loop
  clk: mb86s7x: Drop non-building driver
  clk: ti: check for null return in strrchr to avoid null dereferencing
  clk: Don't write error code into divider register
  clk: uniphier: add video input subsystem clock
  clk: uniphier: add audio system clock
  clk: stm32h7: Add stm32h743 clock driver
  clk: gate: expose clk_gate_ops::is_enabled
  clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()
  clk: uniphier: add PXs3 clock data
  clk: hi6220: change watchdog clock source
  clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808
  clk: cs2000: Add cs2000_set_saved_rate
  ...
2017-09-13 11:04:14 -07:00
Linus Torvalds
e90937e756 ARM: arm64: Devicetree updates for v4.14
As usual, device tree updates is the bulk of our material in this merge
 window. This time around, 559 patches affecting both 32- and 64-bit
 platforms.
 
 Changes are too many to list individually, but some of the larger ones:
 
 New platform/SoC support:
 
  - Automotive:
    + Renesas R-Car D3 (R8A77995)
    + TI DT76x
    + MediaTek mt2712e
  - Communication-oriented:
    + Qualcomm IPQ8074
    + Broadcom Stingray
    + Marvell Armada 8080
  - Set top box:
    + Uniphier PXs3
 
 Besides some vendor reference boards for the SoC above, there are also several
 new boards/machines:
 
  - TI AM335x Moxa UC-8100-ME-T open platform
  - TI AM57xx Beaglebone X15 Rev C
  - Microchip/Atmel sama5d27 SoM1 EK
  - Broadcom Raspberry Pi Zero W
  - Gemini-based D-Link DIR-685 router
  - Freescale i.MX6:
    + Toradex Apalis module + Apalis and Ixora carrier boards
    + Engicam GEAM6UL Starter Kit
  - Freescale i.MX53-based Beckhoff CX9020 Embedded PC
  - Mediatek mt7623-based BananaPi R2
  - Several Allwinner-based single-board computers:
   + Cubietruck plus
   + Bananapi M3, M2M and M64
   + NanoPi A64
   + A64-OLinuXino
   + Pine64
  - Rockchip RK3328 Pine64/Rock64 board support
  - Rockchip RK3399 boards:
   + RK3399 Sapphire module on Excavator carrier (RK3399 reference design)
   + Theobroma Systems RK3399-Q7 SoM
  - ZTE ZX296718 PCBOX Board
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJZtdtjAAoJEIwa5zzehBx3PzgP/iCQyUk5wklG9E5YNl8a9m/o
 djBkelabTm52s5ZTu6Awsq5rx8jUMqcb0vo+9v9yPWFG6On2oTZyZ/rE1Wbj3+gG
 +ENVyRgxmzYDTXqQLiu1UOV9wSA0gHwQCRZvE7i32NNfLu+tAsvu9e/AuznQ1xhR
 4G7dGCRRlRkZkrVKrJ7JjklmW578pFQkZLmz8K2nWqwh1tKpK3fY19SrwUKx+YCR
 tnMPYAPjB5zxR9tfcDS4FUKdiC7dMiMzZNGiYl5a26X6wsNR7xYtNzFMaGZn1ecG
 PwOS+DAnj8J+AfpQBLWu9xytHbJdqITRuNcF+OXNVW9TKmb0syf7VgRUDkhjIMxP
 aGZc4Q6PwgTRwnX+w6fTzJTyk+uXtieCicZaaZ1jlgcQq0pfbzJ1vZMpq4aoVlxU
 mS84i1bd8AiavmHuyIRNB3/T4aAsVhTUIBndXluKV8yWroXhAukfI1YmGr1Eux7C
 fy5pPeDqk9lXR3bqIhfnaLoVsApEXTOWMC8X48vwfaQHiCGR9JJwpfsGcaNi1bri
 Col1qRzkXWGA6KqTWtpo+o12rYuMGc0mpZTCmejKuBoxMXOU+wLyJYgaxa7pyesX
 S5rLaIe2l9ppXHjjEERp7AzczzLS5W20Tez5vYnZAQb1dYuJzwXwiATt8NT+XG3V
 Wu92UwUfjxYk8vGz48ph
 =R45j
 -----END PGP SIGNATURE-----

Merge tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM/arm64 Devicetree updates from Olof Johansson:
 "As usual, device tree updates is the bulk of our material in this
  merge window. This time around, 559 patches affecting both 32- and
  64-bit platforms.

  Changes are too many to list individually, but some of the larger
  ones:

  New platform/SoC support:

   - Automotive:
     + Renesas R-Car D3 (R8A77995)
     + TI DT76x
     + MediaTek mt2712e
   - Communication-oriented:
     + Qualcomm IPQ8074
     + Broadcom Stingray
     + Marvell Armada 8080
   - Set top box:
     + Uniphier PXs3

  Besides some vendor reference boards for the SoC above, there are also
  several new boards/machines:

   - TI AM335x Moxa UC-8100-ME-T open platform
   - TI AM57xx Beaglebone X15 Rev C
   - Microchip/Atmel sama5d27 SoM1 EK
   - Broadcom Raspberry Pi Zero W
   - Gemini-based D-Link DIR-685 router
   - Freescale i.MX6:
     + Toradex Apalis module + Apalis and Ixora carrier boards
     + Engicam GEAM6UL Starter Kit
   - Freescale i.MX53-based Beckhoff CX9020 Embedded PC
   - Mediatek mt7623-based BananaPi R2
   - Several Allwinner-based single-board computers:
  + Cubietruck plus
  + Bananapi M3, M2M and M64
  + NanoPi A64
  + A64-OLinuXino
  + Pine64
   - Rockchip RK3328 Pine64/Rock64 board support
   - Rockchip RK3399 boards:
  + RK3399 Sapphire module on Excavator carrier (RK3399 reference design)
  + Theobroma Systems RK3399-Q7 SoM
   - ZTE ZX296718 PCBOX Board"

* tag 'armsoc-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (559 commits)
  ARM: dts: at91: at91sam9g45: add AC97
  arm64: dts: marvell: mcbin: enable more networking ports
  arm64: dts: marvell: add a reference to the sysctrl syscon in the ppv2 node
  arm64: dts: marvell: add TX interrupts for PPv2.2
  arm64: dts: uniphier: add PXs3 SoC support
  ARM: dts: uniphier: add pinctrl groups of ethernet phy mode
  ARM: dts: uniphier: fix size of sdctrl nodes
  ARM: dts: uniphier: add AIDET nodes
  arm64: dts: uniphier: fix size of sdctrl node
  arm64: dts: uniphier: add AIDET nodes
  Revert "ARM: dts: sun8i: h3: Enable dwmac-sun8i on the Beelink X2"
  arm64: dts: uniphier: add reset controller node of analog amplifier
  arm64: dts: marvell: add Device Tree files for Armada-8KP
  arm64: dts: rockchip: add Haikou baseboard with RK3399-Q7 SoM
  arm64: dts: rockchip: add RK3399-Q7 (Puma) SoM
  dt-bindings: add rk3399-q7 SoM
  ARM: dts: rockchip: enable usb for rv1108-evb
  ARM: dts: rockchip: add usb nodes for rv1108 SoCs
  dt-bindings: update grf-binding for rv1108 SoCs
  ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers
  ...
2017-09-10 20:54:48 -07:00
Marek Szyprowski
ae432a9b31 clk: samsung: exynos-audss: Add support for runtime PM
This patch adds support for runtime PM to Exynos Audio SubSystem driver to
enable full support for audio power domain on Exynos5 SoCs. The main change
is moving register saving and restoring code from system sleep PM ops to
runtime PM ops and implementing system sleep PM ops with generic
pm_runtime_force_suspend/resume helpers. Runtime PM of the Exynos AudSS
device is managed from clock core depending on the preparation status
of the provided clocks.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1503302703-13801-6-git-send-email-m.szyprowski@samsung.com
2017-09-07 15:26:01 -07:00
Marek Szyprowski
232d7e4792 clk: samsung: exynos-audss: Use local variable for controller's device
Store pointer to the controller's device in local variable to avoid
extracting it from platform device in each call. This will also simplify
code in the future, when runtime PM support is added.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1503302703-13801-5-git-send-email-m.szyprowski@samsung.com
2017-09-07 15:25:57 -07:00
Marek Szyprowski
523d3de41f clk: samsung: exynos5433: Add support for runtime PM
Add runtime pm support for all clock controller units (CMU), which belong
to power domains and require special handling during on/off operations.
Typically special values has to be written to MUX registers to change
internal clocks parents to OSC clock before turning power off. During such
operation all clocks, which enter CMU has to be enabled to let MUX to
stabilize. Also for each CMU there is one special parent clock, which has
to be enabled all the time when any access to CMU registers is being done.

This patch solves most of the mysterious external abort and freeze issues
caused by a lack of proper parent CMU clock enabled or incorrect turn off
procedure.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1503302703-13801-4-git-send-email-m.szyprowski@samsung.com
2017-09-07 15:25:52 -07:00
Marek Szyprowski
d2f18d7e20 clk: samsung: Add support for runtime PM
This patch adds struct device pointer to samsung_clk_provider and forwarding it
to clk_register_* functions, so drivers can register clocks, which use runtime
pm feature.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1503302703-13801-3-git-send-email-m.szyprowski@samsung.com
2017-09-07 15:25:46 -07:00
Marek Szyprowski
9a34b45397 clk: Add support for runtime PM
Registers for some clocks might be located in the SOC area, which are under the
power domain. To enable access to those registers respective domain has to be
turned on. Additionally, registers for such clocks will usually loose its
contents when power domain is turned off, so additional saving and restoring of
them might be needed in the clock controller driver.

This patch adds basic infrastructure in the clocks core to allow implementing
driver for such clocks under power domains. Clock provider can supply a
struct device pointer, which is the used by clock core for tracking and managing
clock's controller runtime pm state. Each clk_prepare() operation
will first call pm_runtime_get_sync() on the supplied device, while
clk_unprepare() will do pm_runtime_put_sync() at the end.

Additional calls to pm_runtime_get/put functions are required to ensure that any
register access (like calculating/changing clock rates and unpreparing/disabling
unused clocks on boot) will be done with clock controller in runtime resumend
state.

When one wants to register clock controller, which make use of this feature, he
has to:
1. Provide a struct device to the core when registering the provider.
2. Ensure to enable runtime PM for that device before registering clocks.
3. Make sure that the runtime PM status of the controller device reflects
   the HW state.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1503302703-13801-2-git-send-email-m.szyprowski@samsung.com
2017-09-07 15:25:13 -07:00
Russell King
73c950da6e clk: si5351: fix PLL reset
Changing the audio sample rate on the SolidRun Cubox disrupts the video
output.  The Si5351 provides both the video clock (using PLLA on output
0) and the audio clock (using PLLB on output 2).

When the rate of clock output 2 is changed, it reconfigures PLLB, which
results in both PLLA and PLLB being reset.  The reset of PLLA causes
clock output 0 to be disrupted, thereby causing a loss of sync by the
attached display device.

Hence, each time the audio sample rate changes (eg, when a video player
starts up, or when starting to play music) the video display momentarily
blanks while the Si5351 settles down.  Prior to the commit below, this
behaviour did not happen.

Fix this by only resetting only the PLL which has been changed.

Fixes: 6dc669a22c ("clk: si5351: Add PLL soft reset")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01 16:00:54 -07:00
Quentin Schulz
1a1a36d72e clk: at91: clk-generated: make gclk determine audio_pll rate
This allows gclk to determine audio_pll rate and set the parent rate
accordingly.

However, there are multiple children clocks that could technically
change the rate of audio_pll (via gck). With the rate locking, the first
consumer to enable the clock will be the one definitely setting the rate
of the clock.

Since audio IPs are most likely to request the same rate, we enforce
that the only clks able to modify gck rate are those of audio IPs.

To remain consistent, we deny other clocks to be children of audio_pll.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01 15:46:54 -07:00
Quentin Schulz
8a8f4bf0c4 clk: at91: clk-generated: create function to find best_diff
The way to find the best_diff and do the appropriate process afterwards
can be re-used.

This patch prepares the driver for an upcoming patch that will allow
clk_generated to determine the rate of the audio_pll.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01 15:46:53 -07:00
Quentin Schulz
0865805d82 clk: at91: add audio pll clock drivers
This new clock driver set allows to have a fractional divided clock that
would generate a precise clock particularly suitable for audio
applications.

The main audio pll clock has two children clocks: one that is connected
to the PMC, the other that can directly drive a pad. As these two routes
have different enable bits and different dividers and divider formulas,
they are handled by two different drivers. Each of them could modify the
rate of the main audio pll parent.

The main audio pll clock can output 620MHz to 700MHz.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01 15:46:52 -07:00
Quentin Schulz
8c7aa63289 clk: at91: clk-generated: remove useless divisor loop
The driver requests the current clk rate of each of its parent clocks to
decide whether a clock rate is suitable or not. It does not request
determine_rate from a parent clock which could request a rate change in
parent clock (i.e. there is no parent rate propagation).

We know the rate we want (passed along req argument of the function) and
the parent clock rate, thus we know the closest rounded divisor, we
don't need to iterate over the available divisors to find the best one
for a given clock.

Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01 15:46:48 -07:00
Andreas Färber
8bb48f79ea clk: mb86s7x: Drop non-building driver
It fails to build once we introduce the ARCH_MB86S7X Kconfig symbol:

  drivers/clk/clk-mb86s7x.c:27:10: fatal error: soc/mb86s7x/scb_mhu.h: No such file or directory
   #include <soc/mb86s7x/scb_mhu.h>
            ^~~~~~~~~~~~~~~~~~~~~~~
  compilation terminated.

And when commenting out that line, we get:

  drivers/clk/clk-mb86s7x.c: In function 'crg_gate_control':
  drivers/clk/clk-mb86s7x.c:72:8: error: implicit declaration of function 'mb86s7x_send_packet' [-Werror=implicit-function-declaration]
    ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
          ^~~~~~~~~~~~~~~~~~~
  drivers/clk/clk-mb86s7x.c:72:28: error: 'CMD_PERI_CLOCK_GATE_SET_REQ' undeclared (first use in this function)
    ret = mb86s7x_send_packet(CMD_PERI_CLOCK_GATE_SET_REQ,
                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~
  drivers/clk/clk-mb86s7x.c:72:28: note: each undeclared identifier is reported only once for each function it appears in
  drivers/clk/clk-mb86s7x.c: In function 'crg_rate_control':
  drivers/clk/clk-mb86s7x.c:116:10: error: 'CMD_PERI_CLOCK_RATE_SET_REQ' undeclared (first use in this function)
     code = CMD_PERI_CLOCK_RATE_SET_REQ;
            ^~~~~~~~~~~~~~~~~~~~~~~~~~~
  drivers/clk/clk-mb86s7x.c:121:10: error: 'CMD_PERI_CLOCK_RATE_GET_REQ' undeclared (first use in this function); did you mean 'CMD_PERI_CLOCK_RATE_SET_REQ'?
     code = CMD_PERI_CLOCK_RATE_GET_REQ;
            ^~~~~~~~~~~~~~~~~~~~~~~~~~~
            CMD_PERI_CLOCK_RATE_SET_REQ
  drivers/clk/clk-mb86s7x.c: In function 'mhu_cluster_rate':
  drivers/clk/clk-mb86s7x.c:276:10: error: 'CMD_CPU_CLOCK_RATE_GET_REQ' undeclared (first use in this function)
     code = CMD_CPU_CLOCK_RATE_GET_REQ;
            ^~~~~~~~~~~~~~~~~~~~~~~~~~
  drivers/clk/clk-mb86s7x.c:278:10: error: 'CMD_CPU_CLOCK_RATE_SET_REQ' undeclared (first use in this function); did you mean 'CMD_CPU_CLOCK_RATE_GET_REQ'?
     code = CMD_CPU_CLOCK_RATE_SET_REQ;
            ^~~~~~~~~~~~~~~~~~~~~~~~~~
            CMD_CPU_CLOCK_RATE_GET_REQ
  cc1: some warnings being treated as errors
  scripts/Makefile.build:302: recipe for target
  'drivers/clk/clk-mb86s7x.o' failed
  make[2]: *** [drivers/clk/clk-mb86s7x.o] Error 1

Remove the driver for now.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-09-01 13:31:24 -07:00
Colin Ian King
df2f845167 clk: ti: check for null return in strrchr to avoid null dereferencing
strrchr can potentially return a null so the following strlen on the
null pointer can cause a null dereference. Add a check to see if
the string postfix is not null before calling strlen.

Detected by CoverityScan, CID#1452039 ("Dereference null return")

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 18:44:13 -07:00
Alex Frid
2316a7a334 clk: Don't write error code into divider register
Add a check for error returned by divider value calculation to avoid
writing error code into hw register.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Fixes: bca9690b94 ("clk: divider: Make generic for usage elsewhere")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 18:43:38 -07:00
Katsuhiro Suzuki
6c264416c9 clk: uniphier: add video input subsystem clock
Add a clock for video input subsystem (EXIV) on
UniPhier LD11/LD20 SoCs.

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 18:41:14 -07:00
Katsuhiro Suzuki
e3dd205860 clk: uniphier: add audio system clock
Add clock for audio subsystem (AIO) and SoC internal audio codec
(EVEA) on UniPhier LD11/LD20 SoCs.

Signed-off-by: Katsuhiro Suzuki <suzuki.katsuhiro@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 18:40:23 -07:00
Gabriel Fernandez
3e4d618b07 clk: stm32h7: Add stm32h743 clock driver
This patch enables clocks for STM32H743 boards.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>

for MFD changes:
Acked-by: Lee Jones <lee.jones@linaro.org>

for DT-Bindings
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 18:35:47 -07:00
Gabriel Fernandez
0a9c869d5c clk: gate: expose clk_gate_ops::is_enabled
This patch exposes clk_gate_ops::is_enabled as functions
that can be directly called and assigned in places like this so
we don't need wrapper functions that do nothing besides forward
the call.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 18:35:45 -07:00
Gabriel Fernandez
42d3c5f634 clk: nxp: clk-lpc32xx: rename clk_gate_is_enabled()
We need to export clk_gate_is_enabled() from clk framework, then
to avoid compilation issue we have to rename clk_gate_is_enabled()
in NXP LPC32xx clock driver.
We changed all gate op with 'lpc32xx_' prefix:
lpc32xx_clk_gate_enable(),
lpc32xx_clk_gate_disable(),
lpc32xx_clk_gate_is_enabled().

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Acked-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 18:35:44 -07:00
Masahiro Yamada
736de651a8 clk: uniphier: add PXs3 clock data
Add basic clock data for Socionext's new SoC PXs3.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 18:34:35 -07:00
Leo Yan
9fa7231b19 clk: hi6220: change watchdog clock source
The old code uses tcxo (19.2MHz) as watchdog clock but actually the
watchdog uses 32K clock, as result the watchdog timeout cannot be set
correctly and delay long time to reset SoC.

So this patch is to use 'ref32k' as clock source for watchdog.

Fixes: 72ea48610d ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC")
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 18:32:43 -07:00
Elaine Zhang
65bc9d7ff2 clk: Kconfig: Name RK805 in Kconfig for COMMON_CLK_RK808
The RK808 and RK805 PMICs are using a similar register map.
We can reuse the clk driver for the RK805 PMIC. So let's add
the RK805 in the Kconfig description.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 16:20:12 -07:00
Gaku Inami
e001525c4b clk: cs2000: Add cs2000_set_saved_rate
This patch adds the common function to reset the clk rate in order to
be able to use it in other cases.

Signed-off-by: Gaku Inami <gaku.inami.xw@bp.renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-08-31 11:32:32 -07:00