Commit Graph

420 Commits

Author SHA1 Message Date
Alex Deucher
dc50ba7f9a drm/radeon/kms: add dpm support for evergreen (v4)
This adds dpm support for evergreen asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2 switching (requires additional acpi support)

Set radeon.dpm=1 to enable.

v2: reduce stack usage, rename ulv struct
v3: fix thermal interrupt check notices by Jerome
v4: fix state enable

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 19:15:22 -04:00
Alex Deucher
66229b2005 drm/radeon/kms: add dpm support for rv7xx (v4)
This adds dpm support for rv7xx asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2 switching

Set radeon.dpm=1 to enable.

v2: reduce stack usage
v3: fix 64 bit div
v4: fix state enable

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 19:14:59 -04:00
Alex Deucher
4a6369e993 drm/radeon/kms: add dpm support for rv6xx (v3)
This adds dpm support for rv6xx asics.  This includes:
- clockgating
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen1/gen2 switching

Set radeon.dpm=1 to enable.

v2: remove duplicate line
v3: fix thermal interrupt check noticed by Jerome

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2013-06-27 10:50:08 -04:00
Alex Deucher
2e9d4c05a1 drm/radeon/kms: add common r600 dpm functions
These are shared by rs780/rs880, rv6xx, and newer chips.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:24 -04:00
Alex Deucher
da321c8a6a drm/radeon/kms: add common dpm infrastructure
This adds the common dpm (dynamic power management)
infrastructure:
- dpm callbacks
- dpm init/fini/suspend/resume
- dpm power state selection

No device specific code is enabled yet.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:20 -04:00
Alex Deucher
ae5b0abbb6 drm/radeon/kms: add atom helper functions for dpm (v3)
dpm needs access to atombios data and command tables
for setup and calculation of a number of parameters.

v2: endian fix
v3: fix mc reg table bug

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:19 -04:00
Alex Deucher
2948f5e6c2 drm/radeon: properly set up the RLC on ON/LN/TN (v3)
This is required for certain advanced functionality.

v2: save/restore list takes dword offsets
v3: rebase on gpu reset changes

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:18 -04:00
Alex Deucher
6bd1c38532 drm/radeon: make get_temperature functions a callback
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:16 -04:00
Alex Deucher
46f9564ab0 drm/radeon/evergreen: add indirect register accessors for CG registers
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:15 -04:00
Alex Deucher
ff82bbc4d5 drm/radeon/kms: add accessors for RCU indirect space
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:14 -04:00
Alex Deucher
39aee49028 drm/radeon: add cik tile mode array query
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:12 -04:00
Alex Deucher
963e81f9e0 drm/radeon/cik: Add support for compute queues (v4)
On CIK, the compute rings work slightly differently than
on previous asics, however the basic concepts are the same.

The main differences:
- New MEC engines for compute queues
- Multiple queues per MEC:
  - CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues
  -    KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues
- Queues can be allocated and scheduled by another queue
- New doorbell aperture allows you to assign space in the aperture
  for the wptr which allows for userspace access to queues

v2: add wptr shadow, fix eop setup
v3: fix comment
v4: switch to new callback method

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2013-06-27 10:49:08 -04:00
Alex Deucher
75efdee11b drm/radeon: implement simple doorbell page allocator
The doorbell aperture is a PCI BAR whose pages can be
mapped to compute resources for things like wptrs
for userspace queues.

This patch maps the BAR and sets up a simple allocator
to allocate pages from the BAR.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:07 -04:00
Alex Deucher
f93bdefe62 drm/radeon: use callbacks for ring pointer handling (v3)
Add callbacks to the radeon_asic struct to handle
rptr/wptr fetchs and wptr updates.
We currently use one version for all rings, but this
allows us to override with a ring specific versions.

Needed for compute rings on CIK.

v2: udpate as per Christian's comments
v3: fix some rebase cruft

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-27 10:49:07 -04:00
Alex Deucher
1d5d0c3497 drm/radeon: add indirect register accessors for SMC registers
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:47 -04:00
Alex Deucher
9e05fa1d24 drm/radeon/cik: add hw cursor support (v2)
CIK (DCE8) hw cursors are programmed the same as evergreen
(DCE4) with the following caveats:
- cursors are now 128x128 pixels
- new alpha blend enable bit

v2: rebase

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:38 -04:00
Alex Deucher
5115020714 drm/radeon: handle the integrated thermal controller on CI
No support for reading the temperature yet.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-26 16:11:36 -04:00
Alex Deucher
21a93e130d drm/radeon/cik: add support for sDMA dma engines (v8)
CIK has new asynchronous DMA engines called sDMA
(system DMA).  Each engine supports 1 ring buffer
for kernel and gfx and 2 userspace queues for compute.

TODO: fill in the compute setup.

v2: update to the latest reset code
v3: remove ib_parse
v4: fix copy_dma()
v5: drop WIP compute sDMA queues
v6: rebase
v7: endian fixes for IB
v8: cleanup for release

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:33 -04:00
Alex Deucher
a59781bbe5 drm/radeon: add support for interrupts on CIK (v5)
Todo:
- handle interrupts for compute queues

v2: add documentation
v3: update to latest reset code
v4: update to latest illegal CP handling
v5: fix missing break in interrupt handler switch statement

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:31 -04:00
Alex Deucher
02c8132741 drm/radeon: add initial ucode loading for CIK (v5)
Currently the driver required 6 sets of ucode:
1. pfp - pre-fetch parser, part of the GFX CP
2. me - micro engine, part of the GFX CP
3. ce - constant engine, part of the GFX CP
4. rlc - interrupt, etc. controller
5. mc - memory controller (discrete cards only)
6. mec - compute engines, part of Compute CP

V2: add documentation
V3: update MC ucode
V4: rebase
V5: update mc ucode

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:27 -04:00
Alex Deucher
8cc1a5328b drm/radeon: add gpu init support for CIK (v9)
v2: tiling fixes
v3: more tiling fixes
v4: more tiling fixes
v5: additional register init
v6: rebase
v7: fix gb_addr_config for KV/KB
v8: drop wip KV bits for now, add missing config reg
v9: fix cu count on Bonaire

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:24 -04:00
Alex Deucher
e282917ca3 drm/radeon: add DCE8 macro for CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:23 -04:00
Alex Deucher
8f61b34ceb drm/radeon: add a reset work handler
New asics support non-privileged IBs.  This allows us
to skip IB checking in the driver since the hardware
will check the command buffers for us.  When using
non-privileged IBs, if the CP encounters an illegal
register in the command stream, it will halt and generate
an interrupt.  The CP needs to be reset to continue.  For now
just do a full GPU reset when this happens.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-06-25 17:50:21 -04:00
Alex Deucher
948bee3ff4 drm/radeon: track which asics have UVD
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-20 12:09:37 -04:00
Alex Deucher
b5d9d72624 drm/radeon: add chip family for Hainan
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2013-05-20 11:13:06 -04:00
Christian König
facd112d13 drm/radeon: consolidate UVD clock programming
Instead of duplicating the code over and over again, just use a single
function to handle the clock calculations.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-02 10:09:48 -04:00
Jerome Glisse
409851f489 radeon: add bo tracking debugfs
This is to allow debugging of userspace program not freeing buffer
after, which is basicly a memory leak. This print the list of all
gem object along with their size and placement (VRAM,GTT,CPU) and
with the pid of the task that created them.

agd5f: add warning fix

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-02 10:09:47 -04:00
Alex Deucher
2e1b65f98b drm/radeon: add helper function to support golden registers
Golden registers are arrays of register settings from the
hw team that need to be initialized at asic startup.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-23 18:03:55 -04:00
Alex Deucher
a973bea11c drm/radeon: switch audio handling to use callbacks
Register audio callbacks for asic where we support
audio.  Cleans up the code and makes it easier to
add support for newer asics.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-23 18:03:53 -04:00
Christian König
55b51c88c5 drm/radeon: raise UVD clocks only on demand
That not only saves some power, but also solves problems with
older chips where an idle UVD block on higher clocks can
cause problems.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-23 17:45:44 -04:00
Rafał Miłecki
d5169fc4cc drm/radeon: add helpers for masking and setting bits in regs
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-22 10:39:12 -04:00
Jerome Glisse
64d7b8bed8 drm/radeon: add si tile mode array query v3
Allow userspace to query for the tile mode array so userspace can properly
compute surface pitch and alignment requirement depending on tiling.

v2: Make strict aliasing safer by casting to char when copying
v3: merge fix from Christian

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-11 09:22:06 -04:00
Alex Deucher
492d2b61b3 drm/radeon/kms: replace *REG32_PCIE_P with *REG32_PCIE_PORT
Avoid confusion with the *REG32_P mask macro.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:40 -04:00
Christian König
7062ab67d4 drm/radeon: add radeon_atom_get_clock_dividers helper
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:35 -04:00
Alex Deucher
73afc70d11 drm/radeon: add pm callback for setting uvd clocks
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:34 -04:00
Christian König
f2ba57b5ea drm/radeon: UVD bringup v8
Just everything needed to decode videos using UVD.

v6: just all the bugfixes and support for R7xx-SI merged in one patch
v7: UVD_CGC_GATE is a write only register, lockup detection fix
v8: split out VRAM fallback changes, remove support for RV770,
    add support for HEMLOCK, add buffer sizes checks

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:33 -04:00
Christian König
4474f3a91f drm/radeon: rework fallback handling v2
Let the CS module decide if we can fall back to VRAM or not.

v2: remove unintended change

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:33 -04:00
Samuel Li
a0a53aa8c7 drm/radeon: Use direct mapping for fast fb access on RS690
This patch allows the CPU to map the stolen vram segment
directly rather than going through the PCI BAR.  This
significantly improves performance for certain workloads with
a properly patched ddx.

Use radeon.fastfb=1 to enable it (disabled by default).
Currently only supported on RS690, but support for RS780/880
and newer APUs may be added eventually.

Signed-off-by: Samuel Li <samuel.li@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:31:31 -04:00
Alex Deucher
9ed8b1f93c drm/radeon: clean up vram/gtt location handling
Add a per-asic MC (memory controller) mask which holds the
mak address mask the asic is capable of.  Use this when
calculating the vram and gtt locations rather using asic
specific functions or limiting everything to 32 bits.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-04-09 10:23:50 -04:00
Dave Airlie
74e1697478 Merge branch 'drm-next-3.9' of git://people.freedesktop.org/~agd5f/linux into drm-next
More drm-next bits for radeon.  Just bug fixes.

* 'drm-next-3.9' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: properly validate the atpx interface
  drm/radeon: switch get_gpu_clock() to a callback (v2)
  drm/radeon: add a asic callback to get the xclk
  drm/radeon: Avoid NULL pointer dereference from atom_index_iio() allocation failure
  drm/radeon: remove overzealous warning in hdmi handling
  drm/radeon: fix multi-head power profile stability on BTC+ asics
2013-02-21 07:15:16 +10:00
Alex Deucher
d041889414 drm/radeon: switch get_gpu_clock() to a callback (v2)
Cleans up the code for future asics

v2: rebase, fix some missing radeon_asic updates

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-20 08:51:21 -05:00
Alex Deucher
454d2e2a32 drm/radeon: add a asic callback to get the xclk
This is required to get the reference clock used
by the gfx engine for things like timestamps. Fixes
support for GL extensions the use timestamps on
certain boards.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-20 08:51:20 -05:00
Aaron Plattner
1e6d17a5df drm/radeon: use prime helpers
Simplify the Radeon prime implementation by using the default behavior provided
by drm_gem_prime_import and drm_gem_prime_export.

v2:
- Rename functions to radeon_gem_prime_get_sg_table and
  radeon_gem_prime_import_sg_table.
- Delete the now-unused vmapping_count variable.

Signed-off-by: Aaron Plattner <aplattner@nvidia.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: David Airlie <airlied@linux.ie>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-02-08 13:48:43 +10:00
Alex Deucher
624d35242a drm/radeon: add Oland chip family
Oland is a new asic in the SI family.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-02-01 19:34:23 -05:00
Alex Deucher
43f1214aa0 drm/radeon: use IBs for VM page table updates v2
For very large page table updates, we can exceed the
size of the ring.  To avoid this, use an IB to perform
the page table update.

v2(ck): cleanup the IB infrastructure and the use it instead
        of filling the struct ourself.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
2013-02-01 13:57:10 -05:00
Alex Deucher
410a3418a8 drm/radeon: add a bios scratch asic hung helper
Used by all asic families from r600+.
Flag for the vbios and later instances of the driver
that the GPU is hung.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:49 -05:00
Alex Deucher
9ff0744c6d drm/radeon: add additional reset flags
This adds further flags for fine grained reset.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:48 -05:00
Ilija Hadzic
e971699309 drm/radeon: pull out common next_reloc function
next_reloc function does the same thing in all ASICs with
the exception of R600 which has a special case in legacy mode.
Pull out the common function in preparation for refactoring.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:45 -05:00
Ilija Hadzic
c3ad63afcd drm/radeon: rename r100_cs_dump_packet to radeon_cs_dump_packet
This function is not limited to r100, but it can dump a
(raw) packet for any ASIC. Rename it accordingly and move
its declaration to radeon.h

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:44 -05:00
Ilija Hadzic
40592a17b8 drm/radeon: refactor vline packet parsing function
vline packet parsing function for R600 and Evergreen+ are
the same, except that they use different registers. Factor
out the algorithm into a common function that uses register
table passed from ASIC-specific caller.

This reduces ASIC-specific function to (trivial) setup
of register table and call into the common function.

Signed-off-by: Ilija Hadzic <ihadzic@research.bell-labs.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-01-31 16:24:43 -05:00