Commit Graph

11193 Commits

Author SHA1 Message Date
Alex Deucher
f7466e6ca0 drm/radeon: switch to pptable.h
Internally we switched to using a separate header for
atombios pplib definitions.  Switch over the open source
driver.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:11 -04:00
Alex Deucher
03243fc656 drm/radeon/sumo add helper to go from vid7 to vid2
Needed for DPM on KB/KV.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:10 -04:00
Alex Deucher
1d58234d5e drm/radeon: add indirect accessors for dift registers on CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:09 -04:00
Alex Deucher
22c775ce80 drm/radeon: implement clock and power gating for CIK (v3)
Only the APUs support power gating.

v2: disable cgcg for now
v3: workaround hw issue in mgcg

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:08 -04:00
Alex Deucher
1fd11777c2 drm/radeon: convert SI,CIK to use sumo_rlc functions
and remove duplicate si_rlc functions.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:08 -04:00
Alex Deucher
10b7ca7e09 drm/radeon: clean up sumo_rlc_init() for code sharing
This will eventually be shared with newer asics to
reduce code duplication.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:07 -04:00
Alex Deucher
866d83de0c drm/radeon/cik: restructure rlc setup
Restructure rlc setup to handle clock and power
gating.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:06 -04:00
Alex Deucher
7235711a43 drm/radeon: add support for ASPM on CIK asics
Enables PCIE ASPM (Active State Power Management) on
CIK asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:05 -04:00
Alex Deucher
8a7cd27679 drm/radeon/cik: add support for pcie gen1/2/3 switching
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:04 -04:00
Alex Deucher
8c68e39388 drm/radeon: switch CIK to use radeon_ucode.h
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:04 -04:00
Alex Deucher
62c35fd7d2 drm/radeon/cik: implement some more atom helpers for DPM
Required for DPM on CIK.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:03 -04:00
Alex Deucher
58ea2deab3 drm/radeon/kms: fix up dce8 display watermark calc for dpm
Calculate the low and high watermarks based on the low and high
clocks for the current power state.  The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:02 -04:00
Alex Deucher
d4d3278c65 drm/radeon/dpm: use performance state if no UVD state
Newer asics don't have specific UVD states.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:01 -04:00
Alex Deucher
edcd26e81f drm/radeon: default to 1024M gart size on rv770+
Newer asics have a lot of vram so it's less of an
issue to waste a little more space for the gart
page table.  This gives us some additional gart space
before having to migrate to non-gart system ram
for games, etc. where we use up most of vram.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:00 -04:00
Alex Deucher
6032034761 drm/radeon/dpm: rework thermal state handling
1. Handle the the thermal state directly in the work handler.
Remove the state selection function since nothing else uses it now.
2. On some asics there is no thermal state, so we just use a regular
state and force the low performance state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:30:00 -04:00
Alex Deucher
ce3537d571 drm/radeon/dpm: use multiple UVD power states (v3)
Use the UVD handle information to determine which
which power states to select when using UVD.  For
example, decoding a single SD stream requires much
lower clocks than multiple HD streams.

v2: switch to a cleaner dpm/uvd interface
v3: change the uvd power state while streams
are active if need be

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:29:59 -04:00
Alex Deucher
85a129ca8d drm/radeon: add UVD->DPM helper function (v5)
Add a helper function for counting the number of open stream handles.

v2: fix copy-pasta in comments and whitespace error
v3: make function static since it's only used in radeon_uvd.c
at the moment
v4: make non-static again for future changes
v5: make static again for new rework of dpm uvd changes

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:29:58 -04:00
Alex Deucher
4f86296758 drm/radeon/kms: remove r6xx+ blit copy routines
No longer used now that we use the async dma engines or
CP DMA for bo copies.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:29:57 -04:00
Alex Deucher
8dddb993bc drm/radeon: switch r6xx+ to using CP DMA for the blit copy callback
CP DMA is lighter weight than using the 3D engine.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-30 16:29:57 -04:00
Alex Deucher
118bdbd86b drm/edid: add quirk for Medion MD30217PG
This LCD monitor (1280x1024 native) has a completely
bogus detailed timing (640x350@70hz).  User reports that
1280x1024@60 has waves so prefer 1280x1024@75.

Manufacturer: MED  Model: 7b8  Serial#: 99188
Year: 2005  Week: 5
EDID Version: 1.3
Analog Display Input,  Input Voltage Level: 0.700/0.700 V
Sync:  Separate
Max Image Size [cm]: horiz.: 34  vert.: 27
Gamma: 2.50
DPMS capabilities: Off; RGB/Color Display
First detailed timing is preferred mode
redX: 0.645 redY: 0.348   greenX: 0.280 greenY: 0.605
blueX: 0.142 blueY: 0.071   whiteX: 0.313 whiteY: 0.329
Supported established timings:
720x400@70Hz
640x480@60Hz
640x480@72Hz
640x480@75Hz
800x600@56Hz
800x600@60Hz
800x600@72Hz
800x600@75Hz
1024x768@60Hz
1024x768@70Hz
1024x768@75Hz
1280x1024@75Hz
Manufacturer's mask: 0
Supported standard timings:
Supported detailed timing:
clock: 25.2 MHz   Image Size:  337 x 270 mm
h_active: 640  h_sync: 688  h_sync_end 784 h_blank_end 800 h_border: 0
v_active: 350  v_sync: 350  v_sync_end 352 v_blanking: 449 v_border: 0
Monitor name: MD30217PG
Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 83 kHz, PixClock max 145 MHz
Serial No: 501099188
EDID (in hex):
          00ffffffffffff0034a4b80774830100
          050f010368221b962a0c55a559479b24
          125054afcf00310a0101010101018180
          000000000000d60980a0205e63103060
          0200510e1100001e000000fc004d4433
          3032313750470a202020000000fd0038
          4c1e530e000a202020202020000000ff
          003530313039393138380a2020200078

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reported-by: friedrich@mailstation.de
Cc: stable@vger.kernel.org
2013-08-30 16:29:56 -04:00
Jakob Bornecrantz
6e4dcff3ad drm/vmwgfx: Split GMR2_REMAP commands if they are to large
This fixes the piglit test texturing/max-texture-size
causing the VM to die due to a too large SVGA command.

Signed-off-by: Jakob Bornecrantz <jakob@vmware.com>
Reviewed-by: Biran Paul <brianp@vmware.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@gmail.com>
2013-08-30 09:03:39 +10:00
Imre Deak
77fa4cbd5f drm/i915: ivb: fix edp voltage swing reg val
Fix the typo introduced in

commit 1a2eb4604b
Author: Keith Packard <keithp@keithp.com>
Date:   Wed Nov 16 16:26:07 2011 -0800

    drm/i915: Hook up Ivybridge eDP

This fixes eDP link-training failures and cases where all voltage swing
/pre-emphasis levels were tried and failed during clock recovery and -
as a fallback - we go on to do channel equalization with the last voltage
swing/pre-emphasis level which will succeed. Both issues can lead to a
blank screen.

v2:
- improve commit message

CC: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64880
Tested-by: Jeremy Moles <cubicool@gmail.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-08-30 00:07:27 +02:00
Dave Airlie
4dd17ee957 Merge tag 'drm-intel-fixes-2013-08-23' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Just one patch that soaked for quite a bit to fix a resume issue,
resulting in gpu hangs (or worse) due to tlb containing garbage.

* tag 'drm-intel-fixes-2013-08-23' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: Invalidate TLBs for the rings after a reset
2013-08-23 18:52:37 +10:00
Guillaume Clement
6f1e120438 gma500: Fix SDVO turning off randomly
Some Poulsbo cards seem to incorrectly report SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED instead of SDVO_CMD_STATUS_PENDING, which causes the display to be turned off.

Signed-off-by: Guillaume Clement <gclement@baobob.org>
Acked-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-22 10:37:49 +10:00
Dave Airlie
317b07b58c Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes
regression fixes and null derefs and oops fixes.

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nv04/disp: fix framebuffer pin refcounting
  drm/nouveau/mc: fix race condition between constructor and request_irq()
  drm/nouveau: fix reclocking on nv40
  drm/nouveau/ltcg: fix allocating memory as free
  drm/nouveau/ltcg: fix ltcg memory initialization after suspend
  drm/nouveau/fb: fix null derefs in nv49 and nv4e init
2013-08-22 10:34:58 +10:00
Ben Skeggs
78ae0ad403 drm/nv04/disp: fix framebuffer pin refcounting
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-08-21 11:36:21 +10:00
Ben Skeggs
6ff8c76a56 drm/nouveau/mc: fix race condition between constructor and request_irq()
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-08-21 11:36:20 +10:00
Pali Rohár
0ff42c5af6 drm/nouveau: fix reclocking on nv40
In commit 77145f1cbd was introduced
error which cause that reclocking on nv40 not working anymore.
There is missing assigment of return value from pll_calc to ret.

Signed-off-by: Pali Rohár <pali.rohar@gmail.com>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-08-21 11:36:08 +10:00
Maarten Lankhorst
18902bbf06 drm/nouveau/ltcg: fix allocating memory as free
Allocating type=0 marks the memory as free. This allows the ltcg memory
to be allocated twice.

Add a BUG_ON in core/mm.c to prevent this ever happening again.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-08-21 11:35:53 +10:00
Maarten Lankhorst
52f9a4d71b drm/nouveau/ltcg: fix ltcg memory initialization after suspend
Some registers were not initialized in init, this causes them to be
uninitialized after suspend.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-08-21 11:35:53 +10:00
Ilia Mirkin
6284bf41b9 drm/nouveau/fb: fix null derefs in nv49 and nv4e init
Commit dceef5d87 (drm/nouveau/fb: initialise vram controller as pfb
sub-object) moved some code around and introduced these null derefs.
pfb->ram is set to the new ram object outside of this ctor.

Reported-by: Ronald Uitermark <ronald645@gmail.com>
Tested-by: Ronald Uitermark <ronald645@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-08-21 11:35:53 +10:00
Dave Airlie
3387ed8394 Merge tag 'drm-intel-fixes-2013-08-15' of git://people.freedesktop.org/~danvet/drm-intel
* tag 'drm-intel-fixes-2013-08-15' of git://people.freedesktop.org/~danvet/drm-intel: (153 commits)
  drm/i915: Don't deref pipe->cpu_transcoder in the hangcheck code
2013-08-19 13:49:20 +10:00
Daniel Vetter
eb91626ac4 drm/i915: unpin backing storage in dmabuf_unmap
This fixes a WARN in i915_gem_free_object when the
obj->pages_pin_count isn't 0.

v2: Add locking to unmap, noticed by Chris Wilson. Note that even
though we call unmap with our own dev->struct_mutex held that won't
result in an immediate deadlock since we never go through the dma_buf
interfaces for our own, reimported buffers. But it's still easy to
blow up and anger lockdep, but that's already the case with our ->map
implementation. Fixing this for real will involve per dma-buf ww mutex
locking by the callers. And lots of fun. So go with the duct-tape
approach for now.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Cc: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Tested-by: Armin K. <krejzi@email.com> (v1)
Tested-by: Dave Airlie <airlied@redhat.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@gmail.com>
2013-08-19 13:24:54 +10:00
Chris Wilson
884020bf3d drm/i915: Invalidate TLBs for the rings after a reset
After any "soft gfx reset" we must manually invalidate the TLBs
associated with each ring. Empirically, it seems that a
suspend/resume or D3-D0 cycle count as a "soft reset". The symptom is
that the hardware would fail to note the new address for its status
page, and so it would continue to write the shadow registers and
breadcrumbs into the old physical address (now used by something
completely different, scary). Whereas the driver would read the new
status page and never see any progress, it would appear that the GPU
hung immediately upon resume.

Based on a patch by naresh kumar kachhi <naresh.kumar.kacchi@intel.com>

Reported-by: Thiago Macieira <thiago@kde.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64725
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Thiago Macieira <thiago@kde.org>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-08-18 19:37:41 +02:00
Rafał Miłecki
d43a93c8d9 drm/radeon: fix WREG32_OR macro setting bits in a register
This bug (introduced in 3.10) in WREG32_OR made
commit d3418eacad
"drm/radeon/evergreen: setup HDMI before enabling it"
cause a regression. Sometimes audio over HDMI wasn't working, sometimes
display was corrupted.

This fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=60687
https://bugzilla.kernel.org/show_bug.cgi?id=60709
https://bugs.freedesktop.org/show_bug.cgi?id=67767

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-15 12:59:45 -04:00
Alex Deucher
022374c02e drm/radeon/r7xx: fix copy paste typo in golden register setup
Uses the wrong array size for some asics which can lead
to garbage getting written to registers.

Fixes:
https://bugzilla.kernel.org/show_bug.cgi?id=60674

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-08-14 18:03:40 -04:00
Chris Wilson
63b66e5ba5 drm/i915: Don't deref pipe->cpu_transcoder in the hangcheck code
If we get an error event really early in the driver setup sequence,
which gen3 is especially prone to with various display GTT faults we
Oops. So try to avoid this.

Additionally with Haswell the transcoders are a separate bank of
registers from the pipes (4 transcoders, 3 pipes). In event of an
error, we want to be sure we have a complete and accurate picture of
the machine state, so record all the transcoders in addition to all
the active pipes.

This regression has been introduced in

commit 702e7a56af
Author: Paulo Zanoni <paulo.r.zanoni@intel.com>
Date:   Tue Oct 23 18:29:59 2012 -0200

    drm/i915: convert PIPECONF to use transcoder instead of pipe

Based on the patch "drm/i915: Dump all transcoder registers on error"
from Chris Wilson:

v2: Rebase so that we don't try to be clever and try to figure out the
cpu transcoder from hw state. That exercise should be done when we
analyze the error state offline.

The actual bugfix is to not call intel_pipe_to_cpu_transcoder in the
error state capture code in case the pipes aren't fully set up yet.

v3: Simplifiy the err->num_transcoders computation a bit. While at it
make the error capture stuff save on systems without a display block.

v4: Fix fail, spotted by Jani.

v5: Completely new commit message, cc: stable.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=60021
Cc: stable@vger.kernel.org
Tested-by: Dustin King <daking@rescomp.stanford.edu>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-08-14 20:26:49 +02:00
Christian König
112a6d0c07 drm/radeon: fix UVD message buffer validation
When the message buffer is currently moving block until it is idle again.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-12 10:46:02 -04:00
Dave Airlie
e42f581421 Merge tag 'drm-intel-fixes-2013-08-08' of git://people.freedesktop.org/~danvet/drm-intel into drm-fixes
Daniel writes:
A few bugfixes for serious stuff and regressions. Highlight is the
reinstated hack to keep the i915 backlight on when running on an optimus
machine, this prevents black screens especially with some radeon muxed
platforms. And the patch to quiet dmesg on Linus' old mac mini ;-)

* tag 'drm-intel-fixes-2013-08-08' of git://people.freedesktop.org/~danvet/drm-intel:
  drm/i915: do not disable backlight on vgaswitcheroo switch off
  drm/i915: Don't call encoder's get_config unless encoder is active
  drm/i915: avoid brightness overflow when doing scale
  drm/i915: update last_vblank when disabling the power well
  drm/i915: fix gen4 digital port hotplug definitions
2013-08-09 09:09:37 +10:00
Michel Dänzer
e91abf80a0 drm: Don't pass negative delta to ktime_sub_ns()
It takes an unsigned value. This happens not to blow up on 64-bit
architectures, but it does on 32-bit, causing
drm_calc_vbltimestamp_from_scanoutpos() to calculate totally bogus
timestamps for vblank events. Which in turn causes e.g. gnome-shell to
hang after a DPMS off cycle with current xf86-video-ati Git.

[airlied: regression introduced in drm: use monotonic time in drm_calc_vbltimestamp_from_scanoutpos]

Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59339
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=59836
Tested-by: shui yangwei <yangweix.shui@intel.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-08-08 09:50:25 +10:00
Dave Airlie
16d5b27250 Merge branch 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux
Some more radeon fixes.  Mostly dpm and uvd fixes.  Fixes hangs
with dpm on more rv6xx asics, and fixes suspend and resume with UVD.

* 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon: make missing smc ucode non-fatal
  drm/radeon/dpm: require rlc for dpm
  drm/radeon/cik: use a mutex to properly lock srbm instanced registers
  drm/radeon: remove unnecessary unpin
  drm/radeon: add more UVD CS checking
  drm/radeon: stop sending invalid UVD destroy msg
  drm/radeon: only save UVD bo when we have open handles
  drm/radeon: always program the MC on startup
  drm/radeon: fix audio dto calculation on DCE3+ (v3)
  drm/radeon/dpm: disable sclk ss on rv6xx
  drm/radeon: fix halting UVD
  drm/radeon/dpm: adjust power state properly for UVD on SI
  drm/radeon/dpm: fix spread spectrum setup (v2)
  drm/radeon/dpm: adjust thermal protection requirements
  drm/radeon: select audio dto based on encoder id for DCE3
  drm/radeon: properly handle pm on gpu reset
2013-08-08 09:47:02 +10:00
Alex Deucher
8a53fa23fd drm/radeon: make missing smc ucode non-fatal
The smc ucode is required for dpm (dynamic power
management), but if it's missing just skip dpm setup
and don't disable acceleration.

Should fix:
https://bugs.freedesktop.org/show_bug.cgi?id=67876

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:19 -04:00
Alex Deucher
761bfb9998 drm/radeon/dpm: require rlc for dpm
The rlc is required for dpm to work properly, so if
the rlc ucode is missing, don't enable dpm.  Enabling
dpm without the rlc enabled can result in hangs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:19 -04:00
Alex Deucher
f61d5b4677 drm/radeon/cik: use a mutex to properly lock srbm instanced registers
We need proper locking in the driver when accessing instanced
registers on CIK.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:18 -04:00
Christian König
3744b248f9 drm/radeon: remove unnecessary unpin
We don't pin the BO on allocation, so don't unpin it on free.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:17 -04:00
Christian König
56cc2c1538 drm/radeon: add more UVD CS checking
Improve error handling in case userspace sends us
an invalid command buffer.

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:16 -04:00
Christian König
641a00593f drm/radeon: stop sending invalid UVD destroy msg
We also need to check the handle.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:15 -04:00
Christian König
4ad9c1c774 drm/radeon: only save UVD bo when we have open handles
Otherwise just reinitialize from scratch on resume,
and so make it more likely to succeed.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:15 -04:00
Alex Deucher
6fab3febf6 drm/radeon: always program the MC on startup
For r6xx+ asics.  This mirrors the behavior of pre-r6xx
asics.  We need to program the MC even if something
else in startup() fails.  Failure to do so results in
an unusable GPU.

Based on a fix from: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-08-07 17:37:14 -04:00
Alex Deucher
1518dd8efd drm/radeon: fix audio dto calculation on DCE3+ (v3)
Need to set the wallclock ratio and adjust the phase
and module registers appropriately.  May fix problems
with audio timing at certain display timings.

v2: properly handle clocks below 24mhz
v3: rebase r600 changes

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-08-07 17:37:13 -04:00