In order to forward the guest's ARCH_WORKAROUND_2 calls to EL3,
add a small(-ish) sequence to handle it at EL2. Special care must
be taken to track the state of the guest itself by updating the
workaround flags. We also rely on patching to enable calls into
the firmware.
Note that since we need to execute branches, this always executes
after the Spectre-v2 mitigation has been applied.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
In order to offer ARCH_WORKAROUND_2 support to guests, we need
a bit of infrastructure.
Let's add a flag indicating whether or not the guest uses
SSBD mitigation. Depending on the state of this flag, allow
KVM to disable ARCH_WORKAROUND_2 before entering the guest,
and enable it when exiting it.
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
As we're going to require to access per-cpu variables at EL2,
let's craft the minimum set of accessors required to implement
reading a per-cpu variable, relying on tpidr_el2 to contain the
per-cpu offset.
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
If running on a system that performs dynamic SSBD mitigation, allow
userspace to request the mitigation for itself. This is implemented
as a prctl call, allowing the mitigation to be enabled or disabled at
will for this particular thread.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
In order to allow userspace to be mitigated on demand, let's
introduce a new thread flag that prevents the mitigation from
being turned off when exiting to userspace, and doesn't turn
it on on entry into the kernel (with the assumption that the
mitigation is always enabled in the kernel itself).
This will be used by a prctl interface introduced in a later
patch.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
On a system where firmware can dynamically change the state of the
mitigation, the CPU will always come up with the mitigation enabled,
including when coming back from suspend.
If the user has requested "no mitigation" via a command line option,
let's enforce it by calling into the firmware again to disable it.
Similarily, for a resume from hibernate, the mitigation could have
been disabled by the boot kernel. Let's ensure that it is set
back on in that case.
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
In order to avoid checking arm64_ssbd_callback_required on each
kernel entry/exit even if no mitigation is required, let's
add yet another alternative that by default jumps over the mitigation,
and that gets nop'ed out if we're doing dynamic mitigation.
Think of it as a poor man's static key...
Reviewed-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
We're about to need the mitigation state in various parts of the
kernel in order to do the right thing for userspace and guests.
Let's expose an accessor that will let other subsystems know
about the state.
Reviewed-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
On a system where the firmware implements ARCH_WORKAROUND_2,
it may be useful to either permanently enable or disable the
workaround for cases where the user decides that they'd rather
not get a trap overhead, and keep the mitigation permanently
on or off instead of switching it on exception entry/exit.
In any case, default to the mitigation being enabled.
Reviewed-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
As for Spectre variant-2, we rely on SMCCC 1.1 to provide the
discovery mechanism for detecting the SSBD mitigation.
A new capability is also allocated for that purpose, and a
config option.
Reviewed-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
In a heterogeneous system, we can end up with both affected and
unaffected CPUs. Let's check their status before calling into the
firmware.
Reviewed-by: Julien Grall <julien.grall@arm.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
In order for the kernel to protect itself, let's call the SSBD mitigation
implemented by the higher exception level (either hypervisor or firmware)
on each transition between userspace and kernel.
We must take the PSCI conduit into account in order to target the
right exception level, hence the introduction of a runtime patching
callback.
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Several source files have been taken from OpenSSL. In some of them a
comment that "permission to use under GPL terms is granted" was
included below a contradictory license statement. In several cases,
there was no indication that the license of the code was compatible
with the GPLv2.
This change clarifies the licensing for all of these files. I've
confirmed with the author (Andy Polyakov) that a) he has licensed the
files with the GPLv2 comment under that license and b) that he's also
happy to license the other files under GPLv2 too. In one case, the
file is already contained in his CRYPTOGAMS bundle, which has a GPLv2
option, and so no special measures are needed.
In all cases, the license status of code has been clarified by making
the GPLv2 license prominent.
The .S files have been regenerated from the updated .pl files.
This is a comment-only change. No code is changed.
Signed-off-by: Adam Langley <agl@chromium.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
A few more fixes for v4.17:
- A fix for a crash in scm_call_atomic on qcom platforms
- Display fix for Allwinner A10
- A fix that re-enables ethernet on Allwinner H3 (C.H.I.P et al)
- A fix for eMMC corruption on hikey
- i2c-gpio descriptor tables for ixp4xx
+ a small typo fix
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlsJynEPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3QEkP/A5dGXeQkArCWPvWoFr+20KjIS07f7F8olNy
9JKG3R2uEZsqjD3c6HFkd1abTtUQmgg/hmpxakAI8vbypA4gsq9jyFC6TxqsBSyz
uw7hQ5XcGA99pQXp8jYUrazi/XnG9Wm8LLBslsx75wJwNikzlAl6PStKDFcz0Pr6
A9JXWnqFY50YRzUr4y9GrSo3o4dvVniF3PUFEwnYliUI5qszph2/rwaE2zLQt/PT
X0DMA4v+c+4ngS5TGipY4vFjRyvsOv/NeDQzGTvGcU6QMdP4ZEsQBrye6BqowmaD
DqaoSHvsi7Lel4u29p5KyBKrM0bAhtFX+iCGiqTfkKwRWHkh7CHombUk2qX/9OJW
oB9orkKgiP35xAL5xFmB5tf03s0tQ8/qicE72tGW/TVIEBX/l+ymD76DH4rmYvRw
wNZ+HwHrMVkYgVG0TQIxxEgkXbPsyDbk3DbNbQkHf/pV5+PsMrp0iSo7oaglsS9Y
NYTRA/DQCldzhv68YRoMBh5gD4oE5iK3e3c4nLm80vd7zj8YsuXnc4+55a8PrHfs
oVg0PE5fVlP3AVRJW09ikdf03U7m0AFX/fFKHrAwWylT1+Z1KSJhM4ZaXGgdvuOV
asFUenzF3WF6Nsx+smL/vLzr/AvvYeq80Q9OdLWQl4056HurkrpL/E2HVj4MYaoW
WKKRdfzX
=mga+
-----END PGP SIGNATURE-----
Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"A few more fixes for v4.17:
- a fix for a crash in scm_call_atomic on qcom platforms
- display fix for Allwinner A10
- a fix that re-enables ethernet on Allwinner H3 (C.H.I.P et al)
- a fix for eMMC corruption on hikey
- i2c-gpio descriptor tables for ixp4xx
... plus a small typo fix"
* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: Fix i2c-gpio GPIO descriptor tables
arm64: dts: hikey: Fix eMMC corruption regression
firmware: qcom: scm: Fix crash in qcom_scm_call_atomic1()
ARM: sun8i: v3s: fix spelling mistake: "disbaled" -> "disabled"
ARM: dts: sun4i: Fix incorrect clocks for displays
ARM: dts: sun8i: h3: Re-enable EMAC on Orange Pi One
* Enable UFS and PCIe for Qualcomm msm8996/db820c
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbCHdwAAoJEFKiBbHx2RXV/5sQAIx4JnUs2HfYYnK1ILooGk5h
D95ck/OUAtnAeNfMo6pm13MPd3rMCm5Sjp8qp6vvR4JnImRuIQzPD9MD7s1kgAHm
fPQrEcENfBtPBrYs8skoJQxBuAGcQHOZSyqrTwYJYCqKMm2UymtlpS1zw/N/nWc9
h9Nh2vKc9wgF5sGdDEhCMXMnSqgWTKnAvuJQXAl7FCN1r5AIsI5myMoh1weVPZG2
PseiT2w6KAP38kZkNh/OPx5SDjcRLSrLTlK6s2i5SycAaEstYbPr/3wfsyhR26pH
nhWZzYUDZw5fBhWOBIbKv1vRmBp7Qc312sOcpODoosA7SjQn12Yqt56AC88g5krG
ijJL81Q9OePLh6MAO2oIg04pUSB2TA64b/83VaTXPdWXLxkajaQhIq4Z/JJKGXws
toiv60QaifQW3jvmpSIP2vR68iUHxVchtSu4UvWLlIqKRfCEzq2d0R+cNrwVDM4x
saOfCNee7i3eIDyWkfRzfZNk3gMIGdsmEAxJ9flvtQscNIXGvxKasOLy7bi2iWQ4
G+AXS1hmSHkugeZwU8h2RjOlKkTO5yvWQm9vi60gB/So14RLajgF120Yn2rOF5IS
r+14YXEDHZkGm3FczIgT2drdtXfEmadbYpTROvifnj3WrTi7NJDBOTsf8kV85aa6
Zc/sU/BazzUqQat30BiX
=sPLc
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-defconfig-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/defconfig
Qualcomm ARM64 Based defconfig Updates for v4.18
* Enable UFS and PCIe for Qualcomm msm8996/db820c
* tag 'qcom-arm64-defconfig-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: defconfig: Enable PCIe on msm8996 and db820c
arm64: defconfig: Enable UFS on msm8996
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch is a partial revert of
commit abd7d0972a ("arm64: dts: hikey: Enable HS200 mode on eMMC")
which has been causing eMMC corruption on my HiKey board.
Symptoms usually looked like:
mmc_host mmc0: Bus speed (slot 0) = 24800000Hz (slot req 400000Hz, actual 400000HZ div = 31)
...
mmc_host mmc0: Bus speed (slot 0) = 148800000Hz (slot req 150000000Hz, actual 148800000HZ div = 0)
mmc0: new HS200 MMC card at address 0001
...
dwmmc_k3 f723d000.dwmmc0: Unexpected command timeout, state 3
mmc_host mmc0: Bus speed (slot 0) = 24800000Hz (slot req 400000Hz, actual 400000HZ div = 31)
mmc_host mmc0: Bus speed (slot 0) = 148800000Hz (slot req 150000000Hz, actual 148800000HZ div = 0)
mmc_host mmc0: Bus speed (slot 0) = 24800000Hz (slot req 400000Hz, actual 400000HZ div = 31)
mmc_host mmc0: Bus speed (slot 0) = 148800000Hz (slot req 150000000Hz, actual 148800000HZ div = 0)
mmc_host mmc0: Bus speed (slot 0) = 24800000Hz (slot req 400000Hz, actual 400000HZ div = 31)
mmc_host mmc0: Bus speed (slot 0) = 148800000Hz (slot req 150000000Hz, actual 148800000HZ div = 0)
print_req_error: I/O error, dev mmcblk0, sector 8810504
Aborting journal on device mmcblk0p10-8.
mmc_host mmc0: Bus speed (slot 0) = 24800000Hz (slot req 400000Hz, actual 400000HZ div = 31)
mmc_host mmc0: Bus speed (slot 0) = 148800000Hz (slot req 150000000Hz, actual 148800000HZ div = 0)
mmc_host mmc0: Bus speed (slot 0) = 24800000Hz (slot req 400000Hz, actual 400000HZ div = 31)
mmc_host mmc0: Bus speed (slot 0) = 148800000Hz (slot req 150000000Hz, actual 148800000HZ div = 0)
mmc_host mmc0: Bus speed (slot 0) = 24800000Hz (slot req 400000Hz, actual 400000HZ div = 31)
mmc_host mmc0: Bus speed (slot 0) = 148800000Hz (slot req 150000000Hz, actual 148800000HZ div = 0)
mmc_host mmc0: Bus speed (slot 0) = 24800000Hz (slot req 400000Hz, actual 400000HZ div = 31)
mmc_host mmc0: Bus speed (slot 0) = 148800000Hz (slot req 150000000Hz, actual 148800000HZ div = 0)
EXT4-fs error (device mmcblk0p10): ext4_journal_check_start:61: Detected aborted journal
EXT4-fs (mmcblk0p10): Remounting filesystem read-only
And quite often this would result in a disk that wouldn't properly
boot even with older kernels.
It seems the max-frequency property added by the above patch is
causing the problem, so remove it.
Cc: Ryan Grachek <ryan@edited.us>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Ulf Hansson <ulf.hansson@linaro.org>
Cc: YongQin Liu <yongqin.liu@linaro.org>
Cc: Leo Yan <leo.yan@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Tested-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei04@gmail.com>
Add the rtc enable clock for watchdog controller to make it work well.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds device nodes to enable one GPIO controller located on
digital chip, 2 EIC (external interrupt controller) controllers loacted
on PMIC and digital chip for Spreadtrum SC9860 platform.
Moreover this patch adds 3 GPIO keys relied on EIC controller to support
power key and volume up/down keys.
Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
- Enable the support of ethernet, eMMC, Combo/INNO phy
and PCIe for Hi3798CV200
- Enable the LPC for hip06 and hip07
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbCDTrAAoJEAvIV27ZiWZcESIP/jd+gcVS2D0gxbtT85sWoW+e
UvScBrFNUly+WPpd3txfncrQ5IEOzR1NdzWmdKn29KqvmvM/zbuoNpS0+0IZZ/YX
acSF3FnGJazIQHz2bYu/0A53cV7Xu+41Ml/NVaRFet4IimZsa/R8j7mIcz0FfDnu
CBR6A4DfF9G9WD14x/yKhTbs7LSyqFQsSdzOWD9W13pcIoX5KFkfwcoaDKOWJLbF
0n+v6c/DB9L/UWMub/ihE6FWJcvyPLTEIPtPnQD2rZRnRtp429PRNwkIDj3TUdQq
0hmJpix2eygMhhDo2wuQEyUECok9VRKh1zVQAs+ScFYvbRsneHiBXDWSAr068OSf
+f1h0EYjxR85nlcA+HLgwVK/sztoedDdOiJJFLUjPaKejUfMFvAa3wcKnRKpVdE0
dJaQ+j93f6Xz/0qy5bIhDrRwAnKPWdRf87DktH6jLUSx6JLRCTRNwO7GG4mMsrFs
QuE/6E7p3BQ98Y2oCAfK0vzJ6sFo/w0N5ImD2sjbetrA3v4XjQLY38ZiqlFh0WeW
bSSCroGFcRgldq/nm4NOWXObnWucu2ODTdKBCgAjozQP6EJwXLcurxE08d1/wdhN
KdN4MR7U4uq4IYg8yi5YadcWxBi3tPEW0huCEov/gQ1gzFIpSAQ/Ywz0qOdTnoJd
4FqgwVIc8UGtY0QKxOT7
=l2fi
-----END PGP SIGNATURE-----
Merge tag 'hisi-defconfig-for-4.18v3' of git://github.com/hisilicon/linux-hisi into next/defconfig
ARM64: hisilicon: defconfig updates for 4.18
- Enable the support of ethernet, eMMC, Combo/INNO phy
and PCIe for Hi3798CV200
- Enable the LPC for hip06 and hip07
* tag 'hisi-defconfig-for-4.18v3' of git://github.com/hisilicon/linux-hisi:
arm64: defconfig: Enable HISILICON_LPC
arm64: defconfig: enable drivers for Poplar support
Signed-off-by: Olof Johansson <olof@lixom.net>
dtc now warns on incomplete OF graph endpoint connections:
arch/arm64/boot/dts/sprd/sp9860g-1h10.dtb: Warning (graph_endpoint): /soc/stm@10006000/port/endpoint: graph connection to node '/soc/funnel@10001000/ports/port@2/endpoint' is not bidirectional
The cause is a typo in 'remote-endpoint'.
Cc: Orson Zhai <orsonzhai@gmail.com>
Cc: Baolin Wang <baolin.wang@linaro.org>
Cc: Chunyan Zhang <zhang.lyra@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
1. Add clocks necessary for DECON hardware windows no 4 and 5 on
Exynos5433.
-----BEGIN PGP SIGNATURE-----
iQItBAABCAAXBQJbBwHaEBxrcnprQGtlcm5lbC5vcmcACgkQwTdm5oaLg9f4URAA
i0ExFHHBL9iG7/X3ixhpkHZQr1zw7wn7lEWVDY1O3BWo9WKT7MgnfqxOBe8IXU5i
Q6ao1ExBhWX5S3H8urtx6kNtc8hYRz4Iusysbdu11miuxE5Msljz+lFvDJLIE5bR
WLIVfm+3pZtsOSWVRvEQjWlAHeFv9kElXQOlXQyX8s6mM9PSvaWmXn2ttCOEgphT
EUoyAARb94q3z7smU4XjYYeOTxXahBGb4XHecTRu+Pd0Y/veNbGdtR79t9goHzsX
jVDDbCDpQifUVcUjsddHMiKhY8EQWepsLcELpYD01s1GWqMHtQZ0bE9wZNSxeZyg
pqXpqu1H8FBsnmxmWMAjtprSKYwRobaMWsGnibc995dZgEjaMVgUvoltBzwo/1Ze
Mq9iFCGPLgfD/cRI0c9zOYezFpAwbOGYlVcV5JIS+7Fltq1IGzTgp7O54Inl/D9Z
vqhF8rTe9UI73T6tnwvp2mO0+PxqmNyqfcClEPpm9WJNauBdaK/JR++72itWnKKd
USdR85M1cXDLdZFpa2PRbhQDgw+Wej/i1x6WgpzmU4TIFDxsLXSpRhjhtR/D3fTK
+aPwLUHkmufLX/poHdPcQYJPhkogtc2Q+i2zdo/oClPO/naO7+WRDn8+gttFk8yS
CBescFGGrk0Eqt1usaTI4eQk8CFaDiiSJvLq4Nx8lwE=
=6wYh
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt
Samsung DTS ARM64 changes for v4.18, part 2
1. Add clocks necessary for DECON hardware windows no 4 and 5 on
Exynos5433.
* tag 'samsung-dt64-4.18-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add more clocks to Exynos5433 Decon/DeconTV
Signed-off-by: Olof Johansson <olof@lixom.net>
-----BEGIN PGP SIGNATURE-----
iQJHBAABCgAxFiEE2MW6uuYZ+0zBfpF41kg+k28NbwgFAlsGU58THGpzemhhbmcz
QGdtYWlsLmNvbQAKCRDWSD6Tbw1vCOOzD/4wBhoFn/97yrZSJeOpbctEFmqjWuls
d1ogSCRTOvmlG6FwBXFoZiatF6DwMjkv0hKxuhW4wjmV6n9HwlgonAYXurHMAD0a
xSHbjEqvu1aX8XGPRq0WKa/oyQrCLCiiO6/9+hIfIZbGoRVkkLWBQ7KB+1UMpgPb
Y9BCoPaOrFR78emcNDjBVkZ+QWCnOm2MkQO7CZa8DOrgsNEW5247hE0c6H2fwRa1
5kulVElAs2XVlx9HXxiNbrhDA7kwvxCSJiFkCB/w3YsSdSk7RUN/cSXj5xSnFdPW
74gD/fCzLyL3vVkogegqBmpSh6NavppZlw0yJlDeszQGO/YXjDpu2Tol+Mp7KH0W
LdIJltdc/kqe7bw8eSm3cWwJiXtSIzFX5Rn456DxvezWUF4rjSZgUu41bnBR7KHw
Kq/w1800pU6pHFvx57Kq/zIid5usB83BoOVuMz0Ul86b/dbBvxQdzZlHbT0/ZVkD
l5UcaoCvNh4NzDbx5fRGLwTLcaUz0ZJb0M6MxM/Dm/+qebU/0tMowPsV9hk7G7Vb
QyfdU8b4dUYZAlFp+sSvEXXo1qfAREofdIpDsVYvTQqepdoelk8K93uzTUUdqWCc
INBpe0sZpT82vq1Rc2svyMysQhFKboyWwjR0DHOTOU64g8tC280M1ozB1eptf0N0
BQrlrw1ttJWmJA==
=corl
-----END PGP SIGNATURE-----
Merge tag 'berlin64-dt-for-v4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin into next/dt
Berlin64 DT changes for v4.18
* tag 'berlin64-dt-for-v4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin:
arm64: dts: move berlin SoC files from marvell dir to synaptics dir
arm64: dts: berlin4ct-*.dts: use SPDX-License-Identifier
arm64: dts: berlin4ct: use SPDX-License-Identifier
Signed-off-by: Olof Johansson <olof@lixom.net>
* Add support for SDM845 and associated peripherals
* Fix gic_irq_domain_translation warnings on Qualcomm platforms
* Add binding for GENI SE, Qualcomm bluetooth, and Command DB
* Add support for SDHCI and ramoops on MSM8992
* Fixup qcom,pcie devices to pcie
* Add wlan, bluetooth, and micro SD supplies on db820c
* Add UFS related nodes on MSM8996
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJbBO5XAAoJEFKiBbHx2RXVepsP/RLrHukvzg4uAg1jrmhoE0W8
DKdjwwXHC4gZwi7PQuB4RVMXiJKKGU83d4NjVCw54ZokkWr+Lh3wkzRr3JZLMrTM
BCJO8PXMs5ScXqpWg78mBE/N2BUoL/V6A9wZZpi0Nfg+qUzMSPvkLq5ddq8AZ23E
+gQ2U8IK2ndn4AgUOSefoXNwjxhHA3nL+nfReMICHIAH6S+mmYDJCjh1Jo+v1ty3
AhPnaTKwdNBMceZlr1RcST7fnas82Tc0Vs+8gI4h5LCoDNkMCxm+0HEVN7RrTTCi
e7Lxn36PJ2ebaY/BF9kuZbSFoevrKpq9syV4CUkmncWuIXLAxVNnLOfsWwbuHibR
m1nXP6gXCkVA+RgugYrxP2RRPwKS0tVuqjiBprPOPrGd9awjME5qSUxrhtXQtFUS
++7EXxu/2fbQyub1M0xOPk0VWXuKLB4SaeY6OUxSAm/2wFJXFYm7BI3tBAEsSGQo
+D98W0c85H5tuVk9Ga3EH13U0mWKT9iBxOJUlSA+0iad5N8nZ1aQj1MVyWFzsQ5s
x3bKpO2PzvoeMNi3RaJl6L1liy6e1TiQpmfgRTsHQbhtD/XCw6duozlTQFWIPV2F
XwTl2EsXXQbT1YKrGelOBTS3OKrzPhYDfhTUWr9sqJ5QFMXJuENEDFIWz4PvXDqt
LwrkGlUGriES0LoUQdsz
=pxUm
-----END PGP SIGNATURE-----
Merge tag 'qcom-arm64-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt
Qualcomm ARM64 Updates for v4.18
* Add support for SDM845 and associated peripherals
* Fix gic_irq_domain_translation warnings on Qualcomm platforms
* Add binding for GENI SE, Qualcomm bluetooth, and Command DB
* Add support for SDHCI and ramoops on MSM8992
* Fixup qcom,pcie devices to pcie
* Add wlan, bluetooth, and micro SD supplies on db820c
* Add UFS related nodes on MSM8996
* tag 'qcom-arm64-for-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux:
arm64: dts: qcom: msm8996: Add ufs related nodes
arm64: dts: msm8996: fix gic_irq_domain_translate warnings
arm64: dts: qcom: sdm845: Sort nodes in the soc by address
arm64: dts: qcom: sdm845: Sort nodes in the reserved mem by address
arm64: dts: sdm845: Add command DB node
arm64: dts: sdm845: Fix xo_board clock name and speed
arm64: dts: qcom: Add SDM845 SMEM nodes
arm64: dts: qcom: Add APSS shared mailbox node to SDM845
arm64: dts: msm8916: fix gic_irq_domain_translate warnings
dt-bindings: introduce Command DB for QCOM SoCs
arm64: dts: apq8096-db820c: Add micro sd card supplies
dt-bindings: soc: qcom: Add device tree binding for GENI SE
dt-bindings: net: bluetooth: Add qualcomm-bluetooth
arm64: dts: apq8096-db820c: enable bluetooth node
arm64: dts: apq8096-db820c: Enable wlan and bt en pins
arm64: dts: qcom: rename qcom,pcie devices to pcie
arm64: dts: msm8992: add pstore-ramoops support
arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP
arm64: dts: Enable onboard SDHCI on msm8992
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch removes the unused bt-en-1-8v regulator and moves the
bt_en_gios claim to the pm8994_gpios node.
This bt_en_gpio could have been moved to the bluetooth serial node but
instead this node declares an 'enable' gpio addressing the bt_en_gpio.
This is needed by the Qualcomm QCA6174 WLAN/BT combo chip that needs to
have the bt_en_gpio claimed even if only WLAN is used.
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The property name vddpe-supply is not included in
Documentation/devicetree/bindings/pci/qcom,pcie.txt
nor in the pcie-qcom PCIe Root Complex driver.
This property name was used in an initial patchset for pcie-qcom,
but was renamed in a later revision.
Therefore, the regulator is currently never enabled, leaving us with
unoperational wlan.
Fix this by using the correct regulator property name, so that wlan
comes up correctly.
Fixes: 1c8ca74a2ea1 ("arm64: dts: apq8096-db820c: Enable wlan and bt en pins")
Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The UFS host controller occationally (20%) fails to enable
gcc_ufs_axi_clk because the UFS GDSC is not enabled. In most cases it's
enabled through the UFS phy driver, but to make sure it's enabled let's
enable it directly from the UFS host controller directly as well.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
We mostly have some changes to support the H6, Allwinner latest SoC. We're
still in the preliminary phase, with I2C, pinctrl and clock support.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAlsCsQwACgkQ0rTAlCFN
r3S9EhAAifnKDgAqWGuLR9xau3nK8CbjSLyFAba9ARdIuwxO3D0p6xgNkogve3o9
huwtx60TPfZeg86e5dqKmuC7gO/AKK0TaFDQcTXR4dEF6eH635J9yh1G5L6LjrLA
X9+EjuIL7a6HgolwyssRLLQETq3w5Pc+xMcoIc0J4ey0a4H8GjvXQWMzB+ytJWA1
Ykih6hMqJiR1VWbqSefx24+4X7RaBSwqu2S/GDk9Fi6Fabg5rbzH2tgolr0fK2BA
QtGx9LvJFsjpUwa2rOBom1EvEOoFri2ef3D06vOq8Nc0UA9G41JkWBXYczxRP1m5
0SEZUybyudIJMn+X3arEOklEEN5dsfzLnbpT7xWgjocPyt1foPtBYg/usPb8bvwn
k58j/nQDDrVPADEonbWmSBJ+5mtGl7pamJtm6GE0kCAe9eG8kLt0mkL5EH4X2Sq2
0P5q6HAjA866IACZzu4CRipXlBNCY+oMXSeaOkOYIfyIshNKkWPyxqim98FDtm6Y
66nfON3yXWOmbWwIW2z7HSJXpIn4L+qMD0OvTZWDISANQWybaKxeytVMcB65iEGQ
LzhfZi8K1tZdTN0cvsdKXrTTMnkcU4a1OZbDLe6vBPAengX219MYu1uCd+ArQ1Md
Rd1rjT+Nv2JpVTFV1AUgeoA1Yhu1Nw1zQTAu5y3d64HJCnybamU=
=d7Ql
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt64-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner arm64 changes for 4.18
We mostly have some changes to support the H6, Allwinner latest SoC. We're
still in the preliminary phase, with I2C, pinctrl and clock support.
* tag 'sunxi-dt64-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
arm64: allwinner: h6: add PCF8563 RTC on Pine H64 board
arm64: allwinner: h6: add R_I2C controller
arm64: allwinner: h6: add R_INTC interrupt controller
arm64: allwinner: h6: add node for R_PIO pin controller
arm64: allwinner: h6: add PRCM CCU device node
arm64: dts: allwinner: a64: bananapi-m64: add usb otg
arm64: dts: allwinner: axp803: Add drivevbus regulator
arm64: allwinner: h6: restore the usage of CCU slice macros
Signed-off-by: Olof Johansson <olof@lixom.net>
Here is our usual bunch of changes for the H3 and H5 SoCs that share the
same SoC design but with different CPUs.
This time, most of the changes are about supporting CPUFreq on these SoCs,
with voltage scaling being enabled for a number of boards.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAlsClu0ACgkQ0rTAlCFN
r3Q4EA//ayPGoqLdtf7TxEbIdXWKbON/lJRSw3mrOqdwG8p1y9X7OummzMsmXk/7
er9oYdeZfUyTvCf3nd3im5adKyC22vlpIcdjMHIbsznHVDGhxKGnn0p5Y5CvwEhI
ZWpmtxifV5gv3CtUz0VKFosok9pZbD2r52TJHZiifCiikMBeJoesNwrnn/V9cMbq
Bp4BzZyvg2Zl9msrEZDkaEDvwnPIcXxUH3Uy5N9cXu0xs9MRxLag/rRfaHZOkHl1
asHJgDnou6IbqFntLIf2c7seCf+64PlxXawoVY+IS1MNeU8RiF4lV1NI3+TuBuWM
YPWQYEWgnZdyYwQ/M1LAaLtbRgxWJNmnwooU+qO9HK0WEIC3CmuKK0NHT7ySrVQf
dQA2+ytYWV2GWC8EvOxbB0Z3iLSLAZrXbuJTCV5LRdrn8yb14eZQBsK+ZYL8LNJw
L3nh9FNYlTyZ6gmM9sunlX6MHfKPnbgKkTHXe9ieZhXTGrMKh2lNV5oG65Jvja8J
U4D69BrvWXhSpy6oe1z0R01JfPPwCXjbpbLv4kjIx4TmyqS1zscKQW5mvUVXDI+I
i59XUUMzEW4PGYGUzQ2QThEYzqlRUKSAF6tR+SfwZ0PGdrcs0b1ShyQvvSOF+tu6
5kaKSXt3YJMMYc4vXoI+n8OVrMfzzqMMuyuyVp3TflDRF6P7Z/c=
=trdL
-----END PGP SIGNATURE-----
Merge tag 'sunxi-h3-h5-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt
Allwinner H3/H5 support for 4.18
Here is our usual bunch of changes for the H3 and H5 SoCs that share the
same SoC design but with different CPUs.
This time, most of the changes are about supporting CPUFreq on these SoCs,
with voltage scaling being enabled for a number of boards.
* tag 'sunxi-h3-h5-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sun8i: h3: Add SY8106A regulator to Orange Pi PC
arm64: dts: allwinner: Add dts file for Libre Computer Board ALL-H3-CC H5 ver.
arm64: dts: allwinner: Sort dtb entries in Makefile
arm64: dts: allwinner: h5: Add cpu0 label for first cpu
ARM: dts: sun8i: h2+: Add Libre Computer Board ALL-H3-CC H2+ ver.
ARM: dts: sun8i: h2-plus: Sort dtb entries in Makefile
arm: dts: sun8i: h3: libretech-all-h3-cc: Move board definition to common dtsi
ARM: dts: sun8i: h3: fix ALL-H3-CC H3 ver VCC-1V2 regulator voltage
ARM: dts: sun8i: h3: set the cpu-supply to VDD-CPUX on ALL-H3-CC H3 ver
ARM: dts: sun8i: h3: fix ALL-H3-CC H3 ver VDD-CPUX voltage
ARM: dts: sun8i: h3: add SY8113B regulator used by Orange Pi One board
ARM: dts: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board
ARM: dts: sun8i: h3: add operating-points-v2 table for CPU
ARM: dts: sunxi: h3/h5: Add r_i2c I2C controller
ARM: dts: sunxi: h3/h5: Add r_i2c pinmux node
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add unit address for ls208xa-rdb SPI flash node matching 'reg'
property to fix DTC warning unit_address_vs_reg.
- Use hypen instead of underscore in aliases name for fsl-ls1012a to
fix DTC warning alias_paths.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJbAYmKAAoJEFBXWFqHsHzOD9oIAJqlVIlArr2KZfqwLrPrfklv
xN/079g26XlJW9X1hff4sFXudLrwCBDP4FBjscDf9q1aO5Xpxx9BC4zTi5Pk51mY
hT7azoPYdee89aWzeAWWTJz7mqgu81gFIg1tmuyqFgm1TRfkpHM28oSAcMf7p9XX
ZC2cokKQ2sOlPUGnl9S26n4An2fRhxK4/tFNBD4KKm+HxNmSe9frPwkgtoX+8bdF
zL0jNQ6FtNnyWPD96p+cVjxB2CJmNf+F97v8tLRCG83W2ZLr9Hp1tIbzyhZ/hGEL
qTXMeyWD5ZKNY6tZtHyjkG+wGbq+BCTr3vIl/pgINc473fox2mmEzp4bMSZEumo=
=Lh6Z
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt
Freescale arm64 device tree update for 4.18:
- Add unit address for ls208xa-rdb SPI flash node matching 'reg'
property to fix DTC warning unit_address_vs_reg.
- Use hypen instead of underscore in aliases name for fsl-ls1012a to
fix DTC warning alias_paths.
* tag 'imx-dt64-4.18' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: fsl-ls1012a: Fix DTC aliases warnings
arm64: dts: ls208xa-rdb: Pass unit name to SPI flash node
Signed-off-by: Olof Johansson <olof@lixom.net>
The msm8996 PCIe sits behind the "agnoc0", which is represented as a
simple-pm-bus, so enable support for this. Then enable the QMP phy
driver.
Also enable the atl1c ethernet driver and ath10k wlan driver to support
these components on the DragonBoard820c.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add serial, i2c, bam, spi, qpic peripheral nodes.
While here, fix the PMU node's irq trigger to avoid
the boot warnings from GIC.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Now that the driver has been merged for the HiSilicon
LPC host, enable the relevant config.
Turning on this config will also enable config
INDIRECT_PIO, which would have not been enabled
previously - see config info for more details.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
It enables driver support of Ethernet, eMMC, Combo/INNO phy and PCIe
for Hi3798CV200 Poplar platform.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
- Allow using Armada 3700 gpio controller as interrupt one too
- Describe SPI flash on the EspressoBin
- Mark ahci as dma-coherent for Armada 7K/8K
- Add 10G interface support Armada 7K/8K based boards (including MacBin)
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWv8DYwAKCRALBhiOFHI7
1XpdAKCGSSJQjUSkwu7luezYH9Hz0rRkkQCgoPNedba4WxKrKck5aIFiqHyaFBk=
=pUZZ
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.18-1' of git://git.infradead.org/linux-mvebu into next/dt
mvebu dt64 for 4.18 (part 1)
- Allow using Armada 3700 gpio controller as interrupt one too
- Describe SPI flash on the EspressoBin
- Mark ahci as dma-coherent for Armada 7K/8K
- Add 10G interface support Armada 7K/8K based boards (including MacBin)
* tag 'mvebu-dt64-4.18-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: armada-37xx: mark the gpio controllers as irq controller
arm64: dts: marvell: 7040-db: describe the 10G interface as fixed-link
arm64: dts: marvell: 8040-db: describe the 10G interfaces as fixed-link
arm64: dts: marvell: mcbin: enable the fourth network interface
arm64: dts: marvell: mcbin: add 10G SFP support
arm64: dts: marvell: mark CP110 ahci as dma-coherent
arm64: dts: armada-3720-espressobin: wire up spi flash
Signed-off-by: Olof Johansson <olof@lixom.net>
Adding thermal for Armada 7K/8K and SPI for Armada 3700
-----BEGIN PGP SIGNATURE-----
iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWv7/MgAKCRALBhiOFHI7
1SyaAKCbxPDR48yWie2ZLxneKc/xZu/QwQCffSpKG1EARKRgk/rz5frnF1vwUuw=
=olHS
-----END PGP SIGNATURE-----
Merge tag 'mvebu-arm64-4.18-1' of git://git.infradead.org/linux-mvebu into next/defconfig
mvebu arm64 for 4.18 (part 1)
Adding thermal for Armada 7K/8K and SPI for Armada 3700
* tag 'mvebu-arm64-4.18-1' of git://git.infradead.org/linux-mvebu:
arm64: defconfig: enable the Armada thermal driver
arm64: defconfig: enable CONFIG_SPI_ARMADA_3700
Signed-off-by: Olof Johansson <olof@lixom.net>
* Enable in ARM64 defconfig:
- Recently mainlined support for R-Car E3 (r8a77990) SoC
- HDMI sound and depdencies.
HDMI sound is used by R-Car Gen 3. These options are enabled as
modules to avoid unnecesesarily enlarging the kernel image.
-----BEGIN PGP SIGNATURE-----
iQIzBAABCAAdFiEE4nzZofWswv9L/nKF189kaWo3T74FAlr9Rz4ACgkQ189kaWo3
T75JCxAAscx34XKK/0kpWvLz5T7ogQh6h2oJa/wzT8vym3uJfq+kmjNazyTQqF8R
QvkUV/tvMkq2JirSw0OJG4kS3suzYqnF2kp2lzLOeE1TDT0ILwnW06aqHcdXDRji
/dV3Xq0WGCLOBiDjrBB2VeiwqgnfJnPsMfHXgwOHo8u4+Dpt6NDnR+me0zGzWOH8
ERAhS0nYlyCZjSq2Vyz+LNr06tKsVQpWork7X9jD8VvBjQa5BeulcUM7aq8FQRMY
nNOXSwB9pejlYFm3+kREYBwtyhpswHEgssBUqIP00vaV/uIxUKaocI6QsJkJJFQQ
3Mfkoar74aArRr/D+91OcxPo2b2pdH8GxVkWslmfkjBW9DT30VKUeCDB1pMigVbD
1XP06ZtuDGZevFG7wjeAbRf44m5XVvXJhnK2O9waRPbLAuajmi8E+svJQu9qMCtZ
Ddkv05vuJcKLK6xohw0/BO+G+IK/ZdgzZ+4zOUO8YcmJDRRKQ9dFH5Fc3KHH4uw4
OWNfoyY6YAVgksLJfxK6zUqWzakJZtmZFisOFN+LDCbspCF9U3yHdCSao/XGyKP4
CvXm9pF+nDHUh6lTwKY5Ha+pKXHMr6W/7+EuQEZTayf+sizPDHWrDT6cvp62YK5m
Fc/3YfpkCbOmoObRTRssXyq4ipIMgrKtvNzYPge4eC3LQvEihAE=
=pmB3
-----END PGP SIGNATURE-----
Merge tag 'renesas-arm64-defconfig-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/defconfig
Renesas ARM64 Based SoC Defconfig Updates for v4.18
* Enable in ARM64 defconfig:
- Recently mainlined support for R-Car E3 (r8a77990) SoC
- HDMI sound and depdencies.
HDMI sound is used by R-Car Gen 3. These options are enabled as
modules to avoid unnecesesarily enlarging the kernel image.
* tag 'renesas-arm64-defconfig-for-v4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: defconfig: enable R8A77990 SoC
arm64: defconfig: Enable CONFIG_SND_AUDIO_GRAPH_CARD
arm64: defconfig: makes SND_SIMPLE_CARD to module
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add mailbox, stub clock, CPU frequency scaling, thermal cooling
management and pcie msi interruption support for hi3660
- Add LPC support for hip06 and hip07
- Add PCIe, usb and emmc support for hi3798cv200
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJa+umIAAoJEAvIV27ZiWZcItwP/R4kgy+0SKzmHzTXVdfIv1UT
PrxVLLBsGfk2XosBfLAOGOIR7eVH4AtYWs1J6Nsu8yIs1df3+YdUeapOpdzGJiA3
rKG5boI4v2rrMQ75T8gXXzePAth+zgwC3JFKFZioU2kpBYLW1GM9spT7dhdb+Xj8
gETrp/I120KrtSCAmxwT0dG0n0uwDB1ZtWGTDiVFJD6A5LNJte96kd5haShMqLo1
HACVKNc5i5QqfLu/NjsNxu5KBUYUjgHbZnuqbnpfGi2mBjlLYnfp/l0Qu88nfbiO
xVlWem7H0OziO5XxNNaLk8mZ9jZw+Ak9sspDa9+htM4GMkqM0z6WdN52E9Guj1Ll
xOl3ZghM3Z/qwZB4Rnlduhi2R7IKi6el+942Kc3A6gyhJaifHxBn4+BMJ2t1UytR
zTIEj+YhgYQ37TvR/PZkESrAXxpKtH4CwNRZ7gycWBJaVhSGsZTGEW53AnqeTAOf
EKGDoQ/iyZ/T4vNArCAGa7V1Opf3P4pj60rnc8gC6AidDlys9cKEFmkOXTtdFJe0
D3DW9pVIstUm31znKSob13DRHZLPMyoui1ZjDNrbEPLp9ayY5FVkEg2c/1w/dUvo
wNfpTWhgQB8mvsqiQ5P4urjyv9Gv45v4GfRB7GAAed9s7YYXzOmuOpktthQMmLl/
/Zjt36JIyhQ8g//E44NC
=7lcf
-----END PGP SIGNATURE-----
Merge tag 'hisi-arm64-dt-for-4.18v2' of git://github.com/hisilicon/linux-hisi into next/dt
ARM64: DT: Hisilicon SoC DT updates for 4.18v2
- Add mailbox, stub clock, CPU frequency scaling, thermal cooling
management and pcie msi interruption support for hi3660
- Add LPC support for hip06 and hip07
- Add PCIe, usb and emmc support for hi3798cv200
* tag 'hisi-arm64-dt-for-4.18v2' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hi3798cv200: enable emmc support for poplar board
arm64: dts: hi3798cv200: enable usb2 support for poplar board
arm64: dts: hi3798cv200: enable PCIe support for poplar board
arm64: dts: hisi: Enable Hisi LPC node for hip07
arm64: dts: hisi: Enable Hisi LPC node for hip06
arm64: dts: hi3660: Add pcie msi interrupt attribute
arm64: dts: hi3660: Add thermal cooling management
arm64: dts: hi3660: Add CPU frequency scaling support
arm64: dts: hi3660: Add stub clock node
arm64: dts: hi3660: Add mailbox node
Signed-off-by: Olof Johansson <olof@lixom.net>
This new attribute allows the userspace to set the base address
of a reditributor region, relaxing the constraint of having all
consecutive redistibutor frames contiguous.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The conversion of the FPSIMD context switch trap code to C has added
some overhead to calling it, due to the need to save registers that
the procedure call standard defines as caller-saved.
So, perhaps it is no longer worth invoking this trap handler quite
so early.
Instead, we can invoke it from fixup_guest_exit(), with little
likelihood of increasing the overhead much further.
As a convenience, this patch gives __hyp_switch_fpsimd() the same
return semantics fixup_guest_exit(). For now there is no
possibility of a spurious FPSIMD trap, so the function always
returns true, but this allows it to be tail-called with a single
return statement.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The entire tail of fixup_guest_exit() is contained in if statements
of the form if (x && *exit_code == ARM_EXCEPTION_TRAP). As a result,
we can check just once and bail out of the function early, allowing
the remaining if conditions to be simplified.
The only awkward case is where *exit_code is changed to
ARM_EXCEPTION_EL1_SERROR in the case of an illegal GICv2 CPU
interface access: in that case, the GICv3 trap handling code is
skipped using a goto. This avoids pointlessly evaluating the
static branch check for the GICv3 case, even though we can't have
vgic_v2_cpuif_trap and vgic_v3_cpuif_trap true simultaneously
unless we have a GICv3 and GICv2 on the host: that sounds stupid,
but I haven't satisfied myself that it can't happen.
No functional change.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In fixup_guest_exit(), there are a couple of cases where after
checking what the exit code was, we assign it explicitly with the
value it already had.
Assuming this is not indicative of a bug, these assignments are not
needed.
This patch removes the redundant assignments, and simplifies some
if-nesting that becomes trivial as a result.
No functional change.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Now that the host SVE context can be saved on demand from Hyp,
there is no longer any need to save this state in advance before
entering the guest.
This patch removes the relevant call to
kvm_fpsimd_flush_cpu_state().
Since the problem that function was intended to solve now no longer
exists, the function and its dependencies are also deleted.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This patch adds SVE context saving to the hyp FPSIMD context switch
path. This means that it is no longer necessary to save the host
SVE state in advance of entering the guest, when in use.
In order to avoid adding pointless complexity to the code, VHE is
assumed if SVE is in use. VHE is an architectural prerequisite for
SVE, so there is no good reason to turn CONFIG_ARM64_VHE off in
kernels that support both SVE and KVM.
Historically, software models exist that can expose the
architecturally invalid configuration of SVE without VHE, so if
this situation is detected at kvm_init() time then KVM will be
disabled.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In order to make sve_save_state()/sve_load_state() more easily
reusable and to get rid of a potential branch on context switch
critical paths, this patch makes sve_pffr() inline and moves it to
fpsimd.h.
<asm/processor.h> must be included in fpsimd.h in order to make
this work, and this creates an #include cycle that is tricky to
avoid without modifying core code, due to the way the PR_SVE_*()
prctl helpers are included in the core prctl implementation.
Instead of breaking the cycle, this patch defers inclusion of
<asm/fpsimd.h> in <asm/processor.h> until the point where it is
actually needed: i.e., immediately before the prctl definitions.
No functional change.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
sve_pffr(), which is used to derive the base address used for
low-level SVE save/restore routines, currently takes the relevant
task_struct as an argument.
The only accessed fields are actually part of thread_struct, so
this patch changes the argument type accordingly. This is done in
preparation for moving this function to a header, where we do not
want to have to include <linux/sched.h> due to the consequent
circular #include problems.
No functional change.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Having read_zcr_features() inline in cpufeature.h results in that
header requiring #includes which make it hard to include
<asm/fpsimd.h> elsewhere without triggering header inclusion
cycles.
This is not a hot-path function and arguably should not be in
cpufeature.h in the first place, so this patch moves it to
fpsimd.c, compiled conditionally if CONFIG_ARM64_SVE=y.
This allows some SVE-related #includes to be dropped from
cpufeature.h, which will ease future maintenance.
A couple of missing #includes of <asm/fpsimd.h> are exposed by this
change under arch/arm64/. This patch adds the missing #includes as
necessary.
No functional change.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This patch refactors KVM to align the host and guest FPSIMD
save/restore logic with each other for arm64. This reduces the
number of redundant save/restore operations that must occur, and
reduces the common-case IRQ blackout time during guest exit storms
by saving the host state lazily and optimising away the need to
restore the host state before returning to the run loop.
Four hooks are defined in order to enable this:
* kvm_arch_vcpu_run_map_fp():
Called on PID change to map necessary bits of current to Hyp.
* kvm_arch_vcpu_load_fp():
Set up FP/SIMD for entering the KVM run loop (parse as
"vcpu_load fp").
* kvm_arch_vcpu_ctxsync_fp():
Get FP/SIMD into a safe state for re-enabling interrupts after a
guest exit back to the run loop.
For arm64 specifically, this involves updating the host kernel's
FPSIMD context tracking metadata so that kernel-mode NEON use
will cause the vcpu's FPSIMD state to be saved back correctly
into the vcpu struct. This must be done before re-enabling
interrupts because kernel-mode NEON may be used by softirqs.
* kvm_arch_vcpu_put_fp():
Save guest FP/SIMD state back to memory and dissociate from the
CPU ("vcpu_put fp").
Also, the arm64 FPSIMD context switch code is updated to enable it
to save back FPSIMD state for a vcpu, not just current. A few
helpers drive this:
* fpsimd_bind_state_to_cpu(struct user_fpsimd_state *fp):
mark this CPU as having context fp (which may belong to a vcpu)
currently loaded in its registers. This is the non-task
equivalent of the static function fpsimd_bind_to_cpu() in
fpsimd.c.
* task_fpsimd_save():
exported to allow KVM to save the guest's FPSIMD state back to
memory on exit from the run loop.
* fpsimd_flush_state():
invalidate any context's FPSIMD state that is currently loaded.
Used to disassociate the vcpu from the CPU regs on run loop exit.
These changes allow the run loop to enable interrupts (and thus
softirqs that may use kernel-mode NEON) without having to save the
guest's FPSIMD state eagerly.
Some new vcpu_arch fields are added to make all this work. Because
host FPSIMD state can now be saved back directly into current's
thread_struct as appropriate, host_cpu_context is no longer used
for preserving the FPSIMD state. However, it is still needed for
preserving other things such as the host's system registers. To
avoid ABI churn, the redundant storage space in host_cpu_context is
not removed for now.
arch/arm is not addressed by this patch and continues to use its
current save/restore logic. It could provide implementations of
the helpers later if desired.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In struct vcpu_arch, the debug_flags field is used to store
debug-related flags about the vcpu state.
Since we are about to add some more flags related to FPSIMD and
SVE, it makes sense to add them to the existing flags field rather
than adding new fields. Since there is only one debug_flags flag
defined so far, there is plenty of free space for expansion.
In preparation for adding more flags, this patch renames the
debug_flags field to simply "flags", and updates comments
appropriately.
The flag definitions are also moved to <asm/kvm_host.h>, since
their presence in <asm/kvm_asm.h> was for purely historical
reasons: these definitions are not used from asm any more, and not
very likely to be as more Hyp asm is migrated to C.
KVM_ARM64_DEBUG_DIRTY_SHIFT has not been used since commit
1ea66d27e7 ("arm64: KVM: Move away from the assembly version of
the world switch"), so this patch gets rid of that too.
No functional change.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@arm.com>
[maz: fixed minor conflict]
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In preparation for optimising the way KVM manages switching the
guest and host FPSIMD state, it is necessary to provide a means for
code outside arch/arm64/kernel/fpsimd.c to restore the user trap
configuration for SVE correctly for the current task.
Rather than requiring external code to duplicate the maintenance
explicitly, this patch moves the trap maintenenace to
fpsimd_bind_to_cpu(), since it is logically part of the work of
associating the current task with the cpu.
Because fpsimd_bind_to_cpu() is rather a cryptic name to publish
alongside fpsimd_bind_state_to_cpu(), the former function is
renamed to fpsimd_bind_task_to_cpu() to make its purpose more
explicit.
This patch makes appropriate changes to ensure that
fpsimd_bind_task_to_cpu() is always called alongside
task_fpsimd_load(), so that the trap maintenance continues to be
done in every situation where it was done prior to this patch.
As a side-effect, the metadata updates done by
fpsimd_bind_task_to_cpu() now change from conditional to
unconditional in the "already bound" case of sigreturn. This is
harmless, and a couple of extra stores on this slow path will not
impact performance. I consider this a reasonable price to pay for
a slightly cleaner interface.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Currently the FPSIMD handling code uses the condition task->mm ==
NULL as a hint that task has no FPSIMD register context.
The ->mm check is only there to filter out tasks that cannot
possibly have FPSIMD context loaded, for optimisation purposes.
Also, TIF_FOREIGN_FPSTATE must always be checked anyway before
saving FPSIMD context back to memory. For these reasons, the ->mm
checks are not useful, providing that TIF_FOREIGN_FPSTATE is
maintained in a consistent way for all threads.
The context switch logic is already deliberately optimised to defer
reloads of the regs until ret_to_user (or sigreturn as a special
case), and save them only if they have been previously loaded.
These paths are the only places where the wrong_task and wrong_cpu
conditions can be made false, by calling fpsimd_bind_task_to_cpu().
Kernel threads by definition never reach these paths. As a result,
the wrong_task and wrong_cpu tests in fpsimd_thread_switch() will
always yield true for kernel threads.
This patch removes the redundant checks and special-case code,
ensuring that TIF_FOREIGN_FPSTATE is set whenever a kernel thread
is scheduled in, and ensures that this flag is set for the init
task. The fpsimd_flush_task_state() call already present in
copy_thread() ensures the same for any new task.
With TIF_FOREIGN_FPSTATE always set for kernel threads, this patch
ensures that no extra context save work is added for kernel
threads, and eliminates the redundant context saving that may
currently occur for kernel threads that have acquired an mm via
use_mm().
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
The init task is started with thread_flags equal to 0, which means
that TIF_FOREIGN_FPSTATE is initially clear.
It is theoretically possible (if unlikely) that the init task could
reach userspace without ever being scheduled out. If this occurs,
data left in the FPSIMD registers by the kernel could be exposed.
This patch fixes this anomaly by ensuring that the init task's
initial TIF_FOREIGN_FPSTATE is set.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Fixes: 005f78cd88 ("arm64: defer reloading a task's FPSIMD state to userland resume")
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
In preparation for allowing non-task (i.e., KVM vcpu) FPSIMD
contexts to be handled by the fpsimd common code, this patch adapts
task_fpsimd_save() to save back the currently loaded context,
removing the explicit dependency on current.
The relevant storage to write back to in memory is now found by
examining the fpsimd_last_state percpu struct.
fpsimd_save() does nothing unless TIF_FOREIGN_FPSTATE is clear, and
fpsimd_last_state is updated under local_bh_disable() or
local_irq_disable() everywhere that TIF_FOREIGN_FPSTATE is cleared:
thus, fpsimd_save() will write back to the correct storage for the
loaded context.
No functional change.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
To make the lazy FPSIMD context switch trap code easier to hack on,
this patch converts it to C.
This is not amazingly efficient, but the trap should typically only
be taken once per host context switch.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
This patch uses the new update_thread_flag() helpers to simplify a
couple of if () set; else clear; constructs.
No functional change.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
fpsimd_last_state.st is set to NULL as a way of indicating that
current's FPSIMD registers are no longer loaded in the cpu. In
particular, this is done when the kernel temporarily uses or
clobbers the FPSIMD registers for its own purposes, as in CPU PM or
kernel-mode NEON, resulting in them being populated with garbage
data not belonging to a task.
Commit 17eed27b02 ("arm64/sve: KVM: Prevent guests from using
SVE") factors this operation out as a new helper
fpsimd_flush_cpu_state() to make it clearer what is being done
here, and on SVE systems this helper is now used, via
kvm_fpsimd_flush_cpu_state(), to invalidate the registers after KVM
has run a vcpu. The reason for this is that KVM does not yet
understand how to restore the full host SVE registers itself after
loading the guest FPSIMD context into them.
This exposes a particular problem: if fpsimd_last_state.st is set
to NULL without also setting TIF_FOREIGN_FPSTATE, the kernel may
continue to think that current's FPSIMD registers are live even
though they have actually been clobbered.
Prior to the aforementioned commit, the only path where
fpsimd_last_state.st is set to NULL without setting
TIF_FOREIGN_FPSTATE is when kernel_neon_begin() is called by a
kernel thread (where current->mm can be NULL). This does not
matter, because the only harm is that at context-switch time
fpsimd_thread_switch() may unnecessarily save the FPSIMD registers
back to current's thread_struct (even though kernel threads are not
considered to have any FPSIMD context of their own and the
registers will never be reloaded).
Note that although CPU_PM_ENTER lacks the TIF_FOREIGN_FPSTATE
setting, every CPU passing through that path must subsequently pass
through CPU_PM_EXIT before it can re-enter the kernel proper.
CPU_PM_EXIT sets the flag.
The sve_flush_cpu_state() function added by commit 17eed27b02
also lacks the proper maintenance of TIF_FOREIGN_FPSTATE. This may
cause the bits of a host task's SVE registers that do not alias the
FPSIMD register file to spontaneously appear zeroed if a KVM vcpu
runs in the same task in the meantime. Although this effect is
hidden by the fact that the non-FPSIMD bits of the SVE registers
are zeroed by a syscall anyway, it is doubtless a bad idea to rely
on these different code paths interacting correctly under future
maintenance.
This patch makes TIF_FOREIGN_FPSTATE an unconditional side-effect
of fpsimd_flush_cpu_state(), and removes the set_thread_flag()
calls that become redundant as a result. This ensures that
TIF_FOREIGN_FPSTATE cannot remain clear if the FPSIMD state in the
FPSIMD registers is invalid.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Enable GLINK RPM so that we get RPM regulators and clocks and enable the
UFS host controller driver and the Qualcomm UFS platform driver. The UFS
phy is selected by the Qualcomm UFS driver.
The simple ondemand devfreq governor must be builtin, as there's no
mechanism for automatically loading it, causing UFS HCD initialization
to fail.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Commit 15122ee2c5 ("arm64: Enforce BBM for huge IO/VMAP mappings")
disallowed block mappings for ioremap since that code does not honor
break-before-make. The same APIs are also used for permission updating
though and the extra checks prevent the permission updates from happening,
even though this should be permitted. This results in read-only permissions
not being fully applied. Visibly, this can occasionaly be seen as a failure
on the built in rodata test when the test data ends up in a section or
as an odd RW gap on the page table dump. Fix this by using
pgattr_change_is_safe instead of p*d_present for determining if the
change is permitted.
Reviewed-by: Kees Cook <keescook@chromium.org>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reported-by: Peter Robinson <pbrobinson@gmail.com>
Fixes: 15122ee2c5 ("arm64: Enforce BBM for huge IO/VMAP mappings")
Signed-off-by: Laura Abbott <labbott@redhat.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Follow the recent trend for the license description, and also fix the
wrongly stated X11 to MIT.
As already pointed on the DT ML, the X11 license text [1] is explicitly
for the X Consortium and has a couple of extra clauses. The MIT
license text [2] is actually what the current DT files claim.
[1] https://spdx.org/licenses/X11.html
[2] https://spdx.org/licenses/MIT.html
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
>From the hardware perspective, the actual pclk of the AO uarts
is the corresponding clkc_ao uart gate, not the main clock controller clk81.
This was not problem so far, because the uart_gate had
the CLK_IGNORE_UNUSED flag, which kept the gate open.
We plan to remove the CLK_IGNORE_UNUSED flag in another patch,
but before doing that, we need to fix the clock in the DTS file.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This add the AO (Always-On part) clock DT info for Meson-AXG SoC
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
[khilman: cleanup subject]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add all '1x' clocks to decon and decontv devices. Enabling those clocks
is needed to get proper display on hardware windows no 4 and 5.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The i2c AO is used for the MIC daughter card of the S400 board
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add the pins related to the i2c AO controller of the meson-axg platform
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
The clock specified for the i2c AO controller is the one for the EE
domain, which is incorrect as this controller needs the clock for AO
i2c controller.
Fixes: dc6f858e26 ("ARM64: dts: meson-axg: add I2C DT info for Meson-AXG SoC")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Remove undocumented and unused "clk_i2c" clock name and the second
interrupt from i2c nodes of meson-axg platform. Those seems to have
been copy/pasted from the vendor kernel
Fixes: dc6f858e26 ("ARM64: dts: meson-axg: add I2C DT info for Meson-AXG SoC")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
In do_page_fault(), we handle some kernel faults early, and simply
die() with a message. For faults handled later, we dump the faulting
address, decode the ESR, walk the page tables, and perform a number of
steps to ensure that this data is reported.
Let's unify the handling of fatal kernel faults with a new
die_kernel_fault() helper, handling all of these details. This is
largely the same as the existing logic in __do_kernel_fault(), except
that addresses are consistently padded to 16 hex characters, as would be
expected for a 64-bit address.
The messages currently logged in do_page_fault are adjusted to fit into
the die_kernel_fault() message template.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
The naming of is_permission_fault() makes it sound like it should return
true for permission faults from EL0, but by design, it only does so for
faults from EL1.
Let's make this clear by dropping el1 in the name, as we do for
is_el1_instruction_abort().
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Now that we're seeing CPUs shipping with LSE atomics, default them to
'on' in Kconfig. CPUs without the instructions will continue to use
LDXR/STXR-based sequences, but they will be placed out-of-line by the
compiler.
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Add the UFS QMP phy node and the UFS host controller node, now that we
have working UFS and the necessary clocks in place.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb5b "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Tested-by: Amit Kucheria <amit.kucheria@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This is pure-churn and should be a no-op. I'm doing it in the hopes
of reducing merge conflicts. When things are sorted in a sane way
(and by base address seems sane) then it's less likely that future
patches will cause merge conflicts.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Let's keep the reserved-memory node tidy and neat and keep it sorted
by address. This should have no functional change.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add command DB node based on the bindings example.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The RPMh clock driver assumes that the xo_board clock is named
"xo_board", not "xo-board". Add a "clock-output-names" property to
the device tree to get the right name.
Also add the proper speed for the xo-clock as 38400000. This is
internally divided in RPMh clock driver to get "bi_tcxo" at 19200000.
After this change the clock tree in /sys/kernel/debug/clk/clk_summary
looks much better.
NOTES:
- Technically you could argue that this clock could belong in board
.dts files, not in the SoC one. However at the moment it's believed
that 100% of sdm845 boards will have an external clock at 38.4. It
can always be moved later if necessary.
- We could rename the "xo-board" device tree node to "xo_board" to
achieve the same effect as this patch. Presumably device-tree folks
would rather keep node names using dashes though.
- We could change the RPMh clock driver to use a dash to achieve the
same effect as this patch, but all other clocks in the clock tree
use underscores. It seems silly to change just this one.
Fixes: 7bafa643647f ("arm64: dts: sdm845: Add minimal dts/dtsi files for sdm845 SoC and MTP")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add all the necessary dt nodes to support SMEM driver
on SDM845. It also adds the required memory carveouts
so that the kernel does not access memory that is in
use.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch add the node to support APSS shared
mailbox on SDM845
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Remove the usage of IRQ_TYPE_NONE to fix loud warnings from
patch (83a86fbb5b "irqchip/gic: Loudly complain about
the use of IRQ_TYPE_NONE").
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Thierry Escande <thierry.escande@linaro.org>
Tested-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch adds missing microSD card supplies, without this uSD
card will not be detected.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add a new serial node for the Qualcomm BT controller QCA6174. This
allows automatic probing and hci registration through the serdev
framework instead of relying on the userspace helpers.
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This patch enables regulators and gpios for the Qualcomm QCA6174 BT/WLAN
combo controller.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Thierry Escande <thierry.escande@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The node name for a PCIe host bridge must be "pcie" as required by
the binging. dtc now warns about it:
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb: Warning (pci_bridge): /soc/agnoc@0/qcom,pcie@610000: node name is not "pci" or "pcie"
arch/arm64/boot/dts/qcom/apq8096-db820c.dtb: Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge'
arch/arm64/boot/dts/qcom/msm8996-mtp.dtb: Warning (pci_bridge): /soc/agnoc@0/qcom,pcie@610000: node name is not "pci" or "pcie"
arch/arm64/boot/dts/qcom/msm8996-mtp.dtb: Warning (pci_device_bus_num): Failed prerequisite 'pci_bridge'
This renames the nodes as appropriate.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
With the addition of this ramoops node it enables post mortem
analysis if a debug cable is not attached and/or not available.
All addresses and values were extracted from CAF AOSP marshmallow
DR 1.6.
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This enables SDHCI on the Nexus 5X as well creates common smd_rpm node
which can be shared between both 5X and 6P as per HW design.
Given the lack of documentation, only downstream code was used as a reference
and it eludes to the fact that 8994-rpm-regulator is common between both msm8992
& msm8994. [ see msm.git branch: msm-angler-3.10-marshmallow-mr1, msm8992.dtsi]
At this early stage of development it makes sense for the 8994-rpm-regulator
to be common until data / documentation suggests otherwise.
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
If userspace faults on a kernel address, handing them the raw ESR
value on the sigframe as part of the delivered signal can leak data
useful to attackers who are using information about the underlying hardware
fault type (e.g. translation vs permission) as a mechanism to defeat KASLR.
However there are also legitimate uses for the information provided
in the ESR -- notably the GCC and LLVM sanitizers use this to report
whether wild pointer accesses by the application are reads or writes
(since a wild write is a more serious bug than a wild read), so we
don't want to drop the ESR information entirely.
For faulting addresses in the kernel, sanitize the ESR. We choose
to present userspace with the illusion that there is nothing mapped
in the kernel's part of the address space at all, by reporting all
faults as level 0 translation faults taken to EL1.
These fields are safe to pass through to userspace as they depend
only on the instruction that userspace used to provoke the fault:
EC IL (always)
ISV CM WNR (for all data aborts)
All the other fields in ESR except DFSC are architecturally RES0
for an L0 translation fault taken to EL1, so can be zeroed out
without confusing userspace.
The illusion is not entirely perfect, as there is a tiny wrinkle
where we will report an alignment fault that was not due to the memory
type (for instance a LDREX to an unaligned address) as a translation
fault, whereas if you do this on real unmapped memory the alignment
fault takes precedence. This is not likely to trip anybody up in
practice, as the only users we know of for the ESR information who
care about the behaviour for kernel addresses only really want to
know about the WnR bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
S390 bpf_jit.S is removed in net-next and had changes in 'net',
since that code isn't used any more take the removal.
TLS data structures split the TX and RX components in 'net-next',
put the new struct members from the bug fix in 'net' into the RX
part.
The 'net-next' tree had some reworking of how the ERSPAN code works in
the GRE tunneling code, overlapping with a one-line headroom
calculation fix in 'net'.
Overlapping changes in __sock_map_ctx_update_elem(), keep the bits
that read the prog members via READ_ONCE() into local variables
before using them.
Signed-off-by: David S. Miller <davem@davemloft.net>
Otherwise modules that use these arithmetic operations will fail to
link. We accomplish this with the usual EXPORT_SYMBOL, which on most
architectures goes in the .S file but the ARM64 maintainers prefer that
insead it goes into arm64ksyms.
While we're at it, we also fix this up to use SPDX, and I personally
choose to relicense this as GPL2||BSD so that these symbols don't need
to be export_symbol_gpl, so all modules can use the routines, since
these are important general purpose compiler-generated function calls.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reported-by: PaX Team <pageexec@freemail.hu>
Cc: stable@vger.kernel.org
Signed-off-by: Will Deacon <will.deacon@arm.com>
