Commit Graph

211 Commits

Author SHA1 Message Date
Wei Yang
d74b9027a4 PCI: Consider additional PF's IOV BAR alignment in sizing and assigning
When sizing and assigning resources, we divide the resources into two
lists: the requested list and the additional list.  We don't consider the
alignment of additional VF(n) BAR space.

This is because the alignment required for the VF(n) BAR space is the size
of an individual VF BAR, not the size of the space for *all* VFs.  But we
want additional alignment to support partitioning on PowerNV.

Consider the additional IOV BAR alignment when sizing and assigning
resources.  When there is not enough system MMIO space to accomodate both
the requested list and the additional list, the PF's IOV BAR alignment will
not contribute to the bridge. When there is enough system MMIO space for
both lists, the additional alignment will contribute to the bridge.

The additional alignment is stored in the min_align of pci_dev_resource,
which is stored in the additional list by add_to_list() at the end of
pbus_size_mem(). The additional alignment is calculated in
pci_resource_alignment().  For an IOV BAR, we have arch dependent function
to get the alignment for different arch.

[bhelgaas: changelog, printk cast]
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2015-03-31 13:02:37 +11:00
Yinghai Lu
8505e729a2 PCI: Add pci_claim_bridge_resource() to clip window if necessary
Add pci_claim_bridge_resource() to claim a PCI-PCI bridge window.  This is
like regular pci_claim_resource(), except that if we fail to claim the
window, we check to see if we can reduce the size of the window and try
again.

This is for scenarios like this:

  pci_bus 0000:00: root bus resource [mem 0xc0000000-0xffffffff]
  pci 0000:00:01.0:   bridge window [mem 0xbdf00000-0xddefffff 64bit pref]
  pci 0000:01:00.0: reg 0x10: [mem 0xc0000000-0xcfffffff pref]

The 00:01.0 window is illegal: it starts before the host bridge window, so
we have to assume the [0xbdf00000-0xbfffffff] region is inaccessible.  We
can make it legal by clipping it to [mem 0xc0000000-0xddefffff 64bit pref].

Previously we discarded the 00:01.0 window and tried to reassign that part
of the hierarchy from scratch.  That is a problem because Linux doesn't
always assign things optimally.  For example, in this case, BIOS put the
01:00.0 device in a prefetchable window below 4GB, but after 5b28541552,
Linux puts the prefetchable window above 4GB where the 32-bit 01:00.0
device can't use it.

Clipping the 00:01.0 window is less intrusive than completely reassigning
things and is sufficient to let us use most of the BIOS configuration.  Of
course, it's possible that devices below 00:01.0 will no longer fit.  If
that's the case, we'll have to reassign things.  But that's a separate
problem.

[bhelgaas: changelog, split into separate patch]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=85491
Reported-by: Marek Kordik <kordikmarek@gmail.com>
Fixes: 5b28541552 ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v3.16+
2015-01-16 10:04:42 -06:00
Yinghai Lu
3f2f4dc456 PCI: Pass bridge device, not bus, when updating bridge windows
pci_setup_bridge_io(), pci_setup_bridge_mmio(), and
pci_setup_bridge_mmio_pref() program the windows of PCI-PCI bridges.
Previously they accepted a pointer to the pci_bus of the secondary bus,
then looked up the bridge leading to that bus.  Pass the bridge directly,
which will make it more convenient for future callers.

No functional change.

[bhelgaas: changelog, split into separate patch]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=85491
Reported-by: Marek Kordik <kordikmarek@gmail.com>
Fixes: 5b28541552 ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v3.16+
2015-01-16 10:04:42 -06:00
Yinghai Lu
d61b0e87d2 PCI: Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources()
In 5b28541552 ("PCI: Restrict 64-bit prefetchable bridge windows to
64-bit resources"), we added IORESOURCE_MEM_64 to the mask in
pci_assign_unassigned_root_bus_resources(), but not to the mask in
pci_assign_unassigned_bridge_resources().

Add IORESOURCE_MEM_64 to the pci_assign_unassigned_bridge_resources() type
mask.

Fixes: 5b28541552 ("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources")
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v3.16+
2014-09-30 13:56:46 -06:00
Yinghai Lu
096d4221f9 PCI: Support BAR sizes up to 128GB
Increase the maximum BAR size from 8GB to 128GB.

[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-07-08 16:17:26 -06:00
Ryan Desfosses
227f064705 PCI: Merge multi-line quoted strings
Merge quoted strings that are broken across lines into a single entity.
The compiler merges them anyway, but checkpatch complains about it, and
merging them makes it easier to grep for strings.

No functional change.

[bhelgaas: changelog, do the same for everything under drivers/pci]
Signed-off-by: Ryan Desfosses <ryan@desfo.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-06-10 20:20:42 -06:00
Ryan Desfosses
3c78bc61f5 PCI: Whitespace cleanup
Fix various whitespace errors.

No functional change.

[bhelgaas: fix other similar problems]
Signed-off-by: Ryan Desfosses <ryan@desfo.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-06-10 20:20:19 -06:00
Bjorn Helgaas
d1a2523d2a Merge branches 'pci/hotplug', 'pci/pci_is_bridge' and 'pci/virtualization' into next
* pci/hotplug:
  PCI: cpqphp: Fix possible null pointer dereference
  NVMe: Implement PCIe reset notification callback
  PCI: Notify driver before and after device reset

* pci/pci_is_bridge:
  pcmcia: Use pci_is_bridge() to simplify code
  PCI: pciehp: Use pci_is_bridge() to simplify code
  PCI: acpiphp: Use pci_is_bridge() to simplify code
  PCI: cpcihp: Use pci_is_bridge() to simplify code
  PCI: shpchp: Use pci_is_bridge() to simplify code
  PCI: rpaphp: Use pci_is_bridge() to simplify code
  sparc/PCI: Use pci_is_bridge() to simplify code
  powerpc/PCI: Use pci_is_bridge() to simplify code
  ia64/PCI: Use pci_is_bridge() to simplify code
  x86/PCI: Use pci_is_bridge() to simplify code
  PCI: Use pci_is_bridge() to simplify code
  PCI: Add new pci_is_bridge() interface
  PCI: Rename pci_is_bridge() to pci_has_subordinate()

* pci/virtualization:
  PCI: Introduce new device binding path using pci_dev.driver_override

Conflicts:
	drivers/pci/pci-sysfs.c
2014-05-28 16:21:07 -06:00
Yijing Wang
6788a51fe3 PCI: Use pci_is_bridge() to simplify code
Use pci_is_bridge() to simplify code.  No functional change.

Requires: 326c1cdae7 PCI: Rename pci_is_bridge() to pci_has_subordinate()
Requires: 1c86438c94 PCI: Add new pci_is_bridge() interface
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-05-27 14:53:41 -06:00
Bjorn Helgaas
e5558d1a51 Merge branches 'dma-api', 'pci/virtualization', 'pci/msi', 'pci/misc' and 'pci/resource' into next
* dma-api:
  iommu/exynos: Remove unnecessary "&" from function pointers
  DMA-API: Update dma_pool_create ()and dma_pool_alloc() descriptions
  DMA-API: Fix duplicated word in DMA-API-HOWTO.txt
  DMA-API: Capitalize "CPU" consistently
  sh/PCI: Pass GAPSPCI_DMA_BASE CPU & bus address to dma_declare_coherent_memory()
  DMA-API: Change dma_declare_coherent_memory() CPU address to phys_addr_t
  DMA-API: Clarify physical/bus address distinction

* pci/virtualization:
  PCI: Mark RTL8110SC INTx masking as broken

* pci/msi:
  PCI/MSI: Remove pci_enable_msi_block()

* pci/misc:
  PCI: Remove pcibios_add_platform_entries()
  s390/pci: use pdev->dev.groups for attribute creation
  PCI: Move Open Firmware devspec attribute to PCI common code

* pci/resource:
  PCI: Add resource allocation comments
  PCI: Simplify __pci_assign_resource() coding style
  PCI: Change pbus_size_mem() return values to be more conventional
  PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources
  PCI: Support BAR sizes up to 8GB
  resources: Clarify sanity check message
  PCI: Don't add disabled subtractive decode bus resources
  PCI: Don't print anything while decoding is disabled
  PCI: Don't set BAR to zero if dma_addr_t is too small
  PCI: Don't convert BAR address to resource if dma_addr_t is too small
  PCI: Reject BAR above 4GB if dma_addr_t is too small
  PCI: Fail safely if we can't handle BARs larger than 4GB
  x86/gart: Tidy messages and add bridge device info
  x86/gart: Replace printk() with pr_info()
  x86/PCI: Move pcibios_assign_resources() annotation to definition
  x86/PCI: Mark ATI SBx00 HPET BAR as IORESOURCE_PCI_FIXED
  x86/PCI: Don't try to move IORESOURCE_PCI_FIXED resources
  x86/PCI: Fix Broadcom CNB20LE unintended sign extension
2014-05-26 17:29:17 -06:00
Bjorn Helgaas
67d29b5c6c PCI: Add resource allocation comments
Add comments in the code to match the allocation strategy of 7c671426dfc3
("PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources").

No functional change.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-05-23 12:40:49 -06:00
Bjorn Helgaas
30afe8d00b PCI: Change pbus_size_mem() return values to be more conventional
pbus_size_mem() previously returned 0 for failure and 1 for success.
Change it to return -ENOSPC for failure and 0 for success.

No functional change.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-05-23 12:40:48 -06:00
Yinghai Lu
5b28541552 PCI: Restrict 64-bit prefetchable bridge windows to 64-bit resources
This patch changes the way we handle 64-bit prefetchable bridge windows to
make it more likely that we can assign space to all devices.

Previously we put all prefetchable resources in the prefetchable bridge
window.  If any of those resources was 32-bit only, we restricted the
window to be below 4GB.

After this patch, we only put 64-bit prefetchable resources in a 64-bit
prefetchable window.  We put all 32-bit prefetchable resources in the
non-prefetchable window, even if there are no 64-bit prefetchable
resources.

With the previous approach, if there was a 32-bit prefetchable resource
behind a bridge, we forced the bridge's prefetchable window below 4GB,
which meant that even if there was plenty of space above 4GB available, we
couldn't use it, and assignment of large 64-bit resources could fail, as
in the bugzilla below.

The new strategy is:

  1) If the prefetchable window is 64 bits wide, we put only 64-bit
     prefetchable resources in it.  Any 32-bit prefetchable resources go in
     the non-prefetchable window.

  2) If the prefetchable window is 32 bits wide, we put both 32- and 64-bit
     prefetchable resources in it.

  3) If there is no prefetchable window, all MMIO resources go in the
     non-prefetchable window.

This reduces performance for 32-bit prefetchable resources below a bridge
with a 64-bit prefetchable window.  We previously assigned prefetchable
space, but now we'll assign non-prefetchable space.  This is the case even
if there are no 64-bit prefetchable resources, or if they would all fit
below 4GB.  In those cases, the old strategy would work and would have
better performance.

[bhelgaas: write changelog, add bugzilla link, fold in mem64_mask removal]
Link: https://bugzilla.kernel.org/show_bug.cgi?id=74151
Tested-by: Guo Chao <yan@linux.vnet.ibm.com>
Tested-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-05-23 12:40:48 -06:00
Alan
14c8530dbc PCI: Support BAR sizes up to 8GB
This is needed for some of the Xeon Phi type systems.

[bhelgaas: added Nikhil, use ARRAY_SIZE() to connect with decl, folded in
Kevin's "order < 0" fix to ARRAY_SIZE() usage]
Signed-off-by: Nikhil P Rao <nikhil.rao@intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-05-23 10:47:21 -06:00
Bjorn Helgaas
10874f5a00 PCI: Remove unnecessary __ref annotations
Some PCI functions used to be marked __devinit.  When CONFIG_HOTPLUG was
not set, these functions were discarded after boot.  A few callers of these
__devinit functions were marked __ref to indicate that they could safely
call the __devinit functions even though the callers were not __devinit.

But CONFIG_HOTPLUG and __devinit are now gone, and the need for the __ref
annotations is also gone, so remove them.  Relevant historical commits:

  54b956b903 Remove __dev* markings from init.h
  a8e4b9c101 PCI: add generic pci_hp_add_bridge()
  0ab2b57f8d PCI: fix section mismatch warning in pci_scan_child_bus
  451124a7cc PCI: fix 4x section mismatch warnings

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-04-29 17:36:44 -06:00
Bjorn Helgaas
96702be560 Merge branch 'pci/resource' into next
* pci/resource:
  PCI: Allocate 64-bit BARs above 4G when possible
  PCI: Enforce bus address limits in resource allocation
  PCI: Split out bridge window override of minimum allocation address
  agp/ati: Use PCI_COMMAND instead of hard-coded 4
  agp/intel: Use CPU physical address, not bus address, for ioremap()
  agp/intel: Use pci_bus_address() to get GTTADR bus address
  agp/intel: Use pci_bus_address() to get MMADR bus address
  agp/intel: Support 64-bit GMADR
  agp/intel: Rename gtt_bus_addr to gtt_phys_addr
  drm/i915: Rename gtt_bus_addr to gtt_phys_addr
  agp: Use pci_resource_start() to get CPU physical address for BAR
  agp: Support 64-bit APBASE
  PCI: Add pci_bus_address() to get bus address of a BAR
  PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
  PCI: Change pci_bus_region addresses to dma_addr_t
2014-01-10 14:23:15 -07:00
Yinghai Lu
fc2798502f PCI: Convert pcibios_resource_to_bus() to take a pci_bus, not a pci_dev
These interfaces:

  pcibios_resource_to_bus(struct pci_dev *dev, *bus_region, *resource)
  pcibios_bus_to_resource(struct pci_dev *dev, *resource, *bus_region)

took a pci_dev, but they really depend only on the pci_bus.  And we want to
use them in resource allocation paths where we have the bus but not a
device, so this patch converts them to take the pci_bus instead of the
pci_dev:

  pcibios_resource_to_bus(struct pci_bus *bus, *bus_region, *resource)
  pcibios_bus_to_resource(struct pci_bus *bus, *resource, *bus_region)

In fact, with standard PCI-PCI bridges, they only depend on the host
bridge, because that's the only place address translation occurs, but
we aren't going that far yet.

[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-21 10:06:10 -07:00
Bjorn Helgaas
5b764b834e PCI: Stop clearing bridge Secondary Status when setting up I/O aperture
pci_setup_bridge_io() accessed PCI_IO_BASE and PCI_IO_LIMIT using dword
(32-bit) reads and writes, which also access the Secondary Status register.
Since the Secondary Status register is in the upper 16 bits of the dword,
and we preserved those upper 16 bits, this had the effect of clearing any
of the write-1-to-clear bits that happened to be set in the Secondary
Status register.

That's not what we want, so use word (16-bit) accesses to update only
PCI_IO_BASE and PCI_IO_LIMIT.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-13 08:44:30 -07:00
Bjorn Helgaas
d2f54d9b3e PCI: Prevent bus conflicts while checking for bridge apertures
pci_bridge_check_ranges() determines whether the bridge supports an I/O
aperture and a prefetchable memory aperture.

Previously, if the I/O aperture was unsupported, disabled, or configured at
[io 0x0000-0x0fff], we wrote 0xf0 to PCI_IO_BASE and PCI_IO_LIMIT, which,
if the bridge supports it, enables the I/O aperture at [io 0xf000-0xffff].
The enabled aperture may conflict with other devices in the system.

Similarly, we wrote 0xfff0 to PCI_PREF_MEMORY_BASE and
PCI_PREF_MEMORY_LIMIT, which enables the prefetchable memory aperture at
[mem 0xfff00000-0xffffffff], and that may also conflict with other devices.

All we need to know is whether the base and limit registers are writable,
so we can use values that leave the apertures disabled, e.g., PCI_IO_BASE =
0xf0, PCI_IO_LIMIT = 0xe0, PCI_PREF_MEMORY_BASE = 0xfff0,
PCI_PREF_MEMORY_LIMIT = 0xffe0.

Writing non-zero values to both the base and limit registers means we
detect whether either or both are writable, as we did before.

Reported-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Based-on-patch-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-12-13 08:44:30 -07:00
Bjorn Helgaas
f7625980f5 PCI: Fix whitespace, capitalization, and spelling errors
Fix whitespace, capitalization, and spelling errors.  No functional change.
I know "busses" is not an error, but "buses" was more common, so I used it
consistently.

Signed-off-by: Marta Rybczynska <rybczynska@gmail.com> (pci_reset_bridge_secondary_bus())
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-11-14 11:28:18 -07:00
Wei Yang
3ad94b0d79 PCI: Pass type, width, and prefetchability for window alignment
When calculating window_alignment(), type information like IORESOURCE_MEM
and IORESOURCE_PREFETCH may not be enough.  For example, on powernv, we
need to know whether the window is 64-bit or not.

This patch passes the full resource type (res->flags) for window alignment.

[bhelgaas: changelog]
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Gavin Shan <shangw@linux.vnet.ibm.com>
2013-09-25 15:44:58 -06:00
Wei Yang
2ba29e270e PCI: Use pci_is_root_bus() to check for root bus
In __pci_bus_size_bridges() we check whether a bus is a root bus by testing
bus->self.  As indicated by commit 79af72d7 ("PCI: pci_is_root_bus
helper"), bus->self == NULL is not a proper way to check for a root bus.
One issue is that "virtual" buses added for SR-IOV (via virtfn_add_bus())
have bus->self == NULL but are not root buses.

This patch changes it to pci_is_root_bus() to check whether it is a root
bus.

[bhelgaas: changelog]
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-09-25 15:43:48 -06:00
Linus Torvalds
a923874198 PCI changes for the v3.12 merge window:
PCI device hotplug
     - Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
     - Assign resources on per-host bridge basis (Yinghai Lu)
 
   MPS (Max Payload Size)
     - Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
     - Add warnings about unsafe MPS settings (Yijing Wang)
     - Simplify interface and messages (Bjorn Helgaas)
 
   SR-IOV
     - Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
     - Update NumVFs register when disabling SR-IOV (Yijing Wang)
 
   Virtualization
     - Add bus and slot reset support (Alex Williamson)
     - Fix ACS (Access Control Services) issues (Alex Williamson)
 
   Miscellaneous
     - Simplify PCIe Capability accessors (Bjorn Helgaas)
     - Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
     - Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
     - Delay enabling bridges until they're needed (Yinghai Lu)
     - Split Designware support into Synopsys and Exynos parts (Jingoo Han)
     - Convert class code to use dev_groups (Greg Kroah-Hartman)
     - Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
     - Fix bridge I/O window alignment (Bjorn Helgaas)
     - Add pci_wait_for_pending_transaction() (Casey Leedom)
     - Use devm_ioremap_resource() in Marvell driver (Tushar Behera)
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Merge tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI changes from Bjorn Helgaas:

  PCI device hotplug:
    - Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
    - Assign resources on per-host bridge basis (Yinghai Lu)

  MPS (Max Payload Size):
    - Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
    - Add warnings about unsafe MPS settings (Yijing Wang)
    - Simplify interface and messages (Bjorn Helgaas)

  SR-IOV:
    - Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
    - Update NumVFs register when disabling SR-IOV (Yijing Wang)

  Virtualization:
    - Add bus and slot reset support (Alex Williamson)
    - Fix ACS (Access Control Services) issues (Alex Williamson)

  Miscellaneous:
    - Simplify PCIe Capability accessors (Bjorn Helgaas)
    - Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
    - Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
    - Delay enabling bridges until they're needed (Yinghai Lu)
    - Split Designware support into Synopsys and Exynos parts (Jingoo Han)
    - Convert class code to use dev_groups (Greg Kroah-Hartman)
    - Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
    - Fix bridge I/O window alignment (Bjorn Helgaas)
    - Add pci_wait_for_pending_transaction() (Casey Leedom)
    - Use devm_ioremap_resource() in Marvell driver (Tushar Behera)

* tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (63 commits)
  PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available
  PCI: exynos: Add I/O access wrappers
  PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc()
  PCI: Remove pcie_cap_has_devctl()
  PCI: Support PCIe Capability Slot registers only for ports with slots
  PCI: Remove PCIe Capability version checks
  PCI: Allow PCIe Capability link-related register access for switches
  PCI: Add offsets of PCIe capability registers
  PCI: Tidy bitmasks and spacing of PCIe capability definitions
  PCI: Remove obsolete comment reference to pci_pcie_cap2()
  PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment
  PCI: Rename PCIe capability definitions to follow convention
  PCI: Warn if unsafe MPS settings detected
  PCI: Fix MPS peer-to-peer DMA comment syntax
  PCI: Disable decoding for BAR sizing only when it was actually enabled
  PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI=n
  PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality
  PCI: Don't restrict MPS for slots below Root Ports
  PCI: Simplify MPS test for Downstream Port
  PCI: Remove unnecessary check for pcie_get_mps() failure
  ...
2013-09-03 16:24:35 -07:00
Bjorn Helgaas
1193725f54 Merge branch 'pci/yinghai-assign-unassigned-v6' into next
* pci/yinghai-assign-unassigned-v6:
  PCI: Assign resources for hot-added host bridge more aggressively
  PCI: Move resource reallocation code to non-__init
  PCI: Delay enabling bridges until they're needed
  PCI: Assign resources on a per-bus basis
  PCI: Enable unassigned resource reallocation on per-bus basis
  PCI: Turn on reallocation for unassigned resources with host bridge offset
  PCI: Look for unassigned resources on per-bus basis
  PCI: Drop temporary variable in pci_assign_unassigned_resources()
2013-08-26 15:40:03 -06:00
Bjorn Helgaas
2d1d66780e PCI: Align bridge I/O windows as required by downstream devices & bridges
An upstream bridge's I/O window must be at least as aligned as any
downstream device or bridge requires.  In particular, if the upstream
bridge supports 1K alignment but a downstream bridge requires 4K alignment,
the upstream window must also be 4K aligned.

Therefore, do not reduce the required alignment ("min_align") based on
the upstream bridge's capabilities.

Reported-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Suggested-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-08-05 16:15:10 -06:00
Wei Yang
11251a869e PCI: Fix types in pbus_size_io()
This patch changes the type of "size" to resource_size_t and makes the
corresponding dev_printk() change.

[bhelgaas: changelog]
Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-08-02 16:15:32 -06:00
Wei Yang
496f70cf65 PCI: Add comments for pbus_size_mem() parameters
This patch fills in the missing description for two parameters of
pbus_size_mem().

Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-08-02 16:15:26 -06:00
Wei Yang
f2a230bd4e PCI: Enumerate subordinate buses, not devices, in pci_bus_get_depth()
Normally, on one PCI bus there would be more devices than bridges.  When
calculating the depth of a PCI bus, it would be more time efficient to
enumerating through the child buses instead of the child devices.

Also by doing so, the code seems more self explaining.  Previously, it went
through the devices and checked whether a bridge introduced a child bus or
not, which needs more background knowledge to understand it.

This patch calculates the depth by enumerating the bus hierarchy.

Signed-off-by: Wei Yang <weiyang@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-08-02 16:11:09 -06:00
Yinghai Lu
aa914f5ec2 PCI: Retry allocation of only the resource type that failed
Ben Herrenschmidt reported the following problem:

  - The bus has space for all desired MMIO resources, including optional
    space for SR-IOV devices
  - We attempt to allocate I/O port space, but it fails because the bus
    has no I/O space
  - Because of the I/O allocation failure, we retry MMIO allocation,
    requesting only the required space, without the optional SR-IOV space

This means we don't allocate the optional SR-IOV space, even though we
could.

This is related to 0c5be0cb0e ("PCI: Retry on IORESOURCE_IO type
allocations").

This patch changes how we handle allocation failures.  We will now retry
allocation of only the resource type that failed.  If MMIO allocation
fails, we'll retry only MMIO allocation.  If I/O port allocation fails,
we'll retry only I/O port allocation.

[bhelgaas: changelog]
Reference: https://lkml.kernel.org/r/1367712653.11982.19.camel@pasglop
Reported-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v3.10+
2013-07-26 07:32:20 -06:00
Yinghai Lu
39772038ea PCI: Assign resources for hot-added host bridge more aggressively
When hot-adding an ACPI host bridge, use
pci_assign_unassigned_root_bus_resources() instead of
pci_assign_unassigned_bus_resources().

The former is more aggressive and will release and reassign existing
resources if necessary.  This is safe at hot-add time because no drivers
are bound to devices below the new host bridge yet.

[bhelgaas: changelog, split __init changes out for reviewability]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-07-25 12:35:03 -06:00
Yinghai Lu
ff35147cf1 PCI: Move resource reallocation code to non-__init
Resource reallocation is currently done only at boot-time, but will
soon be done when host bridge is hot-added.  This patch removes the
__init annotations so the code will still be present after boot.

[bhelgaas: split __init changes out]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-07-25 12:35:03 -06:00
Yinghai Lu
928bea9648 PCI: Delay enabling bridges until they're needed
We currently enable PCI bridges after scanning a bus and assigning
resources.  This is often done in arch code.

This patch changes this so we don't enable a bridge until necessary, i.e.,
until we enable a PCI device behind the bridge.  We do this in the generic
pci_enable_device() path, so this also removes the arch-specific code to
enable bridges.

[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-07-25 12:35:03 -06:00
Yinghai Lu
55ed83a615 PCI: Assign resources on a per-bus basis
Previously, we did resource assignment globally.  This patch splits up
pci_assign_unassigned_resources() so assignment is done for each root bus
in turn.  We check each root bus individually to see whether it needs any
reassignment, and if it does, we assign resources for just that bus.

[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-07-25 12:35:03 -06:00
Yinghai Lu
967260cdb1 PCI: Enable unassigned resource reallocation on per-bus basis
pci_realloc_detect() turns on automatic resource allocation when it finds
unassigned SR-IOV resources.  Previously it did this on a global basis, so
we enabled reallocation if any PCI device anywhere had an unassigned SR-IOV
resource.

This patch changes pci_realloc_detect() so it looks at a single bus, so we
can do this when a host bridge is hot-added.

[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-07-25 12:35:03 -06:00
Yinghai Lu
fa216bf4db PCI: Turn on reallocation for unassigned resources with host bridge offset
Previously we did not turn on automatic PCI resource reallocation for
unassigned IOV resources behind a host bridge with address offset.  This
patch fixes that bug.

The intent was that "!r->start" would check for a BAR containing zero.  But
that check is incorrect for host bridges that apply an offset, because in
that case the resource address is not the same as the bus address.

This patch fixes that by converting the resource address back to a bus
address before checking for zero.

[bhelgaas: changelog]
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-07-25 12:35:02 -06:00
Yinghai Lu
223d96fc32 PCI: Look for unassigned resources on per-bus basis
When CONFIG_PCI_REALLOC_ENABLE_AUTO=y, pci_realloc_detect() looks at PCI
devices to see if any have SR-IOV resources that need to be assigned.  If
it finds any, it turns on automatic resource reallocation.

This patch changes pci_realloc_detect() so it uses pci_walk_bus() on
each root bus instead of using for_each_pci_dev().  This is a step
toward doing reallocation on a per-bus basis, so we can do it for
a hot-added host bridge.

[bhelgaas: changelog, rename callback to iov_resources_unassigned(), use
boolean for "unassigned"]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-07-25 12:35:02 -06:00
Yinghai Lu
61e83cdde1 PCI: Drop temporary variable in pci_assign_unassigned_resources()
Drop the "bus" temporary variable.  No functional change, but simplifies
later patch slightly.

[bhelgaas: changelog, make same change in
pci_assign_unassigned_bridge_resources() to keep it parallel with
pci_assign_unassigned_resources()]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-07-25 12:35:02 -06:00
Jiang Liu
d66ecb7220 PCI / ACPI: Use boot-time resource allocation rules during hotplug
On x86 platforms, the kernel respects PCI resource assignments from
the BIOS and only reassigns resources for unassigned BARs at boot
time.  However, with the ACPI-based hotplug (acpiphp), it ignores the
BIOS' PCI resource assignments completely and reassigns all resources
by itself.  This causes differences in PCI resource allocation
between boot time and runtime hotplug to occur, which is generally
undesirable and sometimes actively breaks things.

Namely, if there are enough resources, reassigning all PCI resources
during runtime hotplug should work, but it may fail if the resources
are constrained.  This may happen, for instance, when some PCI
devices with huge MMIO BARs are involved in the runtime hotplug
operations, because the current PCI MMIO alignment algorithm may
waste huge chunks of MMIO address space in those cases.

On the Alexander's Sony VAIO VPCZ23A4R the BIOS allocates limited
MMIO resources for the dock station which contains a device
(graphics adapter) with a 256MB MMIO BAR.  An attempt to reassign
that during runtime hotplug causes the dock station MMIO window to be
exhausted and acpiphp fails to allocate resources for the majority
of devices on the dock station as a result.

To prevent that from happening, modify acpiphp to follow the boot
time resources allocation behavior so that the BIOS' resource
assignments are respected during runtime hotplug too.

[rjw: Changelog]
References: https://bugzilla.kernel.org/show_bug.cgi?id=56531
Reported-and-tested-by: Alexander E. Patrakov <patrakov@gmail.com>
Tested-by: Illya Klymov <xanf@xanf.me>
Signed-off-by: Jiang Liu <jiang.liu@huawei.com>
Acked-by: Yinghai Lu <yinghai@kernel.org>
Cc: 3.9+ <stable@vger.kernel.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-06-23 01:01:35 +02:00
Bjorn Helgaas
9fc9eea09f PCI: Warn about failures instead of "must_check" functions
These places capture return values to avoid "must_check" warnings,
but we didn't *do* anything with the return values, which causes
"set but not used" warnings.  We might as well do something instead
of just trying to evade the "must_check" warnings.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-04-17 10:21:12 -06:00
Bjorn Helgaas
9738abedd6 PCI: Make local functions/structs static
This fixes "no previous prototype" warnings found via "make W=1".

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2013-04-12 11:26:01 -06:00
Yinghai Lu
a3cb999dcf PCI: Add root bus children dev's res to fail list
We can stop trying according to try_number now and do not need to use
root_bus checking as stop sign.

In extreme case we could need to reallocate resource for device just
under root bus.  For PCI root bus hot-add, we need to retry to assign
resources to PCI devices just under pci root bus.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
2013-01-25 13:45:00 -07:00
Yinghai Lu
e164f658f2 PCI: Move out pci_enable_bridges out of assign_unsigned_bus_res
So could use assign_unassigned_bus_res pci root bus add

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-11-03 16:20:30 -06:00
Yinghai Lu
a5213a3194 PCI: Move pci_rescan_bus() back to probe.c
We have pci_assign_unassigned_bus_resources() in as global function now.

Move pci_rescan_bus() back to probe.c where it should be.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-11-03 16:20:07 -06:00
Yinghai Lu
1778794031 PCI: Separate out pci_assign_unassigned_bus_resources()
It is main portion of pci_rescan_bus().

Separate it out and prepare to use it for PCI root bus hot add later.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-10-30 14:31:10 -06:00
Gavin Shan
c121504e89 PCI: Refactor pbus_size_mem()
The original idea comes from Ram Pai.  This patch puts the chunk of
code for calculating the minimal alignment of memory window into a
separate inline function.

Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-09-11 16:59:46 -06:00
Gavin Shan
462d930306 PCI: Align P2P windows using pcibios_window_alignment()
This patch changes pbus_size_io() and pbus_size_mem() to do window (I/O,
memory and prefetchable memory) reassignment based on the minimal
alignments for the P2P bridge, which was retrieved by window_alignment().

[bhelgaas: changelog]
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-09-11 16:59:46 -06:00
Gavin Shan
ac5ad93e92 PCI: Add weak pcibios_window_alignment() interface
This patch implements a weak function to return the default I/O or memory
window alignment for a P2P bridge.  By default, I/O windows are aligned to
4KiB or 1KiB and memory windows are aligned to 4MiB.  Some platforms, e.g.,
powernv, have special alignment requirements and can override
pcibios_window_alignment().

[bhelgaas: changelog]
Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-09-11 16:59:45 -06:00
Linus Torvalds
6dd53aa456 PCI changes for the 3.6 merge window:
Host bridge hotplug
     - Add MMCONFIG support for hot-added host bridges (Jiang Liu)
   Device hotplug
     - Move fixups from __init to __devinit (Sebastian Andrzej Siewior)
     - Call FINAL fixups for hot-added devices, too (Myron Stowe)
     - Factor out generic code for P2P bridge hot-add (Yinghai Lu)
     - Remove all functions in a slot, not just those with _EJx (Amos Kong)
   Dynamic resource management
     - Track bus number allocation (struct resource tree per domain) (Yinghai Lu)
     - Make P2P bridge 1K I/O windows work with resource reassignment (Bjorn Helgaas, Yinghai Lu)
     - Disable decoding while updating 64-bit BARs (Bjorn Helgaas)
   Power management
     - Add PCIe runtime D3cold support (Huang Ying)
   Virtualization
     - Add VFIO infrastructure (ACS, DMA source ID quirks) (Alex Williamson)
     - Add quirks for devices with broken INTx masking (Jan Kiszka)
   Miscellaneous
     - Fix some PCI Express capability version issues (Myron Stowe)
     - Factor out some arch code with a weak, generic, pcibios_setup() (Myron Stowe)
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Merge tag 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI changes from Bjorn Helgaas:
 "Host bridge hotplug:
    - Add MMCONFIG support for hot-added host bridges (Jiang Liu)
  Device hotplug:
    - Move fixups from __init to __devinit (Sebastian Andrzej Siewior)
    - Call FINAL fixups for hot-added devices, too (Myron Stowe)
    - Factor out generic code for P2P bridge hot-add (Yinghai Lu)
    - Remove all functions in a slot, not just those with _EJx (Amos
      Kong)
  Dynamic resource management:
    - Track bus number allocation (struct resource tree per domain)
      (Yinghai Lu)
    - Make P2P bridge 1K I/O windows work with resource reassignment
      (Bjorn Helgaas, Yinghai Lu)
    - Disable decoding while updating 64-bit BARs (Bjorn Helgaas)
  Power management:
    - Add PCIe runtime D3cold support (Huang Ying)
  Virtualization:
    - Add VFIO infrastructure (ACS, DMA source ID quirks) (Alex
      Williamson)
    - Add quirks for devices with broken INTx masking (Jan Kiszka)
  Miscellaneous:
    - Fix some PCI Express capability version issues (Myron Stowe)
    - Factor out some arch code with a weak, generic, pcibios_setup()
      (Myron Stowe)"

* tag 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (122 commits)
  PCI: hotplug: ensure a consistent return value in error case
  PCI: fix undefined reference to 'pci_fixup_final_inited'
  PCI: build resource code for M68K architecture
  PCI: pciehp: remove unused pciehp_get_max_lnk_width(), pciehp_get_cur_lnk_width()
  PCI: reorder __pci_assign_resource() (no change)
  PCI: fix truncation of resource size to 32 bits
  PCI: acpiphp: merge acpiphp_debug and debug
  PCI: acpiphp: remove unused res_lock
  sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases()
  PCI: call final fixups hot-added devices
  PCI: move final fixups from __init to __devinit
  x86/PCI: move final fixups from __init to __devinit
  MIPS/PCI: move final fixups from __init to __devinit
  PCI: support sizing P2P bridge I/O windows with 1K granularity
  PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)
  PCI: disable MEM decoding while updating 64-bit MEM BARs
  PCI: leave MEM and IO decoding disabled during 64-bit BAR sizing, too
  PCI: never discard enable/suspend/resume_early/resume fixups
  PCI: release temporary reference in __nv_msi_ht_cap_quirk()
  PCI: restructure 'pci_do_fixups()'
  ...
2012-07-24 16:17:07 -07:00
Masanari Iida
367fa9821a pci: hotplug: Fix typo in pci
Correct spelling typo in drivers/pci/hotplug.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2012-07-24 12:59:30 +02:00
Bjorn Helgaas
6ee53f4c38 Merge branch 'pci/bjorn-p2p-bridge-windows' into next
* pci/bjorn-p2p-bridge-windows:
  sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases()
  PCI: support sizing P2P bridge I/O windows with 1K granularity
  PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)
  PCI: allow P2P bridge windows starting at PCI bus address zero

Conflicts:
	drivers/pci/probe.c
	include/linux/pci.h
2012-07-10 08:36:09 -06:00
Yinghai Lu
fd59134110 PCI: support sizing P2P bridge I/O windows with 1K granularity
Some bridges support I/O windows with 1K alignment, not just the 4K
alignment defined by the PCI spec.  For example, see the IOBL_ADR register
and the EN1K bit in the CNF register in the Intel 82870P2 (P64H2).

This patch adds support for sizing the window in 1K increments based
on the requirements of downstream devices.

[bhelgaas: changelog, comment]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-09 19:55:29 -06:00
Bjorn Helgaas
2b28ae1912 PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)
9d265124d0 and 15a260d53f added quirks for P2P bridges that support
I/O windows that start/end at 1K boundaries, not just the 4K boundaries
defined by the PCI spec.  For details, see the IOBL_ADR register and the
EN1K bit in the CNF register in the Intel 82870P2 (P64H2).

These quirks complicate the code that reads P2P bridge windows
(pci_read_bridge_io() and pci_cfg_fake_ranges()) because the bridge
I/O resource is updated in the HEADER quirk, in pci_read_bridge_io(),
in pci_setup_bridge(), and again in the FINAL quirk.  This is confusing
and makes it impossible to reassign the bridge windows after FINAL
quirks are run.

This patch adds support for 1K windows in the generic paths, so the
HEADER quirk only has to enable this support.  The FINAL quirk, which
used to undo damage done by pci_setup_bridge(), is no longer needed.

This removes "if (!res->start) res->start = ..." from pci_read_bridge_io();
that was part of 9d265124d0 to avoid overwriting the resource filled in
by the quirk.  Since pci_read_bridge_io() itself now knows about
granularity, the quirk no longer updates the resource and this test is no
longer needed.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-07-09 19:52:04 -06:00
Bjorn Helgaas
0f6662a49b Merge branch 'topic/bjorn-trivial' into next
* topic/bjorn-trivial:
  PCI: remove useless pcix_set_mmrbc() dev->bus check
  PCI: acpiphp: check whether _ADR evaluation succeeded
  PCI: shpchp: remove dead code
  PCI: fix P2P bridge I/O port window sign extension
  PCI: fix upstream P2P bridge checks when enabling OBFF and LTR
  PCI: use __weak consistently
  PCI: cleanup assign_requested_resources_sorted() kernel-doc warning
  sparc/PCI: remove unused pcibios_assign_resource() definition
2012-06-22 15:32:50 -06:00
Wanpeng Li
8356aad430 PCI: cleanup assign_requested_resources_sorted() kernel-doc warning
Warning(drivers/pci/setup-bus.c:277): No description found for parameter 'fail_head'
Warning(drivers/pci/setup-bus.c:277): Excess function parameter 'failed_list' description in 'assign_requested_resources_sorted'

Signed-off-by: Wanpeng Li <liwp.linux@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-20 10:44:35 -06:00
Yinghai Lu
b918c62e08 PCI: replace struct pci_bus secondary/subordinate with busn_res
Replace the struct pci_bus secondary/subordinate members with the
struct resource busn_res.  Later we'll build a resource tree of these
bus numbers.

[bhelgaas: changelog]
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-06-13 15:42:22 -06:00
Jesse Barnes
ecd58d667a Merge branch 'pci-next+probe_only+bus2res-fb127cb' of git://github.com/bjorn-helgaas/linux into linux-next 2012-02-24 14:25:33 -08:00
Yinghai Lu
b07f2ebc10 PCI: add a PCI resource reallocation config option
Add a new config option, PCI_REALLOC_ENABLE_AUTO, which will
automatically try to re-allocate PCI resources if PCI_IOV support is
enabled and the SR-IOV resources are unassigned.  Behavior can still be
controlled using the pci=realloc= parameter.

-v2: According to Jesse, adding one CONFIG option for distribution to
     disable it or enable it.
-v3: update Kconfig text (jbarnes)

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-24 09:38:59 -08:00
Yinghai Lu
eb572e7c76 PCI: print out suggestion about using pci=realloc
let user know they could try if pci=realloc could help.

-v2: update suggestion text.

Suggested-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-24 08:47:53 -08:00
Yinghai Lu
b55438fdd5 PCI: prepare pci=realloc for multiple options
Let the user could enable and disable with pci=realloc=on or pci=realloc=off

Also
1. move variable and functions near the place they are used.
2. change macro to function
3. change related functions and variable to static and _init
4. update parameter description accordingly.

This will let us add a config option to control default behavior, and
still allow the user to turn off automatic reallocation if it fails on
their platform until a permanent solution is found.

-v2: still honor pci=realloc, and treat it as pci=realloc=on
     also use enum instead of ...
-v3: update kernel-paramenters.txt according to Jesse.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-24 08:47:42 -08:00
Yinghai Lu
0c5be0cb0e PCI: Retry on IORESOURCE_IO type allocations
When enabling pci reallocation for a pci bridge, we clear the small size
in in bridge and re-assign with requested + optional size for first
several tries, but Ram mention could have problem with one case:
	https://bugzilla.kernel.org/show_bug.cgi?id=15960

After checking the booting log in
	https://lkml.org/lkml/2010/4/19/44
	[regression, bisected] Xonar DX invalid PCI I/O range since 977d17bb17

We should not stop too early for io ports.
	Apr 19 10:19:38 [kernel] pci 0000:04:00.0: BAR 7: can't assign io (size 0x4000)
	Apr 19 10:19:38 [kernel] pci 0000:05:01.0: BAR 8: assigned [mem 0x80400000-0x805fffff]
	Apr 19 10:19:38 [kernel] pci 0000:05:01.0: BAR 7: can't assign io (size 0x2000)
	Apr 19 10:19:38 [kernel] pci 0000:05:02.0: BAR 7: can't assign io (size 0x1000)
	Apr 19 10:19:38 [kernel] pci 0000:05:03.0: BAR 7: can't assign io (size 0x1000)
	Apr 19 10:19:38 [kernel] pci 0000:08:00.0: BAR 7: can't assign io (size 0x1000)
	Apr 19 10:19:38 [kernel] pci 0000:09:04.0: BAR 0: can't assign io (size 0x100)
and clear 00:1c.0 to retry again.

This patch removes IORESOUCE_IO checking, and tries one more time.  It
gives us a chance to get an allocation for the 00:1c.0 io port range
because the range from 0x4000 to 0x8000 will be freed and we can use it.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-24 08:44:38 -08:00
Bjorn Helgaas
844393f4c5 PCI: make pci_flags non-weak
No architecture defines its own pci_flags, so the core symbol does not
need to be weak.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-02-23 20:18:59 -07:00
Bjorn Helgaas
47087700ce PCI: make pci_flags always available
If we move resource assignment functions into the core, we'll still
need a way for architectures to prevent reassignment, e.g., the
"pci_probe_only" functionality, and we'll need a generic, always
available way the core can test for that.  The "pci_flags"
arrangement used by several architectures seems like a convenient
way to do this.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2012-02-23 20:18:55 -07:00
Yinghai Lu
3796f1e2ca PCI: Skip cardbus assigned resource reset during pci bus rescan
Otherwise when rescan is used for cardbus, assigned resources will get
cleared.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Tested-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-23 12:00:04 -08:00
Yinghai Lu
1184893439 PCI: Fix "cardbus bridge resources as optional" size handling
We should not set the requested size to -2; that will confuse the
resource list sorting with align when SIZEALIGN is used.

Change to STARTALIGN and pass align from start;  we are safe to do that
just as we do that regular pci bridge.  In the long run, we should just
treat cardbus like a regular pci bridge.

Also fix the case when realloc_head is not passed: we should keep the
requested size.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Tested-by: Dominik Brodowski <linux@dominikbrodowski.net>
Acked-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-23 11:59:56 -08:00
Yinghai Lu
dcef0d06b3 PCI: Disable cardbus bridge MEM1 prefetchable bit
Some BIOSes enable prefetch on both MEM0 and MEM1.  But the cardbus code
assumes MEM1 is non-pref...

Discussion could be found at:
	https://lkml.org/lkml/2012/1/12/1
	https://bugzilla.kernel.org/show_bug.cgi?id=41622#c23

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Tested-by: Dominik Brodowski <linux@dominikbrodowski.net>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-23 11:59:45 -08:00
Yinghai Lu
67cc7e26a5 PCI: remove add_to_failed_list()
Only one user; just use add_to_list instead.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:58 -08:00
Yinghai Lu
b592443d90 PCI: add debug print out for add_size
For use in debugging resource reallocation.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:58 -08:00
Yinghai Lu
bffc56d411 PCI: make free_list() into a function
After merging struct pci_dev_resource_x and pci_dev_resource,
We can use a function instead of macro now.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:57 -08:00
Yinghai Lu
b9b0bba96c PCI: Rename dev_res_x to add_res or fail_res
Linus says don't use dev_res_x because it doesn't communicate anything
about usage.  Rename them to add_res or fail_res etc according to
context.

Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:57 -08:00
Yinghai Lu
764242a0ae PCI: Merge pci_dev_resource_x and pci_dev_resource
pci_dev_resource_x is a superset of pci_dev_resource and they're just
temp structs used during resource reallocation.

pci_dev_resource usage is quite limted.

So just use pci_dev_resource_x, and rename it as new pci_dev_resource.

-v2: According to Linus, Separate free_list change to another patch

Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:56 -08:00
Yinghai Lu
bdc4abecae PCI: Replace resource_list with generic list
So we can use helper functions for generic list.  This makes the
resource re-allocation code much more readable.

-v2: Use list_add_tail instead of adding list_insert_before, Pointed out
     by Linus.

Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:55 -08:00
Yinghai Lu
2934a0de09 PCI: Move struct resource_list to setup-bus.c
No user outside of setup-bus.c now.  Later patches will convert
resource_list to a regular list.

Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:55 -08:00
Yinghai Lu
78c3b329b9 PCI: Move pdev_sort_resources() to setup-bus.c
This allows us to move the definition of struct resource_list to
setup_bus.c and later convert resource_list to a regular list.

Suggested-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:54 -08:00
Yinghai Lu
19aa7ee432 PCI: make re-allocation try harder by reassigning ranges higher in the heirarchy
On a system with devices that support SRIOV connected to a pcie switch
to pcie root port:

 +-[0000:80]-+-00.0-[81-8f]--
 |           +-01.0-[90-9f]--
 |           +-02.0-[a0-af]----00.0-[a1-a3]--+-02.0-[a2]--+-00.0 Oracle Corporation Device 207a
 |           |                               \-03.0-[a3]--+-00.0 Oracle Corporation Device 207a
 |           +-02.2-[b0-bf]----00.0-[b1-b3]--+-02.0-[b2]--+-00.0 Oracle Corporation Device 207a
 |           |                               \-03.0-[b3]--+-00.0 Oracle Corporation Device 207a

When the BIOS does not assign resources for SRIOV BARs, kernel pci
reallocation only goes up one bridge and then gives up, failing to to
get resources for all sSRIOV BARs, even though the range is large enough
in the peer root bus.

Specifically, only the bridge at the a1:02.0 level has its resources
cleared and reallocated.  The kernel does not go up to clear the bridge
at the 80:02.0 level.

To make it go to upper levels, during retry, we need to treat "good to have"
resources as "must have".

Only on the last try will we treat good to have resources as optional.
At that time, parent bridge resources will already have been released so
we'll have a chance to get everything assigned with must_have plus
good_to_have for all child devices.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:54 -08:00
Yinghai Lu
9b03088f95 PCI: Make pci_rescan_bus handle add_list
This allows us to allocate resources to hotplug bridges during
remove/rescan.

We need to move the function to setup-bus.c so it can use
__pci_bus_size_bridges and __pci_bus_assign_resources directly to take
the add_list resource tracking list.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:53 -08:00
Yinghai Lu
8424d7592e PCI: Use add_list in pcie hotplug path.
We need add size for hot plug path when pluging in hotplug chassis
without cards.

-v2: change descriptions. make it applicable after "pci: Check bridge
     resources after resource allocation."

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:52 -08:00
Yinghai Lu
3e6e0d8094 PCI: try to assign required+option size first
We found reassignment can not find a range for one resource, even if the
total available range is large enough.

bridge b1:02.0 will need 2M+3M
bridge b1:03.0 will need 2M+3M

so bridge b0:00.0 will get assigned: 4M : [f8000000-f83fffff]
   later is reassigned to 10M : [f8000000-f9ffffff]

b1:02.0 is assigned to 2M : [f8000000-f81fffff]
b1:03.0 is assigned to 2M : [f8200000-f83fffff]

After that b1:03.0 get chance to be reassigned to [f8200000-f86fffff],
but b1:02.0 will not have chance to expand, because b1:03.0 is using in
middle one.

[  187.911401] pci 0000:b1:02.0: bridge window [mem 0x00100000-0x002fffff] to [bus b2-b2] add_size 300000
[  187.920764] pci 0000:b1:03.0: bridge window [mem 0x00100000-0x002fffff] to [bus b3-b3] add_size 300000
[  187.930129] pci 0000:b1:02.0: [mem 0x00100000-0x002fffff] get_res_add_size  add_size 300000
[  187.938500] pci 0000:b1:03.0: [mem 0x00100000-0x002fffff] get_res_add_size  add_size 300000
[  187.946857] pci 0000:b0:00.0: bridge window [mem 0x00100000-0x004fffff] to [bus b1-b3] add_size 600000
[  187.956206] pci 0000:b0:00.0: BAR 14: assigned [mem 0xf8000000-0xf83fffff]
[  187.963102] pci 0000:b0:00.0: BAR 15: assigned [mem 0xf5000000-0xf51fffff pref]
[  187.970434] pci 0000:b0:00.0: BAR 14: reassigned [mem 0xf8000000-0xf89fffff]
[  187.977497] pci 0000:b1:02.0: BAR 14: assigned [mem 0xf8000000-0xf81fffff]
[  187.984383] pci 0000:b1:02.0: BAR 15: assigned [mem 0xf5000000-0xf50fffff pref]
[  187.991695] pci 0000:b1:03.0: BAR 14: assigned [mem 0xf8200000-0xf83fffff]
[  187.998576] pci 0000:b1:03.0: BAR 15: assigned [mem 0xf5100000-0xf51fffff pref]
[  188.005888] pci 0000:b1:03.0: BAR 14: reassigned [mem 0xf8200000-0xf86fffff]
[  188.012939] pci 0000:b1:02.0: BAR 14: can't assign mem (size 0x200000)
[  188.019471] pci 0000:b1:02.0: failed to add 300000 to res=[mem 0xf8000000-0xf81fffff]
[  188.027326] pci 0000:b2:00.0: reg 184: [mem 0x00000000-0x00003fff 64bit]
[  188.034071] pci 0000:b2:00.0: reg 18c: [mem 0x00000000-0x000fffff 64bit]
[  188.040795] pci 0000:b2:00.0: BAR 2: assigned [mem 0xf8000000-0xf80fffff 64bit]
[  188.048119] pci 0000:b2:00.0: BAR 2: set to [mem 0xf8000000-0xf80fffff 64bit] (PCI address [0xf8000000-0xf80fffff])
[  188.058550] pci 0000:b2:00.0: BAR 6: assigned [mem 0xf5000000-0xf50fffff pref]
[  188.065802] pci 0000:b2:00.0: BAR 0: assigned [mem 0xf8100000-0xf8103fff 64bit]
[  188.073125] pci 0000:b2:00.0: BAR 0: set to [mem 0xf8100000-0xf8103fff 64bit] (PCI address [0xf8100000-0xf8103fff])
[  188.083596] pci 0000:b2:00.0: reg 18c: [mem 0x00000000-0x000fffff 64bit]
[  188.090310] pci 0000:b2:00.0: BAR 9: can't assign mem (size 0x300000)
[  188.096773] pci 0000:b2:00.0: reg 184: [mem 0x00000000-0x00003fff 64bit]
[  188.103479] pci 0000:b2:00.0: BAR 7: assigned [mem 0xf8104000-0xf810ffff 64bit]
[  188.110801] pci 0000:b2:00.0: BAR 7: set to [mem 0xf8104000-0xf810ffff 64bit] (PCI address [0xf8104000-0xf810ffff])
[  188.121256] pci 0000:b1:02.0: PCI bridge to [bus b2-b2]
[  188.126512] pci 0000:b1:02.0:   bridge window [mem 0xf8000000-0xf81fffff]
[  188.133328] pci 0000:b1:02.0:   bridge window [mem 0xf5000000-0xf50fffff pref]
[  188.140608] pci 0000:b3:00.0: reg 184: [mem 0x00000000-0x00003fff 64bit]
[  188.147341] pci 0000:b3:00.0: reg 18c: [mem 0x00000000-0x000fffff 64bit]
[  188.154076] pci 0000:b3:00.0: BAR 2: assigned [mem 0xf8200000-0xf82fffff 64bit]
[  188.161417] pci 0000:b3:00.0: BAR 2: set to [mem 0xf8200000-0xf82fffff 64bit] (PCI address [0xf8200000-0xf82fffff])
[  188.171865] pci 0000:b3:00.0: BAR 6: assigned [mem 0xf5100000-0xf51fffff pref]
[  188.179090] pci 0000:b3:00.0: BAR 0: assigned [mem 0xf8300000-0xf8303fff 64bit]
[  188.186431] pci 0000:b3:00.0: BAR 0: set to [mem 0xf8300000-0xf8303fff 64bit] (PCI address [0xf8300000-0xf8303fff])
[  188.196884] pci 0000:b3:00.0: reg 18c: [mem 0x00000000-0x000fffff 64bit]
[  188.203591] pci 0000:b3:00.0: BAR 9: assigned [mem 0xf8400000-0xf86fffff 64bit]
[  188.210909] pci 0000:b3:00.0: BAR 9: set to [mem 0xf8400000-0xf86fffff 64bit] (PCI address [0xf8400000-0xf86fffff])
[  188.221379] pci 0000:b3:00.0: reg 184: [mem 0x00000000-0x00003fff 64bit]
[  188.228089] pci 0000:b3:00.0: BAR 7: assigned [mem 0xf8304000-0xf830ffff 64bit]
[  188.235407] pci 0000:b3:00.0: BAR 7: set to [mem 0xf8304000-0xf830ffff 64bit] (PCI address [0xf8304000-0xf830ffff])
[  188.245843] pci 0000:b1:03.0: PCI bridge to [bus b3-b3]
[  188.251107] pci 0000:b1:03.0:   bridge window [mem 0xf8200000-0xf86fffff]
[  188.257922] pci 0000:b1:03.0:   bridge window [mem 0xf5100000-0xf51fffff pref]
[  188.265180] pci 0000:b0:00.0: PCI bridge to [bus b1-b3]
[  188.270443] pci 0000:b0:00.0:   bridge window [mem 0xf8000000-0xf89fffff]
[  188.277250] pci 0000:b0:00.0:   bridge window [mem 0xf5000000-0xf51fffff pref]
[  188.284512] pcieport 0000:80:02.2: PCI bridge to [bus b0-bf]
[  188.290184] pcieport 0000:80:02.2:   bridge window [io  0xa000-0xbfff]
[  188.296735] pcieport 0000:80:02.2:   bridge window [mem 0xf8000000-0xf8ffffff]
[  188.303963] pcieport 0000:80:02.2:   bridge window [mem 0xf5000000-0xf5ffffff 64bit pref]

Thus b2:00.0 BAR 9 does not get assigned...

root cause:
b1:02.0 can not be added more range, because b1:03.0 is just after it;
no space between the required ranges.

Solution:
Try to assign required + optional all together at first, and if that
fails, try again with just the required resources.

-v2: seperate add_to_list change() to another patch according to Jesse.
     seperate get_res_add_size() moving to another patch according to Jesse.
     add !realloc_head->next check if the list is empty to bail early
     according to Jesse.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:52 -08:00
Yinghai Lu
1c372353e9 PCI: Move get_res_add_size() function
Need to call it from __assign_resources_sorted() later and we'd like to
avoid a forward declaraion.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:51 -08:00
Yinghai Lu
ef62dfefa9 PCI: Make add_to_list() return status
Will be used for resource_list_x duplication when trying
requested+optional at first.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:51 -08:00
Yinghai Lu
a4ac9fea01 PCI : Calculate right add_size
During debug of one SRIOV enabled hotplug device, we found found that
add_size is not passed properly.

The device has devices under two level bridges:

 +-[0000:80]-+-00.0-[81-8f]--
 |           +-01.0-[90-9f]--
 |           +-02.0-[a0-af]----00.0-[a1-a3]--+-02.0-[a2]--+-00.0  Oracle Corporation Device
 |           |                               \-03.0-[a3]--+-00.0  Oracle Corporation Device

Which means later the parent bridge will not try to add a big enough range:

[  557.455077] pci 0000:a0:00.0: BAR 14: assigned [mem 0xf9000000-0xf93fffff]
[  557.461974] pci 0000:a0:00.0: BAR 15: assigned [mem 0xf6000000-0xf61fffff pref]
[  557.469340] pci 0000:a1:02.0: BAR 14: assigned [mem 0xf9000000-0xf91fffff]
[  557.476231] pci 0000:a1:02.0: BAR 15: assigned [mem 0xf6000000-0xf60fffff pref]
[  557.483582] pci 0000:a1:03.0: BAR 14: assigned [mem 0xf9200000-0xf93fffff]
[  557.490468] pci 0000:a1:03.0: BAR 15: assigned [mem 0xf6100000-0xf61fffff pref]
[  557.497833] pci 0000:a1:03.0: BAR 14: can't assign mem (size 0x200000)
[  557.504378] pci 0000:a1:03.0: failed to add optional resources res=[mem 0xf9200000-0xf93fffff]
[  557.513026] pci 0000:a1:02.0: BAR 14: can't assign mem (size 0x200000)
[  557.519578] pci 0000:a1:02.0: failed to add optional resources res=[mem 0xf9000000-0xf91fffff]

It turns out we did not calculate size1 properly.

static resource_size_t calculate_memsize(resource_size_t size,
                resource_size_t min_size,
                resource_size_t size1,
                resource_size_t old_size,
                resource_size_t align)
{
        if (size < min_size)
                size = min_size;
        if (old_size == 1 )
                old_size = 0;
        if (size < old_size)
                size = old_size;
        size = ALIGN(size + size1, align);
        return size;
}

We should not pass add_size with min_size in calculate_memsize since
that will make add_size not contribute final add_size.

So just pass add_size with size1 to calculate_memsize().

With this change, we should have chance to remove extra addon in
pci_reassign_resource.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2012-02-14 08:44:50 -08:00
Benjamin Herrenschmidt
e24442733e PCI: Make pci_setup_bridge() non-static for use by arch code
The "powernv" platform of the powerpc architecture needs to assign PCI
resources using a specific algorithm to fit some HW constraints of
the IBM "IODA" architecture (related to the ability to create error
handling domains that encompass specific segments of MMIO space).

For doing so, it wants to call pci_setup_bridge() from architecture
specific resource management in order to configure bridges after all
resources have been assigned. So make it non-static.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-10-14 09:05:29 -07:00
Ram Pai
9e8bf93a7f PCI: code and comments cleanup
a) adjust_resource_sorted() is now called reassign_resource_sorted()
b) nice-to-have is now called optional
c) add_list is now called realloc_list.

Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-08-01 11:50:50 -07:00
Ram Pai
0a2daa1cf3 PCI: make cardbus-bridge resources optional
Allocate resources to cardbus bridge only after all other genuine
resources requests are satisfied. Dont retry if resource allocation
for cardbus-bridges fail.

Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-08-01 11:50:40 -07:00
Yinghai Lu
2aceefcbd5 PCI: make SRIOV resources optional
From: Yinghai Lu <yinghai@kernel.org>

Allocate resources to SRIOV BARs only after all other required
resource-requests are satisfied. Dont retry if resource allocation for SRIOV
BARs fail.

Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-08-01 11:50:31 -07:00
Ram Pai
2bbc694227 PCI : ability to relocate assigned pci-resources
Currently pci-bridges are allocated enough resources to satisfy their immediate
requirements.  Any additional resource-requests fail if additional free space,
contiguous to the one already allocated, is not available. This behavior is not
reasonable since sufficient contiguous resources, that can satisfy the request,
are available at a different location.

This patch provides the ability to expand and relocate a allocated resource.

	v2: Changelog: Fixed size calculation in pci_reassign_resource()
	v3: Changelog : Split this patch. The resource.c changes are already
			upstream. All the pci driver changes are in here.

Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-08-01 11:50:15 -07:00
Yinghai Lu
be768912a4 PCI: honor child buses add_size in hot plug configuration
git commit c8adf9a3e8
    "PCI: pre-allocate additional resources to devices only after
	successful allocation of essential resources."

fails to take into consideration the optional-resources needed by children
devices while calculating the optional-resource needed by the bridge.

This can be a problem on some setup. For example, if a hotplug bridge has 8
children hotplug bridges, the bridge should have enough resources to accomodate
the hotplug requirements for each of its children hotplug bridges.  Currently
this is not the case.

This patch fixes the problem.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Reviewed-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-08-01 11:49:39 -07:00
Bjorn Helgaas
7b87c9df56 PCI: remove printks about disabled bridge windows
I don't think there's enough value in the fact of a bridge window
being disabled to justify cluttering the dmesg log with it.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-22 09:08:07 -07:00
Ram Pai
f483d3923d PCI: conditional resource-reallocation through kernel parameter pci=realloc
Multiple attempts to dynamically reallocate pci resources have
unfortunately lead to regressions. Though we continue to fix the
regressions and fine tune the dynamic-reallocation behavior, we have not
reached a acceptable state yet.
    
This patch provides a interim solution. It disables dynamic reallocation
by default, but adds the ability to enable it through pci=realloc kernel
command line parameter.
    
Tested-by: Oliver Hartkopp <socketcan@hartkopp.net>
Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-08 15:49:20 -07:00
Linus Torvalds
5e152b4c9e Merge branch 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (27 commits)
  PCI: Don't use dmi_name_in_vendors in quirk
  PCI: remove unused AER functions
  PCI/sysfs: move bus cpuaffinity to class dev_attrs
  PCI: add rescan to /sys/.../pci_bus/.../
  PCI: update bridge resources to get more big ranges when allocating space (again)
  KVM: Use pci_store/load_saved_state() around VM device usage
  PCI: Add interfaces to store and load the device saved state
  PCI: Track the size of each saved capability data area
  PCI/e1000e: Add and use pci_disable_link_state_locked()
  x86/PCI: derive pcibios_last_bus from ACPI MCFG
  PCI: add latency tolerance reporting enable/disable support
  PCI: add OBFF enable/disable support
  PCI: add ID-based ordering enable/disable support
  PCI hotplug: acpiphp: assume device is in state D0 after powering on a slot.
  PCI: Set PCIE maxpayload for card during hotplug insertion
  PCI/ACPI: Report _OSC control mask returned on failure to get control
  x86/PCI: irq and pci_ids patch for Intel Panther Point DeviceIDs
  PCI: handle positive error codes
  PCI: check pci_vpd_pci22_wait() return
  PCI: Use ICH6_GPIO_EN in ich6_lpc_acpi_gpio
  ...

Fix up trivial conflicts in include/linux/pci_ids.h: commit a6e5e2be44
moved the intel SMBUS ID definitons to the i2c-i801.c driver.
2011-05-23 15:39:34 -07:00
Yinghai Lu
da7822e5ad PCI: update bridge resources to get more big ranges when allocating space (again)
With Ram's fixes, this should be safe to do again.  So let's give it
another try.

BIOS separates IO ranges between several IOHs, and on some slots, BIOS
assigns resources to a bridge, but stops assigning resources to the
device under that bridge, because the device needs a big resource.

So:
1. allocate resources and record the failed device resources
2. clear the BIOS assigned resources of the parent bridge of failing device
3. go back and call pci assign unassigned
4. if it still fails, go up the tree, clear more bridges. and try again

Now Ram's allocate requested resource already got into mainline. could
put this one again.

Reviewed-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-05-21 12:17:11 -07:00
Yinghai Lu
93d2175d3d PCI: Clear bridge resource flags if requested size is 0
During pci remove/rescan testing found:

  pci 0000:c0:03.0: PCI bridge to [bus c4-c9]
  pci 0000:c0:03.0:   bridge window [io  0x1000-0x0fff]
  pci 0000:c0:03.0:   bridge window [mem 0xf0000000-0xf00fffff]
  pci 0000:c0:03.0:   bridge window [mem 0xfc180000000-0xfc197ffffff 64bit pref]
  pci 0000:c0:03.0: device not available (can't reserve [io  0x1000-0x0fff])
  pci 0000:c0:03.0: Error enabling bridge (-22), continuing
  pci 0000:c0:03.0: enabling bus mastering
  pci 0000:c0:03.0: setting latency timer to 64
  pcieport 0000:c0:03.0: device not available (can't reserve [io  0x1000-0x0fff])
  pcieport: probe of 0000:c0:03.0 failed with error -22

This bug was caused by commit c8adf9a3e8 ("PCI: pre-allocate
additional resources to devices only after successful allocation of
essential resources.")

After that commit, pci_hotplug_io_size is changed to additional_io_size
from minium size.  So it will not go through resource_size(res) != 0
path, and will not be reset.

The root cause is: pci_bridge_check_ranges will set RESOURCE_IO flag for
pci bridge, and later if children do not need IO resource.  those bridge
resources will not need to be allocated.  but flags is still there.
that will confuse the the pci_enable_bridges later.

related code:

   static void assign_requested_resources_sorted(struct resource_list *head,
                                    struct resource_list_x *fail_head)
   {
           struct resource *res;
           struct resource_list *list;
           int idx;

           for (list = head->next; list; list = list->next) {
                   res = list->res;
                   idx = res - &list->dev->resource[0];
                   if (resource_size(res) && pci_assign_resource(list->dev, idx)) {
   ...
                           reset_resource(res);
                   }
           }
   }

At last, We have to clear the flags in pbus_size_mem/io when requested
size == 0 and !add_head.  becasue this case it will not go through
adjust_resources_sorted().

Just make size1 = size0 when !add_head. it will make flags get cleared.

At the same time when requested size == 0, add_size != 0, will still
have in head and add_list.  because we do not clear the flags for it.

After this, we will get right result:

  pci 0000:c0:03.0: PCI bridge to [bus c4-c9]
  pci 0000:c0:03.0:   bridge window [io  disabled]
  pci 0000:c0:03.0:   bridge window [mem 0xf0000000-0xf00fffff]
  pci 0000:c0:03.0:   bridge window [mem 0xfc180000000-0xfc197ffffff 64bit pref]
  pci 0000:c0:03.0: enabling bus mastering
  pci 0000:c0:03.0: setting latency timer to 64
  pcieport 0000:c0:03.0: setting latency timer to 64
  pcieport 0000:c0:03.0: irq 160 for MSI/MSI-X
  pcieport 0000:c0:03.0: Signaling PME through PCIe PME interrupt
  pci 0000:c4:00.0: Signaling PME through PCIe PME interrupt
  pcie_pme 0000:c0:03.0:pcie01: service driver pcie_pme loaded
  aer 0000:c0:03.0:pcie02: service driver aer loaded
  pciehp 0000:c0:03.0:pcie04: Hotplug Controller:

v3: more simple fix. also fix one typo in pbus_size_mem

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Reviewed-by: Ram Pai <linuxram@us.ibm.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-05-16 18:33:35 -07:00
Linus Torvalds
b42282e5a0 pci: fix PCI bus allocation alignment handling
In commit 13583b1659 ("PCI: refactor io size calculation code") Ram
had a thinko in the refactorization of the code: the end result used the
variable 'align' for the bus alignment, but the original code used
'min_align'.

Since then, another use of that 'align' variable got introduced by
commit c8adf9a3e8 ("PCI: pre-allocate additional resources to devices
only after successful allocation of essential resources.")

Fix both of those uses to use 'min_align' as they should.

Daniel Hellstrom <daniel@gaisler.com>
Acked-by: Ram Pai <linuxram@us.ibm.com>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2011-04-11 10:53:11 -07:00
Ram Pai
c8adf9a3e8 PCI: pre-allocate additional resources to devices only after successful allocation of essential resources.
Linux tries to pre-allocate minimal resources to hotplug bridges. This
works fine as long as there are enough resources  to satisfy all other
genuine resource requirements. However if enough resources are not
available to satisfy any of these nice-to-have pre-allocations, the
resource-allocator reports errors and returns failure.

This patch distinguishes between must-have resource from nice-to-have
resource.  Any failure to allocate nice-to-have resources are ignored.

This behavior can be particularly useful to trigger automatic
reallocation when the OS discovers genuine allocation-conflicts or
genuine unallocated-requests caused by buggy allocation behavior of the
native BIOS/uEFI.

https://bugzilla.kernel.org/show_bug.cgi?id=15960 captures the
movitation behind the patch. This patch is verified to resolve the above
bug.

    changelog v2:  o  fixed a bug where pci_assign_resource() was called on a
    		  resource of zero resource size.

    changelog v3:  addressed Bjorn's comment
    	       o  "Please don't indent and right-justify the changelog".
    	       o  removed add_size from struct resource.  The additional
    		  size is now tracked using a linked list.

    changelog v4:  o moved freeing up of elements in head list from
    		assign_requested_resources_sorted() to
    		__assign_resources_sorted().
    	       o removed a wrong reference to 'add_size' in
    			pbus_size_mem().
    	       o some code optimizations in adjust_resources_sorted()
    			and assign_requested_resources_sorted()

    changelog v5:  o moved freeing up of elements in head list from
    		assign_requested_resources_sorted() to
    		__assign_resources_sorted().
    	       o removed a wrong reference to 'add_size' in
    			pbus_size_mem().
    	       o some code optimizations in adjust_resources_sorted()
    			and assign_requested_resources_sorted()

    changelog v5:  o factored out common code and made them into
		separate independent patches
    	       o added comments in kdoc format
	       o added a BUG_ON in pci_assign_unassigned_resources()
		 to catch for memory leak.

Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-03-04 10:46:47 -08:00
Ram Pai
fc075e1da1 PCI: introduce reset_resource()
Introduce reset_resource() which factors out resource reset logic.

Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-03-04 10:46:16 -08:00
Ram Pai
094732a520 PCI: data structure agnostic free list function
Replace free_failed_list() with a free_list() call. free_list() can
handle 'resource_list_x', 'resource_list' and any linked list linked
through ->next

Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-03-04 10:46:04 -08:00
Ram Pai
13583b1659 PCI: refactor io size calculation code
Refactor code that calculates the io size in pbus_size_io() and
pbus_mem_io() into separate functions.

Signed-off-by: Ram Pai <linuxram@us.ibm.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-03-04 10:45:48 -08:00
Yinghai Lu
3f579c340f PCI hotplug: make sure child bridges are enabled at hotplug time
Found one PCIe Module with several bridges built-in where a "cold"
hotadd doesn't work.

If we end up reassigning bridge windows at hotadd time, and have to loop
through assigning new ranges, we won't end up enabling the child bridges
because the first assignment pass already tried to enable them, which
prevents __pci_bridge_assign_resource from updating the windows.

So try to move enabling of child bridges to the end, and only do it
once.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-07-30 09:29:16 -07:00
Linus Torvalds
769d9968e4 Revert "PCI: update bridge resources to get more big ranges in PCI assign unssigned"
This reverts commit 977d17bb17, because it
can cause problems with some devices not getting any resources at all
when the resource tree is re-allocated.

For an example of this, see

	https://bugzilla.kernel.org/show_bug.cgi?id=15960
	(originally https://bugtrack.alsa-project.org/alsa-bug/view.php?id=4982)
	(lkml thread: http://lkml.org/lkml/2010/4/19/20)

where Peter Henriksson reported his Xonar DX sound card gone, because
the IO port region was no longer allocated.

Reported-bisected-and-tested-by: Peter Henriksson <peter.henriksson@gmail.com>
Requested-by: Andrew Morton <akpm@linux-foundation.org>
Requested-by: Clemens Ladisch <clemens@ladisch.de>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-12 18:39:45 -07:00
Yinghai Lu
9a928660c9 pci: don't reassign to ROM res if it is not going to be enabled
A ROM resource that doesn't fit should not cause us to try to re-assign
all the bus resources.  Nobody generally cares, and re-assigning is
going to just cause way more troubles than it tries to solve.

Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-03-01 07:41:55 -08:00
Bjorn Helgaas
89a74ecccd PCI: add pci_bus_for_each_resource(), remove direct bus->resource[] refs
No functional change; this converts loops that iterate from 0 to
PCI_BUS_NUM_RESOURCES through pci_bus resource[] table to use the
pci_bus_for_each_resource() iterator instead.

This doesn't change the way resources are stored; it merely removes
dependencies on the fact that they're in a table.

Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-02-23 09:43:31 -08:00