Commit Graph

5 Commits

Author SHA1 Message Date
Rajan Vaja
e942171bbb clk: zynqmp: Add support for get max divider
To achieve best possible rate, maximum limit of divider is required
while computation. Get maximum supported divisor from firmware. To
maintain backward compatibility assign maximum possible value(0xFFFF)
if query for max divisor is not successful.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Link: https://lkml.kernel.org/r/1575527759-26452-5-git-send-email-rajan.vaja@xilinx.com
Acked-by: Michal Simek <michal.simek@xilinx.com>
[sboyd@kernel.org: Remove else return and just return]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-01-23 13:25:32 -08:00
Michael Tretter
c06e64407e clk: zynqmp: fix check for fractional clock
The firmware sets BIT(13) in clkflag to mark a divider as fractional
divider. The clock driver copies the clkflag straight to the flags of
the common clock framework. In the common clk framework flags, BIT(13)
is defined as CLK_DUTY_CYCLE_PARENT.

Add a new field to the zynqmp_clk_divider to specify if a divider is a
fractional devider. Set this field based on the clkflag when registering
a divider.

At the same time, unset BIT(13) from clkflag when copying the flags to
the common clk framework flags.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11 11:33:12 -07:00
Michael Tretter
e91158f1be clk: zynqmp: do not export zynqmp_clk_register_* functions
The zynqmp_clk_register_* functions are internal functions of the
driver. Only clkc.c uses these functions to register these clocks.
Therefore, there is no need to export these functions.

The gate and pll already don't export their register_* functions.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11 11:33:11 -07:00
Rajan Vaja
60d74e011c drivers: clk: zynqmp: Allow zero divisor value
Zero divider is valid and default for some of ZynqMP
clocks. Allow zero divisor when CLK_DIVIDER_ALLOW_ZERO
for the clock is set.

Signed-off-by: Rajan Vaja <rajanv@xilinx.com>
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-04-11 11:31:33 -07:00
Jolly Shah
3fde0e16d0 drivers: clk: Add ZynqMP clock driver
This patch adds CCF compliant clock driver for ZynqMP.
Clock driver queries supported clock information from
firmware and regiters pll and output clocks with CCF.

Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
Signed-off-by: Tejas Patel <tejasp@xilinx.com>
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Acked-by: Olof Johansson <olof@lixom.net>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-10-09 13:29:19 +02:00