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Author SHA1 Message Date
Thomas Gleixner
d2912cb15b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500 
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 2019-06-19 17:09:55 +02:00
Stephen Boyd
62e59c4e69 clk: Remove io.h from clk-provider.h 
Now that we've gotten rid of clk_readl() we can remove io.h from the
clk-provider header and push out the io.h include to any code that isn't
already including the io.h header but using things like readl/writel,
etc.

Found with this grep:

  git grep -l clk-provider.h | grep '.c$' | xargs git grep -L 'linux/io.h' | \
  	xargs git grep -l \
	-e '\<__iowrite32_copy\>' --or \
	-e '\<__ioread32_copy\>' --or \
	-e '\<__iowrite64_copy\>' --or \
	-e '\<ioremap_page_range\>' --or \
	-e '\<ioremap_huge_init\>' --or \
	-e '\<arch_ioremap_pud_supported\>' --or \
	-e '\<arch_ioremap_pmd_supported\>' --or \
	-e '\<devm_ioport_map\>' --or \
	-e '\<devm_ioport_unmap\>' --or \
	-e '\<IOMEM_ERR_PTR\>' --or \
	-e '\<devm_ioremap\>' --or \
	-e '\<devm_ioremap_nocache\>' --or \
	-e '\<devm_ioremap_wc\>' --or \
	-e '\<devm_iounmap\>' --or \
	-e '\<devm_ioremap_release\>' --or \
	-e '\<devm_memremap\>' --or \
	-e '\<devm_memunmap\>' --or \
	-e '\<__devm_memremap_pages\>' --or \
	-e '\<pci_remap_cfgspace\>' --or \
	-e '\<arch_has_dev_port\>' --or \
	-e '\<arch_phys_wc_add\>' --or \
	-e '\<arch_phys_wc_del\>' --or \
	-e '\<memremap\>' --or \
	-e '\<memunmap\>' --or \
	-e '\<arch_io_reserve_memtype_wc\>' --or \
	-e '\<arch_io_free_memtype_wc\>' --or \
	-e '\<__io_aw\>' --or \
	-e '\<__io_pbw\>' --or \
	-e '\<__io_paw\>' --or \
	-e '\<__io_pbr\>' --or \
	-e '\<__io_par\>' --or \
	-e '\<__raw_readb\>' --or \
	-e '\<__raw_readw\>' --or \
	-e '\<__raw_readl\>' --or \
	-e '\<__raw_readq\>' --or \
	-e '\<__raw_writeb\>' --or \
	-e '\<__raw_writew\>' --or \
	-e '\<__raw_writel\>' --or \
	-e '\<__raw_writeq\>' --or \
	-e '\<readb\>' --or \
	-e '\<readw\>' --or \
	-e '\<readl\>' --or \
	-e '\<readq\>' --or \
	-e '\<writeb\>' --or \
	-e '\<writew\>' --or \
	-e '\<writel\>' --or \
	-e '\<writeq\>' --or \
	-e '\<readb_relaxed\>' --or \
	-e '\<readw_relaxed\>' --or \
	-e '\<readl_relaxed\>' --or \
	-e '\<readq_relaxed\>' --or \
	-e '\<writeb_relaxed\>' --or \
	-e '\<writew_relaxed\>' --or \
	-e '\<writel_relaxed\>' --or \
	-e '\<writeq_relaxed\>' --or \
	-e '\<readsb\>' --or \
	-e '\<readsw\>' --or \
	-e '\<readsl\>' --or \
	-e '\<readsq\>' --or \
	-e '\<writesb\>' --or \
	-e '\<writesw\>' --or \
	-e '\<writesl\>' --or \
	-e '\<writesq\>' --or \
	-e '\<inb\>' --or \
	-e '\<inw\>' --or \
	-e '\<inl\>' --or \
	-e '\<outb\>' --or \
	-e '\<outw\>' --or \
	-e '\<outl\>' --or \
	-e '\<inb_p\>' --or \
	-e '\<inw_p\>' --or \
	-e '\<inl_p\>' --or \
	-e '\<outb_p\>' --or \
	-e '\<outw_p\>' --or \
	-e '\<outl_p\>' --or \
	-e '\<insb\>' --or \
	-e '\<insw\>' --or \
	-e '\<insl\>' --or \
	-e '\<outsb\>' --or \
	-e '\<outsw\>' --or \
	-e '\<outsl\>' --or \
	-e '\<insb_p\>' --or \
	-e '\<insw_p\>' --or \
	-e '\<insl_p\>' --or \
	-e '\<outsb_p\>' --or \
	-e '\<outsw_p\>' --or \
	-e '\<outsl_p\>' --or \
	-e '\<ioread8\>' --or \
	-e '\<ioread16\>' --or \
	-e '\<ioread32\>' --or \
	-e '\<ioread64\>' --or \
	-e '\<iowrite8\>' --or \
	-e '\<iowrite16\>' --or \
	-e '\<iowrite32\>' --or \
	-e '\<iowrite64\>' --or \
	-e '\<ioread16be\>' --or \
	-e '\<ioread32be\>' --or \
	-e '\<ioread64be\>' --or \
	-e '\<iowrite16be\>' --or \
	-e '\<iowrite32be\>' --or \
	-e '\<iowrite64be\>' --or \
	-e '\<ioread8_rep\>' --or \
	-e '\<ioread16_rep\>' --or \
	-e '\<ioread32_rep\>' --or \
	-e '\<ioread64_rep\>' --or \
	-e '\<iowrite8_rep\>' --or \
	-e '\<iowrite16_rep\>' --or \
	-e '\<iowrite32_rep\>' --or \
	-e '\<iowrite64_rep\>' --or \
	-e '\<__io_virt\>' --or \
	-e '\<pci_iounmap\>' --or \
	-e '\<virt_to_phys\>' --or \
	-e '\<phys_to_virt\>' --or \
	-e '\<ioremap_uc\>' --or \
	-e '\<ioremap\>' --or \
	-e '\<__ioremap\>' --or \
	-e '\<iounmap\>' --or \
	-e '\<ioremap\>' --or \
	-e '\<ioremap_nocache\>' --or \
	-e '\<ioremap_uc\>' --or \
	-e '\<ioremap_wc\>' --or \
	-e '\<ioremap_wc\>' --or \
	-e '\<ioremap_wt\>' --or \
	-e '\<ioport_map\>' --or \
	-e '\<ioport_unmap\>' --or \
	-e '\<ioport_map\>' --or \
	-e '\<ioport_unmap\>' --or \
	-e '\<xlate_dev_kmem_ptr\>' --or \
	-e '\<xlate_dev_mem_ptr\>' --or \
	-e '\<unxlate_dev_mem_ptr\>' --or \
	-e '\<virt_to_bus\>' --or \
	-e '\<bus_to_virt\>' --or \
	-e '\<memset_io\>' --or \
	-e '\<memcpy_fromio\>' --or \
	-e '\<memcpy_toio\>'

I also reordered a couple includes when they weren't alphabetical and
removed clk.h from kona, replacing it with clk-provider.h because
that driver doesn't use clk consumer APIs.

Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Sekhar Nori <nsekhar@ti.com>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Mark Brown <broonie@kernel.org>
Cc: Chris Zankel <chris@zankel.net>
Acked-by: Max Filippov <jcmvbkbc@gmail.com>
Acked-by: John Crispin <john@phrozen.org>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-05-15 13:21:37 -07:00
Marek Szyprowski
c41b0ff2f6 clk: samsung: exynos5250: Use generic helper for handling suspend/resume 
Replace common suspend/resume handling code by generic helper.
Almost no functional change, the only difference is in handling
of hypothetical memory allocation failure on boot.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
 2018-10-05 13:36:30 +02:00
Marek Szyprowski
5b23fceec1 clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices 
FIMC LITE SYSMMU devices are defined in exynos5250.dtsi, but clocks for
them are not instantiated by Exynos5250 clock provider driver. Add needed
definitions for those clocks to fix IOMMU probe failure:

ERROR: could not get clock /soc/sysmmu@13c40000:sysmmu(0)
exynos-sysmmu 13c40000.sysmmu: Failed to get device clock(s)!
exynos-sysmmu: probe of 13c40000.sysmmu failed with error -38
ERROR: could not get clock /soc/sysmmu@13c50000:sysmmu(0)
exynos-sysmmu 13c50000.sysmmu: Failed to get device clock(s)!
exynos-sysmmu: probe of 13c50000.sysmmu failed with error -38

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Fixes: bfed1074f2 ("clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks")
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
 2018-03-14 12:12:11 +01:00
Marek Szyprowski
edcefb96fb clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU 
Clocks related to DISP1 block require special handling for power domain
turn on/off sequences. Till now this was handled by Exynos power domain
driver, but that approach was limited only to some special cases. This
patch moves handling of those operations to clock controller driver.
This gives more flexibility and allows fine tune values of some
clock-specific registers. This patch moves handling of those mentioned
clocks to Exynos5 sub-CMU driver instantiated from Exynos5250 driver.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
 2018-03-06 17:39:40 +01:00
Andrzej Hajda
1d5013f1b6 clk: samsung: Add compile time PLL rate validators 
Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. To avoid possible mistakes we can use compile
time validation.
The patch introduces such validators and expands all initializers
with additional input frequency parameter, required to validate rates.
Since S3C24xx PLLs requires different validators two new macros have
been introduced to deal with it. Also, since PLLs 4502 and 4508 have
different formulas PLL_45XX_RATE has been replaced with PLL_4508_RATE.

As the patch adds only compile time validators it should not have impact
on compiled code.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
 2018-02-23 15:15:20 +01:00
Andrzej Hajda
2ac051eeab clk: samsung: exynos5250: Fix PLL rates 
Rates declared in PLL rate tables should match exactly rates calculated
from PLL coefficients. If that is not the case, rate of the PLL's child clock
might be set not as expected. For instance, if in the PLL rates table we have
a 393216000 Hz entry and the real value as returned by the PLL's recalc_rate
callback is 393216003, after setting PLL's clk rate to 393216000 clk_get_rate
will return 393216003. If we now attempt to set rate of a PLL's child divider
clock to 393216000/2 its rate will be 131072001, rather than 196608000.
That is, the divider will be set to 3 instead of 2, because 393216003/2 is
greater than 196608000.

To fix this issue declared rates are changed to exactly match rates generated
by the PLL, as calculated from the P, M, S, K coefficients.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
 2018-02-23 15:14:57 +01:00
Marek Szyprowski
29964890f3 clk: samsung: Remove clkdev alias support in Exynos5250 clk driver 
All Exynos5250 boards have been fully converted to device-tree and use
generic dt-based CPUfreq driver, so there is no need to create any clkdev
aliases for the clocks. Drop all the code related to aliases handling.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
 2017-10-09 11:31:29 +02:00
Krzysztof Kozlowski
1d3f15a89e clk: samsung: exynos5250: Move sleep init function to init section 
The exynos5250_clk_sleep_init() function can be moved to init section
because it is referenced only from other init-level calls.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
 2016-06-02 11:18:12 +02:00
Krzysztof Kozlowski
5b37e8494d clk: samsung: exynos5250: Constify all clock initializers 
All of initialization data can be made const.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
 2016-06-02 11:18:05 +02:00
Krzysztof Kozlowski
dfb86ade53 clk: samsung: Remove useless check for return value of samsung_clk_init 
The samsung_clk_init() cannot return NULL. Either it returns allocated
memory or it panics.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
 2016-06-02 11:17:57 +02:00
Stephen Boyd
728f288d2a clk: samsung: Remove CLK_IS_ROOT 
This flag is a no-op now. Remove usage of the flag.

Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 2016-03-02 17:46:29 -08:00
Tomeu Vizoso
b4dc272b60 clk: samsung: exynos5250: Add DISP1 clocks 
When the DISP1 power domain is powered off, there's two clocks that need
to be temporarily reparented to OSC, and back to their original parents
when the domain is powered on again.

We expose these two clocks in the DT bindings so that the DT node of the
power domain can reference them.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
 2015-10-24 04:31:18 +09:00
Michael Turquette
1db92e54f5 Merge branch 'v4.3-topic/clk-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into clk-next 2015-07-28 11:59:21 -07:00
Thomas Abraham
d7cc4c8165 clk: exynos5250: add cpu clock configuration data and instantiate cpu clock 
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5250.

Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
[b.zolnierkie: split exynos5250 support from the original patch]
[b.zolnierkie: moved E5250_CPU_DIV[0,1] macros to clk-exynos5250.c]
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@dowhile0.org>
Tested-by: Javier Martinez Canillas <javier@dowhile0.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
 2015-07-24 12:41:48 +09:00
Stephen Boyd
6f1ed07a14 clk: samsung: Properly include clk.h and clkdev.h 
Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are
using it. The clkdev.h header isn't always used either, so remove
it and add in slab.h where files were relying on it to include
slab for them.

Cc: Chanwoo Choi <cw00.choi@samsung.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 2015-07-20 11:11:11 -07:00
Krzysztof Kozlowski
305cfab0ba clk: samsung: Make of_device_id array const 
Array of struct of_device_id may be be const as expected by
of_match_table field and of_find_matching_node_and_match() function.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2014-07-26 02:49:58 +02:00
Sylwester Nawrocki
d5e136a21b clk: samsung: Register clk provider only after registering its all clocks 
Ensure the clock provider is not registered until after all its related
clocks were created and are ready to use. Currently there are races
possible and any (of_)clk_get() call right after a clock provider's
clk_init_cb callback call may fail.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2014-06-30 15:07:55 +02:00
Rahul Sharma
0b1643b39d clk/exynos5250: fix bit number for tv sysmmu clock 
Change bit from 2 to 9 for tv (mixer) sysmmu clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Reviewed-by: Sachin Kamat <sachin.kamat@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2014-06-30 14:46:36 +02:00
Olof Johansson
45e70b7d48 Samsung 2nd drivers for 3.16 
This is including fix exynos cpufreq driver compilation with
 ARCH_MULTIPLATFORM. Even though this is a work around, this
 is required for support exynos multiplatform for a while and
 will be updated in near future.
 
 This is based on tags/samsung-exynos.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJTiN4aAAoJEA0Cl+kVi2xqh14P/2Alq0Q4KgPmlsIIOsofADLw
 BEig7xQAh9iREkfKLm6Wy1K/OP99jNWdbtZnMF1UK3pTxNVPKluz3ZADdJXJWlmb
 UsZcu60l9ZuZ+B4vTUG7jQx2oq6sxo7aLVMyTvT+kWmzZsNWEdqMDzDATgqjPOW8
 yGfWg6KwdTkpGbesID6w1h2D611RDIhJU+LpXE+AmyKWX3x/jkOxOU49CY8bKEhw
 ZwYw41vjTk8e2U/cBYCjqPhEuUzpFq+mmVQcVDGch/p/TFUA1/SbzuqbVDHVe+yZ
 qQHNZREsAWJPFJ22IjUleq/oNLiSVkJVVSkVrfXCwowzzPsw+cLFDuSRaJMROm1a
 baR77C0TJREqoXu4FexBSoWLPYbn7aUOlZ3wGmr/7MnPK/bK3e9BGiOsJ8GPIQuF
 e2ytESFl15ABduY0lV0H/TtOxjx8JZJf+xxh0Ip0qoE8XNkNxt5cIsMW7LD/NcaE
 zUuPoO+w97pUxyVDrTPXakLRdn643PmYRX+rMG8gXP82m/CiCKe+x8znc7BkXIq2
 h8rvSLqnWQFYUdEj/0/T8scRT5DyZPjSTDguUj+lhDU2rE0gWNCHEO+2a7Qwm8Js
 YfeQ4dd71ZNqzw8Ui62do2HzNGIA/FWPwQBzHeu2tPxVrWOwSQz/zSA4TLwjeB3J
 n1Tzm9JOJNwH3FTAcH9k
 =SQbr
 -----END PGP SIGNATURE-----

Merge tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers

Merge "Samsung 2nd drivers for 3.16" from Kukjin Kim:

This is including fix exynos cpufreq driver compilation with
ARCH_MULTIPLATFORM. Even though this is a work around, this
is required for support exynos multiplatform for a while and
will be updated in near future.

This is based on tags/samsung-exynos.

* tag 'samsung-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (24 commits)
  cpufreq: exynos: Fix driver compilation with ARCH_MULTIPLATFORM
  ARM: EXYNOS: Enable multi-platform build support
  ARM: EXYNOS: Consolidate Kconfig entries
  ARM: EXYNOS: Add support for EXYNOS5410 SoC
  ARM: EXYNOS: Support secondary CPU boot of Exynos3250
  ARM: EXYNOS: Add Exynos3250 SoC ID
  ARM: EXYNOS: Add 5800 SoC support
  ARM: EXYNOS: initial board support for exynos5260 SoC
  clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks
  cpufreq: exynos: Fix the compile error
  ARM: S3C24XX: move debug-macro.S into the common space
  ARM: S3C24XX: use generic DEBUG_UART_PHY/_VIRT in debug macro
  ARM: S3C24XX: trim down debug uart handling
  ARM: compressed/head.S: remove s3c24xx special case
  ARM: EXYNOS: Remove unnecessary inclusion of cpu.h
  ARM: EXYNOS: Migrate Exynos specific macros from plat to mach
  ARM: EXYNOS: Remove exynos_subsys registration
  ARM: EXYNOS: Remove duplicate lines in Makefile
  ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disabling
  ARM: dts: Remove g2d_pd node for exynos5420
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>
 2014-05-30 21:48:39 -07:00
Cho KyongHo
bfed1074f2 clk: exynos5250: Add missing sysmmu clocks for DISP and ISP blocks 
This patch adds the missing sysmmu clocks for Display and
ISP blocks.

Signed-off-by: Cho KyongHo <pullip.cho@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
 2014-05-26 06:48:10 +09:00
Amit Daniel Kachhap
9a8f39950d ARM: EXYNOS: Move arm core power down clock to exynos5250 common clock 
Now with common clock support added for exynos5250 it is necessary to
move this code to exynos5250 common clock driver as clock registers
should be handled there. This change is tested in exynos5250 based
arndale platform.

Cc: Abhilash Kesavan <a.kesavan@samsung.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsugn.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
[t.figa: Rebased onto current kernel sources.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
 2014-05-26 05:21:06 +09:00
Arun Kumar K
20b82ae27e clk: samsung: exynos5250: Add clocks for G3D 
This patch adds the required clocks for ARM Mali IP
in Exynos5250.

Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
[t.figa: Changed clock ID to avoid conflict with CLK_SSS]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2014-05-14 19:40:15 +02:00
Naveen Krishna Chatradhi
5b73721b60 clk: samsung: exynos5250/5420: Add gate clock for SSS module 
This patch adds gating clock for SSS(Security SubSystem)
module on Exynos5250/5420.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
[t.figa: Fixed sort order and group name.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2014-05-14 19:23:26 +02:00
Rahul Sharma
976face4b4 clk/samsung: add support for multiple clock providers 
Samsung CCF helper functions do not provide support to
register multiple Clock Providers for a given SoC. Due to
this limitation, SoC platforms are not able to use these
helpers for registering multiple clock providers and are
forced to bypass this layer.

This layer is modified accordingly to enable the support
for multiple clock providers.

Clock file for exynos4, exynos5250, exynos5420, exynos5440,
S3c64xx, S3c24xx are also modified as per changed helper functions.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
[t.figa: Modified s3c2410 clock driver as well]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2014-05-14 19:15:38 +02:00
Tomasz Figa
3efb251167 clk: samsung: Drop old suspend/resume code 
Since all SoC drivers have been moved to local suspend/resume handling,
the old code can be safely dropped.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
 2014-02-14 08:16:01 +09:00
Tomasz Figa
c3b6c1d701 clk: samsung: exynos5250: Move suspend/resume handling to SoC driver 
Since there are multiple differences in how suspend/resume of particular
Exynos SoCs must be handled, SoC driver is better place for
suspend/resume handlers and so this patch moves them.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
 2014-02-14 08:16:00 +09:00
Andrew Bresticker
35399dda01 clk: exynos5250: add clock ID for div_pcm0 
There is no gate for the PCM clock input to the AudioSS block, so
the parent of sclk_pcm is div_pcm0.  Add a clock ID for it so that
we can reference it in device trees.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2014-01-08 18:02:42 +01:00
Andrzej Hajda
2fe8f00c49 clk: exynos5250: replace clock ID private enums with IDs from DT header 
The patch replaces private enum clock IDs in the driver with macros provided
by the DT header.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2014-01-08 18:02:38 +01:00
Andrew Bresticker
f521ac8b39 clk: exynos5250: register APLL rate table 
Register the APLL rate table so that we can set the APLL rate from
the cpufreq driver.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2014-01-08 18:01:49 +01:00
Sachin Kamat
e86ffc4199 clk: exynos5250: Add CLK_SET_RATE_PARENT flag to mout_apll 
Add CLK_SET_RATE_PARENT flag to mout_apll clock. This will let us set the
clock rate in the cpufreq driver.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 18:43:28 +01:00
Tomasz Figa
96987ded8f clk: samsung: exynos5250: Fix parents of gate clocks from MFC domain 
This patch adds mout_aclk333_sub mux clock and updates gate clocks from
MFC domain to have it as their parent as specified in SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 18:15:49 +01:00
Tomasz Figa
bfeb9f274b clk: samsung: exynos5250: Correct parent list of audio muxes 
According to SoC documentation, input 5 of mout_audio muxes is connected
to xxti (named fin_pll in the driver). This patch corrects defined
parent arrays to match SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 18:15:49 +01:00
Tomasz Figa
256dd646a3 clk: samsung: exynos5250: Add missing unpopulated mux parents 
This patch updates mux parent arrays with unpopulated mux inputs, as all
inputs need to be specified in parent arrays passed to
clk_register_mux(), otherwise clk_set_parent() can generate out of bound
accesses to the array.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 18:15:48 +01:00
Tomasz Figa
3818f11740 clk: samsung: exynos5250: Fix parent of gate clocks from DISP1 domain 
This patch adds mux_aclk_200_disp1_sub mux clock, which according to SoC
documentation is the correct parent of DISP1 gate clocks.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 18:15:48 +01:00
Tomasz Figa
796d1f4cd6 clk: samsung: exynos5250: Fix parents of gate clocks from GSCL domain 
This patch adds mout_aclk266_gscl_sub mux clock and adjusts definitions
of GSCL domain gate clocks to use it as their parent, as specified in
SoC documentation.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 18:15:47 +01:00
Tomasz Figa
38ee37540f clk: samsung: exynos5250: Make names of mux and div clocks consistent 
This patch renames all mux clocks to start with mout_ prefix and all div
clocks to start with div_ prefix for consistency with other clocks
already defined this way.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 18:15:47 +01:00
Tomasz Figa
2786c9622e clk: samsung: exynos5250: Sort definitions by registers and bitfield 
This patch reorders clock definitions, so they are sorted by register
addresses and bitfield shifts. When at it, blank lines are added to
separate definitions of clocks from different registers.

Overall this should make the driver more readable and reduce the number
of potential conflicts when adding new entries.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 18:15:46 +01:00
Abhilash Kesavan
2feed5aecf clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock 
The sysreg (system register) generates control signals for various blocks
like disp1blk, i2c, mipi, usb etc. However, it gets disabled as an unused
clock at boot-up. This can lead to failures in operation of above blocks,
because they can not be configured properly if this clock is disabled.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 17:59:25 +01:00
Abhilash Kesavan
8fb9aeb7a7 clk: samsung: exynos5250: Add MDMA0 clocks 
Adds gate clock for MDMA0 on Exynos5250 SoC. This is needed to ensure
that the clock is enabled when MDMA0 is used on systems on which
firmware gates the clockby default.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 17:55:52 +01:00
Abhilash Kesavan
3bf34666a0 clk: samsung: exynos5250: Fix ACP gate register offset 
The CLK_GATE_IP_ACP register offset is incorrectly listed making
definition of g2d clock incorrect, which may lead to system failures
when trying to use G2D on systems on which firmware gates this clock
by default. Fix this and the register ordering as well.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Updated patch description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 17:53:26 +01:00
Andrew Bresticker
97c3557c3e clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks 
The gate clocks for the MFC sysmmus appear to be flipped, i.e.
GATE_IP_MFC[2] gates sysmmu_mfcl and GATE_IP_MFC[1] gates sysmmu_mfcr.
Fix this so that the MFC will start up.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
 2013-12-30 17:53:22 +01:00
Tomasz Figa
22e9e7589e clk: samsung: exynos5250: Simplify registration of PLL rate tables 
Since the _get_rate() helper has been modified to use __clk_lookup()
internally, checking of PLL input rates can be done using it and so the
registration code can be simplified.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2013-09-06 13:34:05 -07:00
Rahul Sharma
e2815b048a clk/exynos5250: change parent to aclk200_disp1 for hdmi subsystem 
parent of hdmi and mixer block is mentioned as aclk200 which is
not correct. It is clocked by the ouput of aclk200_disp1. Hence
parent for mixer and hdmi clocks is changed to aclk200_disp1.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2013-08-28 19:23:40 -07:00
Sachin Kamat
b6993ecb87 clk: exynos5250: Fix incorrect placement of __initdata 
__initdata should be placed between the variable name and equal
sign for the variable to be placed in the intended section.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2013-08-08 15:57:35 -07:00
Sachin Kamat
ae2329f790 clk: exynos5250: Make exynos5250_plls static 
exynos5250_plls is used only in this file. Make it static.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2013-08-08 15:57:31 -07:00
Vikas Sajjan
d2127ac451 clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoC 
Adds the EPLL and VPLL freq table for exynos5250 SoC.

Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2013-08-02 13:24:18 -07:00
Vikas Sajjan
8bc2eeb83e clk: samsung: Reorder MUX registration for mout_vpllsrc 
While trying to get rate of "mout_vpllsrc" MUX (parent) for registering the
"fout_vpll" (child), we found get rate was failing.

So this patch moves the mout_vpllsrc MUX out of the existing common list
and registers the mout_vpllsrc MUX before the PLL registrations.

Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2013-08-02 13:22:28 -07:00
Yadwinder Singh Brar
3ff6e0d8d6 clk: samsung: Add support to register rate_table for samsung plls 
This patch defines a common rate_table which will contain recommended p, m, s,
k values for supported rates that needs to be changed for changing
corresponding PLL's rate.

Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2013-08-02 13:22:09 -07:00
Yadwinder Singh Brar
8dac3530c7 clk: samsung: Migrate exynos5250 to use common samsung_clk_register_pll() 
This patch migrates exynos5250 pll registeration to use common
samsung_clk_register_pll() by intialising table of PLLs and adding PLLs to
unique id list of clocks.

Signed-off-by: Yadwinder Singh Brar <yadi.brar@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
 2013-08-02 13:21:27 -07:00