Commit Graph

10 Commits

Author SHA1 Message Date
Chen-Yu Tsai
966c11a3b5 ARM: dts: sun8i-h3: Add uart1 pinmux setting
Add uart1 pins for 4 pin (RX/TX/RTS/CTS) mode.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-07-04 21:17:54 +02:00
Chen-Yu Tsai
2bcb2b1b95 ARM: dts: sun8i-h3: move uart0 pins to sort pinmux list in proper order
Move uart0 pins to sort the list of pin settings in alphabetical order.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-07-04 21:17:53 +02:00
Reinder de Haan
4cf9654eb5 ARM: dts: sun8i: Add usbphy and usb host controller nodes
Add nodes describing the H3's usbphy and usb host controller nodes.

Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-03-27 16:15:04 +02:00
Reinder de Haan
bc9aa43fa9 ARM: dts: sun8i: Add support for H3 usb clocks
Add a node describing the usb-clks found on the H3.

Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-03-27 16:15:04 +02:00
Hans de Goede
9461faf20f ARM: dts: sun8i: Add mmc2_8bit_pins to sun8i-h3.dtsi
Add a pinctrl node for mmc2 in 8 bits mode on H3 SoCs.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-03-27 16:15:04 +02:00
Hans de Goede
fe0a8ea1fb ARM: dts: sun8i: Add ir receiver nodes to H3 dtsi
The H3 ir receiver is completely compatible with the one found in the A31.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-25 11:38:42 -08:00
Krzysztof Adamski
9338536731 ARM: dts: sun8i-h3: Add R_PIO controller node to the dtsi
Add the corresponding device node for R_PIO on H3 to the dtsi. Support
for the controller was added in earlier commit.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-25 11:33:36 -08:00
Krzysztof Adamski
097872945e dts: sun8i-h3: Add APB0 related clocks and resets
APB0 is bearly mentioned in H3 User Manual and it is only setup in the
Allwinners kernel dump for CIR. I have verified experimentally that the
gate for R_PIO exists and works, though. There are probably other gates
there but I don't know their order right now and I don't have access to
their peripherals on my board to test them.

After some experiments and reviewing how this is organized on other
sunxi SoCs, I couldn't actually find any way to disable clocks for R_PIO
and they are working properly without doing anything so I assume they
are connected straight to the 24Mhz oscillator for now.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-25 11:33:05 -08:00
Krzysztof Adamski
5bcaf95c26 ARM: dts: sunxi: Fix #interrupt-cells for PIO in H3
pinctrl-sunxi uses 3 cells to describe interrupt, not 2. It's bank
number, pin number and flags.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-08 18:19:26 +01:00
Jens Kuske
318d93bc41 ARM: dts: sunxi: Add Allwinner H3 DTSI
The Allwinner H3 is a home entertainment system oriented SoC with
four Cortex-A7 cores and a Mali-400MP2 GPU.

Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-12-08 09:28:24 +01:00