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dbc571690e
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63 Commits

Author SHA1 Message Date
Ralf Baechle
dbc571690e Fix wrong comment. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:38 +01:00
Ralf Baechle
ec917c2c1a Fixup a few lose ends in explicit support for MIPS R1/R2. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:37 +01:00
Ralf Baechle
65f1f5a2c3 Don't copy SB1 cache error handler to uncached memory. 
This may have made sense on a paranoid day with pass 1 BCM1250 processors
that were throwing cache error exception left and right for no good
reason.  On modern silicion that hardly makes sense and the code had
gotten just an obscurity ...
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:34 +01:00
Andrew Isaacson
46dc3a4a09 Fix stale comment in c-sb1.c. 
Signed-Off-By: Andrew Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:33 +01:00
Ralf Baechle
02cf211968 Cleanup the mess in cpu_cache_init. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:32 +01:00
Ralf Baechle
f5cfa980e5 Use R4000 TLB routines for SB1 also. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:31 +01:00
Atsushi Nemoto
9043f7e95d Sync c-tx39.c with c-r4k.c. 
tx39_flush_cache_range() does nothing if !cpu_has_dc_aliases.  It should
flush d-cache and invalidate i-cache since the TX39(H2) has separate I/D
cache.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:28 +01:00
Thiemo Seufer
10a3dabddd Add/Fix missing bit of R4600 hit cacheop workaround. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:18 +01:00
Thiemo Seufer
02fe2c9ce3 Minor code cleanup. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:17 +01:00
Thiemo Seufer
f5b4d9563b R4600 v2.0 needs a nop before tlbp. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:17 +01:00
Thiemo Seufer
424cadae94 Don't set up a sg dma address if we have no page address for some reason. 
Code cleanup.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:17 +01:00
Thiemo Seufer
d8748a3abf More .set push/pop. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:16 +01:00
Thiemo Seufer
330cfe016b Let r4600 PRID detection match only legacy CPUs, cleanups. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:15 +01:00
Ralf Baechle
7623debf26 Handle mtc0 - tlb write hazard for VR5432. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:12 +01:00
Ralf Baechle
1d40cfcd34 Avoid SMP cacheflushes. This is a minor optimization of startup but 
will also avoid smp_call_function from doing stupid things when called
from a CPU that is not yet marked online.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:54 +01:00
Pete Popov
bdf21b18b4 Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:54 +01:00
Ralf Baechle
e01402b115 More AP / SP bits for the 34K, the Malta bits and things. Still wants 
a little polishing.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:53 +01:00
Ralf Baechle
ec74e361f1 Mark a few variables __read_mostly. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:46 +01:00
Ralf Baechle
cc61c1fede MIPS R2 instruction hazard handling. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:46 +01:00
Ralf Baechle
bbc7f22f6d Detect the 34K. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:45 +01:00
Ralf Baechle
60080265a1 Define kmap_atomic_pfn() for MIPS. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:42 +01:00
Ralf Baechle
3ef33e68c1 Date: Fri Jul 8 20:10:17 2005 +0000 
Those literals are long.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:40 +01:00
Ralf Baechle
6e760c8dae Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:37 +01:00
Maciej W. Rozycki
2c93e12cfe Avoid tlbw* hazards for the R4600/R4700/R5000. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:34 +01:00
Maciej W. Rozycki
c3455b0efc Inline ioremap() calls for constant addresses that map to KSEG1. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:34 +01:00
Maciej W. Rozycki
4c0a2d4275 Fix the diagnostic dump for the XTLB refill handler. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:32 +01:00
Maciej W. Rozycki
41986a6e7e Fix a diagnostic message. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:32 +01:00
Maciej W. Rozycki
c6ad7b7d3c Use macros for the RM7k cp0.config bits instead of magic numbers. 
Minor clean-ups.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:28 +01:00
Maciej W. Rozycki
fded2e508a Optimize R3k TLB Load/Store/Modified handlers, by scheduling 
delay slots properly and avoiding an unnecessary jump to a jump.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:22 +01:00
Maciej W. Rozycki
d925c262dd Fill R3k load delay slots properly. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:21 +01:00
Maciej W. Rozycki
9678e28b1a Only dump instructions actually emitted. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:21 +01:00
Thiemo Seufer
63b2d2f4d2 Handle _PAGE_DIRTY correctly for CONFIG_64BIT_PHYS_ADDR on 32bit CPUs. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:11 +01:00
Thiemo Seufer
ba5187dbb4 Better interface to run uncached cache setup code. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:11 +01:00
Ralf Baechle
1342f7e6c5 Arrested for multiple offences of header file inclusion. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:07 +01:00
Thiemo Seufer
172546bf60 Fix race conditions for read_c0_entryhi. Remove broken ASID masks in 
tlb-sb1.c. Make tlb-r4k.c and tlb-sb1.c more similiar and more efficient.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:01 +01:00
Maciej W. Rozycki
202d0388e7 Remove useless casts. Fix formatting. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:00 +01:00
Thiemo Seufer
1b3a6e975c Fix 64bit SMP TLB handler and stack frame handling, optimize 32bit SMP 
TLB handlers a bit, match definitions in pgtable-{32,64}.h better.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:00 +01:00
Ralf Baechle
6cbe063159 R4300 delay slot. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:59 +01:00
Ralf Baechle
53de0d471f Reformat; cosmetic cleanups. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:57 +01:00
Ralf Baechle
9ff77c469e Export shm_align_mask and flush_data_cache_page. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:54 +01:00
Ralf Baechle
77c728c224 Gcc 4.0 fixes. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:53 +01:00
Ralf Baechle
fe00f943e0 Sparseify MIPS. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:50 +01:00
Pete Popov
e3ad1c23ba Base Au1200 2.6 support. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:47 +01:00
Thiemo Seufer
685f779e60 Fix initialization. Unbreak the wait-for-completion loops. Code cleanup. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:44 +01:00
Maciej W. Rozycki
65bda1a95d Switch SiByte drivers back to __raw_*() functions. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:44 +01:00
Thiemo Seufer
16033d6104 Handle addresses beyond VMALLOC_END correctly. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:38 +01:00
Thiemo Seufer
26a51b270f Use intermediate variable. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:38 +01:00
Ralf Baechle
79acf83e50 Moves a test which determines if we actually need to perform a 
cacheflush to the right place.  That's a bug which is harmless on UP
but a severe bug on SMP.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:31 +01:00
Ralf Baechle
c6e8b58771 Update MIPS to use the 4-level pagetable code thereby getting rid of 
the compacrapability headers.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:31 +01:00
Ralf Baechle
505403b6a0 25Kf is also physically indexed. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:29 +01:00