Commit Graph

24 Commits

Author SHA1 Message Date
Masahiro Yamada
fb28cef06a arm64: dts: uniphier: make compatible of syscon nodes SoC-specific
These hardware blocks are SoC-specific, so their compatible strings
should be SoC-specific as well.  This change has no impact on the
actual behavior since it is controlled by the generic "simple-mfd",
"syscon" compatible strings.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-11-05 23:30:11 +09:00
Masahiro Yamada
183ad3669f arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC
Add a CPU clock to every CPU node and CPU OPP tables to use the
generic cpufreq driver.  All the CPUs in each cluster share the
same OPP table.

Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2016-11-05 13:25:41 +09:00
Masahiro Yamada
bdb8183681 arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
Add a CPU clock to every CPU node and a CPU OPP table to use the
generic cpufreq driver.

Note:
clock-latency-ns (300ns) was calculated based on the CPU-gear switch
sequencer spec; it takes 12 clock cycles on the sequencer running
at 50 MHz, plus a bit additional latency.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2016-11-05 13:25:32 +09:00
Masahiro Yamada
1ef64af817 arm64: dts: uniphier: increase register region size of sysctrl node
The System Control node has 0x10000 byte of registers.  The current
reg size must be expanded to use the cpufreq driver because the
registers controlling CPU frequency are located at offset 0x8000.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-11-05 13:25:16 +09:00
Masahiro Yamada
2f81137f03 arm64: dts: uniphier: switch over to PSCI enable method
At the first system bring-up, I chose to use spin-table because ARM
Trusted Firmware was not ready for this platform at that moment.

Actually, these SoCs are equipped with EL3 and able to provide PSCI.
Now I finished porting the ATF BL31 for the UniPhier platform, so it
is ready to migrate to PSCI enable method.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-11-05 13:24:57 +09:00
Masahiro Yamada
8e68c65d11 arm64: dts: uniphier: change MIO node to SD control node
I made a mistake bacuse the Media I/O block is not implemented in
this SoC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-10-22 21:59:21 +09:00
Arnd Bergmann
37179033fc Merge branch 'dt/irq-fix' into next/dt64
* dt/irq-fix:
  arm64: dts: Fix broken architected timer interrupt trigger

This resolves a non-obvious conflict between a bugfix from
v4.8 and a cleanup for the exynos7 platform.
2016-09-14 22:48:29 +02:00
Marc Zyngier
f2a89d3b2b arm64: dts: Fix broken architected timer interrupt trigger
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).

A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.

The respective maintainers are of course welcome to prove me wrong.

While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).

Acked-by: Duc Dang <dhdang@apm.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-09-14 22:47:22 +02:00
Masahiro Yamada
270e0c3e1e arm64: dts: uniphier: add LD11 SoC/Board support
This is a low-cost 64bit SoC from Socionext.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-31 05:48:18 +09:00
Masahiro Yamada
9d4f550590 arm64: dts: uniphier: add specific compatible to SoC-Glue node
This is a simple MFD, but add a specific compatible just in case.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-31 05:41:31 +09:00
Masahiro Yamada
42aee2752c arm64: dts: uniphier: use clock/reset controllers
The UniPhier reset controller driver has been merged.  Enable it.
Also, replace the fixed-rate clocks with the dedicated clock
drivers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-31 05:28:44 +09:00
Masahiro Yamada
5d9a83c9c2 arm64: dts: uniphier: add pinctrl property to System Bus node
This pinctrl is needed to get access to the UniPhier System Bus.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-30 21:11:22 +09:00
Masahiro Yamada
cea59bd02c arm64: dts: uniphier: match DT names to other projects and documents
All UniPhier device trees have the common prefix "uniphier-", so
"ph1-" is just making names longer.  Recent documents and other
projects are not using PH1- prefixes any more.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-08-30 21:02:51 +09:00
Masahiro Yamada
ffd8a5ed57 arm64: dts: uniphier: add /memreserve/ for spin-table release address
As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14 10:40:31 -07:00
Masahiro Yamada
1388ea2a8d arm64: dts: uniphier: change cpu-release-address
At first, 256 byte of the head of DRAM space was reserved for some
reasons.  However, as the progress of development, it turned out
unnecessary, and it was never used in the end.  Move the CPU release
address to leave no space.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14 10:40:29 -07:00
Masahiro Yamada
ed6cca5f9a arm64: dts: uniphier: add SoC-Glue node to UniPhier 64bit SoCs
This node consists of various system-level configuration registers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-06-14 10:40:15 -07:00
Linus Torvalds
2ec3240fd7 ARM: 64-bit DT updates for v4.7
We continue ramping up platform support for 64-bit ARM machines,
 with 111 individual non-merge changesets touching 21 platforms.
 
 The LG1312 platform is completely new and is the first ARM
 platform by LG that we support in the mainline kernel. Two other
 SoCs got added that are updated versions of existing SoC
 families, so the port mainly consists of new dts files:
 - The Hisilicon Hip06/D03 is the latest server platform
   from Huawei/Hisilicon, and follows the Hip05/D02 platform.
 - Rockchip RK3399 follows the 32-bit RK3288 that is popular
   in low-end Chromebooks and the 64-bit RK3368 that is mainly
   found in chinese Android TV boxes.
 
 The 96Boards HiKey based on the Hisilicon Hi6220 (Kirin 620)
 gets a long-awaited overhaul with a lot of devices enabled in
 the DT, so it should be much more usable with a mainline kernel
 now. See also
 https://plus.google.com/111524780435806926688/posts/PeGb2VsNhJd
 
 A lot of work went into enabling new device drivers on existing
 machines, but we also have a couple of new commercially
 available machines:
 
 - Google Pixel C laptop based on Tegra210
 - Hardkernel Odroid C2 Based on Amlogic Meson GXBB (S905)
 - Geekbuying GeekBox based on Rockchip RK3368
 
 And finally, a couple of reference or development platforms
 that are not end-user platforms but are used for trying out
 the respective SoC platforms:
 
 - Amlogic Meson GXBB P200 and P201 development systems
 - NXP Layerscape 1043A QDS development board
 - Hisilicon Hip06 D03 server board, as mentioned above
 - LG1312 Reference Design
 - RK3399 Evaluation Board
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "We continue ramping up platform support for 64-bit ARM machines, with
  111 individual non-merge changesets touching 21 platforms.

  The LG1312 platform is completely new and is the first ARM platform by
  LG that we support in the mainline kernel.  Two other SoCs got added
  that are updated versions of existing SoC families, so the port mainly
  consists of new dts files:

   - The Hisilicon Hip06/D03 is the latest server platform from
     Huawei/Hisilicon, and follows the Hip05/D02 platform.

   - Rockchip RK3399 follows the 32-bit RK3288 that is popular in
     low-end Chromebooks and the 64-bit RK3368 that is mainly found in
     chinese Android TV boxes.

  The 96Boards HiKey based on the Hisilicon Hi6220 (Kirin 620) gets a
  long-awaited overhaul with a lot of devices enabled in the DT, so it
  should be much more usable with a mainline kernel now.  See also

     https://plus.google.com/111524780435806926688/posts/PeGb2VsNhJd

  A lot of work went into enabling new device drivers on existing
  machines, but we also have a couple of new commercially available
  machines:

   - Google Pixel C laptop based on Tegra210
   - Hardkernel Odroid C2 Based on Amlogic Meson GXBB (S905)
   - Geekbuying GeekBox based on Rockchip RK3368

  And finally, a couple of reference or development platforms that are
  not end-user platforms but are used for trying out the respective SoC
  platforms:

   - Amlogic Meson GXBB P200 and P201 development systems
   - NXP Layerscape 1043A QDS development board
   - Hisilicon Hip06 D03 server board, as mentioned above
   - LG1312 Reference Design
   - RK3399 Evaluation Board"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (104 commits)
  arm64: dts: marvell: add XOR node for Armada 3700 SoC
  dt-bindings: document rockchip rk3399-evb board
  arm64: dts: rockchip: add dts file for RK3399 evaluation board
  arm64: dts: rockchip: add core dtsi file for RK3399 SoCs
  dt-bindings: rockchip-dw-mshc: add description for rk3399
  arm64: dts: marvell: Use a SoC-specific compatible for xHCI on Armada37xx
  arm64: dts: marvell: Rename armada-37xx USB node
  arm64: dts: marvell: Clean up armada-3720-db
  Documentation: arm64: Add Hisilicon Hip06 D03 dts binding
  arm64: dts: Add initial dts for Hisilicon Hip06 D03 board
  arm64: dts: hip05: Add nor flash support
  arm64: dts: hip05: fix its node without msi-cells
  arm64: dts: r8a7795: Don't disable referenced optional clocks
  arm64: dts: salvator-x: populate EXTALR
  arm64: dts: r8a7795: enable PCIe on Salvator-X
  arm64: dts: r8a7795: Add PCIe nodes
  arm64: tegra: Add IOMMU node to GM20B on Tegra210
  arm64: tegra: Add reference clock to GM20B on Tegra210
  dt-bindings: Add documentation for GM20B GPU
  dt-bindings: gk20a: Document iommus property
  ...
2016-05-18 12:58:39 -07:00
Masahiro Yamada
fb89cf36b6 arm64: dts: uniphier: add reference clock node for PH1-LD20
Add a master clock node generated by a 25MHz crystal oscillator.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-04-25 22:57:54 +02:00
Masahiro Yamada
b455f0a1cc arm64: dts: uniphier: use Daughter board on PH1-LD20 reference board
Include the development base board, which is equipped with some
devices such as EEPROM.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-04-25 22:57:04 +02:00
Masahiro Yamada
56896ef5b9 arm64: dts: uniphier: fix I2C nodes of PH1-LD20
The I2C hardware blocks on this SoC are connected as follows:

  I2C0: external connection
  I2C1: external connection
  I2C2: internal connection
  I2C3: external connection
  I2C4: external connection
  I2C5: internal connection
  I2C6: no connection (not accessible)

Delete pinctrl from Ch2, add pinctrl to Ch4, and remove the Ch6 node.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-04-23 22:08:35 +02:00
Masahiro Yamada
14bae133b8 ARM: dts: uniphier: rework UniPhier System Bus nodes
During the review process of the UniPhier System Bus driver
(drivers/bus/uniphier.c), the current binding of the System Bus
Controller turned out to be no good.  In order to make the driver
really usable, we have to switch over to the new binding defined by
Documentation/devicetree/bindings/bus/uniphier-system-bus.txt.
The old binding will be still supported for a while to keep the
backward compatibility.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-03-18 17:37:52 +01:00
Masahiro Yamada
5c5154e429 ARM: dts: uniphier: factor out ranges property of support card
This property is used in common by several boards.  Move it to the
common place (uniphier-support-card.dtsi).  If necessary, each board
can still override the property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-03-18 17:37:45 +01:00
Masahiro Yamada
65e43389c3 arm64: dts: uniphier: rename PH1-LD10 to PH1-LD20
Due to the company's awful projecting, this chip has been renamed to
PH1-LD20.  It has not been shipped yet, this change would have no
impact on our customers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-03-18 17:37:36 +01:00
Masahiro Yamada
e1a0ebc8d8 arm64: dts: uniphier: add PH1-LD10 SoC/board support
This is the first ARMv8 SoC from Socionext Inc.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2015-12-21 20:38:24 -08:00