Commit Graph

9 Commits

Author SHA1 Message Date
Jeeja KP
d7b188131c ASoC: Intel: Skylake: Update for ssp node index in copier cfg
DSP firmware has interface change for SSP node index structure.
New FW interface removes the dual_mono field and adds 4 bits for
TDM slot group index. This patch updates the ssp dma to align with
the DSP firmware structure.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-24 01:31:34 +09:00
Vinod Koul
3af36706ff ASoC: Intel: Skylake: Add topology core init and handlers
The SKL driver does not code DSP topology in driver. It uses the
newly added ASoC topology core to parse the topology information
(controls, widgets and map) from topology binary.
Each topology element passed private data which contains
information that driver used to identify the module instance
within firmware and send IPCs for that module to DSP firmware
along with parameters.
This patch adds init routine to invoke topology load and callback
for topology creation.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-07 16:04:14 +01:00
Vinod Koul
cfb0a87383 ASoC: Intel: Skylake: Add FE and BE hw_params handling
For FE and BE, the PCM parameters come from FE and BE hw_params
values passed. For a FE we convert the FE params to DSP expected
module format and pass to DSP. For a BE we need to find the
gateway settings (i2s/PDM) to be applied. These are queried from
NHLT table and applied.

Further for BE based on direction the settings are applied as
either source or destination parameters.

These helpers here allow the format to be calculated and queried
as per firmware format.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-07 15:30:16 +01:00
Vinod Koul
d93f8e550f ASoC: Intel: Skylake: add DSP platform widget event handlers
The Skylake driver topology model tries to model the firmware
rule for pipeline and module creation.
The creation rule is:
 - Create Pipe
 - Add modules to Pipe
 - Connect the modules (bind)
 - Start the pipes

Similarly destroy rule is:
 - Stop the pipe
 - Disconnect it (unbind)
 - Delete the pipe

In driver we use Mixer, as there will always be ONE mixer in a
pipeline to model a pipe. The modules in pipe are modelled as PGA
widgets.  The DAPM sequencing rules (mixer and then PGA) are used
to create the sequence DSP expects as depicted above, and then
widget handlers for PMU and PMD events help in that.

This patch adds widget event handlers for PRE/POST PMU and
PRE/POST PMD event for mixer and pga modules.  These event
handlers invoke pipeline creation, destroy, module creation,
module bind, unbind and pipeline bind unbind

Event handler sequencing is implement to target the DSP FW
sequence expectations to enable path from source to sink pipe for
Playback/Capture.

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-07 15:30:15 +01:00
Jeeja KP
e4e2d2f452 ASoC: Intel: Skylake: Add pipe and modules handlers
SKL driver needs to instantiate pipelines and modules in the DSP.
The topology in the DSP is modelled as DAPM graph with a PGA
representing a module instance and mixer representing a pipeline
for a group of modules along with the mixer itself.

Here we start adding building block for handling these. We add
resource checks (memory/compute) for pipelines, find the modules
in a pipeline, init modules in a pipe and lastly bind/unbind
modules in a pipe These will be used by pipe event handlers in
subsequent patches

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-10-07 15:30:15 +01:00
Jeeja KP
c9b1e834bc ASoC: Intel: Skylake: Add pipe management helpers
To manage DSP we need to create processing pipeline and on cleanup destroy
them. So we add create and destroy routines for pipelines The pipelines need
to to be executed so we add pipeline run and stop routines
All these send required IPCs to DSP using IPC routines added earlier

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-07 14:26:03 +01:00
Jeeja KP
beb73b266a ASoC: Intel: Skylake: Add DSP module init and binding routines
A module needs to be instantiated and then connected with other modules. On
cleanup we need to disconnect the module.
This is achieved by helpers module init, bind and unbind which are added
here

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-07 14:26:02 +01:00
Hardik T Shah
a0ffe48bb5 ASoC: Intel: Skylake: Add helpers for SRC and converter modules
SRC and converter modules are required to do frequency and channel
conversion in DSP. Both take base module configuration and additional SRC
and converter parameters. The helpers here are added to calculate the values
for these modules

Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-07 14:26:02 +01:00
Jeeja KP
23db472bba ASoC: Intel: Skylake: Add helpers for DSP module configuration
This adds helper functions to calculate parameters required for base module
format and copier module. A generic module is modelled by base module.
Copier module is responsible for getting/sending data to FE (host DMAs) and
BE (link HDA DMA, SSP, PDM)
This also ads module pin management helpers which help in finding pins to
use or freeing them up

Signed-off-by: Jeeja KP <jeeja.kp@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
2015-08-07 14:26:02 +01:00