Commit Graph

296 Commits

Author SHA1 Message Date
Yijing Wang
26914233b1 PCI: mvebu: Save MSI controller in pci_sys_data
Save MSI controller in pci_sys_data instead of assigning MSI controller
pointer to every PCI bus in .add_bus().

Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-21 09:34:15 -07:00
Yijing Wang
7840cba885 PCI: rcar: Save MSI controller in pci_sys_data
Save MSI controller in pci_sys_data instead of assigning MSI controller
pointer to every PCI bus in .add_bus().

[bhelgaas: use struct rcar_msi.chip, not ctrl]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-21 09:34:07 -07:00
Yijing Wang
0815f957e1 PCI: designware: Save MSI controller in pci_sys_data
Save MSI controller in pci_sys_data instead of assigning MSI controller
pointer to every PCI bus in .add_bus().

[bhelgaas: use dw_pcie_msi_chip, not dw_pcie_msi_controller]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-21 09:33:58 -07:00
Yijing Wang
7ec725b2d5 PCI: tegra: Save MSI controller in pci_sys_data
Save MSI controller in pci_sys_data instead of assigning MSI controller
pointer to every PCI bus in .add_bus().

[bhelgaas: use struct tegra_msi.chip, not ctrl]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-21 09:33:45 -07:00
Bjorn Helgaas
35437e3d9b Merge branches 'pci/host-designware', 'pci/host-dra7xx', 'pci/host-exynos', 'pci/host-generic', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-layerscape', 'pci/host-mvebu', 'pci/host-rcar', 'pci/host-spear' and 'pci/host-tegra' into next
* pci/host-designware:
  PCI: designware: Add a blank line after declarations

* pci/host-dra7xx:
  PCI: dra7xx: Add __init annotation to dra7xx_add_pcie_port()
  PCI: dra7xx: Rename add_pcie_port() to dra7xx_add_pcie_port()

* pci/host-exynos:
  PCI: exynos: Remove unnecessary return statement
  PCI: exynos: Add exynos prefix to add_pcie_port()/pcie_init()

* pci/host-generic:
  PCI: generic: Convert to DT resource parsing API
  PCI: generic: Allocate config space windows after limiting bus number range

* pci/host-imx6:
  PCI: imx6: Use tabs for indentation

* pci/host-keystone:
  PCI: keystone: Remove unnecessary OOM message
  PCI: keystone: Make ks_dw_pcie_msi_domain_ops static

* pci/host-layerscape:
  PCI: layerscape: Add Freescale Layerscape PCIe driver

* pci/host-mvebu:
  PCI: mvebu: Add a blank line after declarations

* pci/host-rcar:
  PCI: rcar: Make rcar_pci static

* pci/host-spear:
  PCI: spear: Remove unnecessary OOM message
  PCI: spear: Add __init annotation to spear13xx_add_pcie_port()
  PCI: spear: Rename add_pcie_port(), pcie_init() to spear13xx_add_pcie_port(), etc.

* pci/host-tegra:
  PCI: tegra: Add Kconfig help text
  PCI: tegra: Do not build on 64-bit ARM
2014-11-15 07:26:12 -07:00
Thierry Reding
6b1c4d7674 PCI: tegra: Add Kconfig help text
Add a standard help text to the Kconfig entry for the Tegra PCIe host
controller driver.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-13 12:03:57 -07:00
Thierry Reding
4407308b73 PCI: tegra: Do not build on 64-bit ARM
32-bit and 64-bit ARM use very different infrastructure to register a PCI
host bridge.  The Tegra PCIe host controller driver currently only supports
the 32-bit ARM infrastructure, so prevent it from being built on 64-bit ARM
where it will break.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-13 12:03:28 -07:00
Jingoo Han
20f9ece101 PCI: spear: Remove unnecessary OOM message
The site-specific OOM messages are unnecessary, because they duplicate the
MM subsystem generic OOM message.  This patch fixes the following
checkpatch warning:

  WARNING: Possible unnecessary 'out of memory' message

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2014-11-13 10:55:39 -07:00
Jingoo Han
cf3a9d6bae PCI: mvebu: Add a blank line after declarations
This patch fixes the following checkpatch warning:

  WARNING: Missing a blank line after declarations

[bhelgaas: drop mvebu_pcie_add_bus() change because it's going away anyway]
Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
2014-11-13 10:53:02 -07:00
Jingoo Han
2c992f3779 PCI: designware: Add a blank line after declarations
This patch fixes the following checkpatch warning:

  WARNING: Missing a blank line after declarations

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-13 10:52:04 -07:00
Jingoo Han
bc512c5a8c PCI: exynos: Remove unnecessary return statement
This patch fixes the following checkpatch warning:

  WARNING: void function return statements are not generally useful

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-13 10:50:31 -07:00
Jingoo Han
d88a7ef99e PCI: imx6: Use tabs for indentation
This patch fixes the following checkpatch error:

  ERROR: code indent should use tabs where possible

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-13 10:48:20 -07:00
Jingoo Han
6670070742 PCI: keystone: Remove unnecessary OOM message
The site-specific OOM messages are unnecessary because they duplicate the
MM subsystem generic OOM message.  This patch fixes the following
checkpatch warning:

  WARNING: Possible unnecessary 'out of memory' message

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-13 10:44:02 -07:00
Duc Dang
336b5be2c5 PCI: xgene: Assign resources to bus before adding new devices
The X-Gene PCIe driver assumes pci_scan_root_bus() assigns resources as
proposed in [1].  But we dropped patch [1] because it would break some
architectures, which means the X-Gene PCIe driver is currently broken.

Add calls to scan the bus, assign resources, and add devices in the X-Gene
driver to fix this.

[bhelgaas: changelog]
[1] http://lkml.kernel.org/r/1412000971-9242-11-git-send-email-Liviu.Dudau@arm.com
Signed-off-by: Duc Dang <dhdang@apm.com>
Signed-off-by: Tanmay Inamdar <tinamdar@apm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-13 09:53:30 -07:00
Jingoo Han
e73044a069 PCI: dra7xx: Add __init annotation to dra7xx_add_pcie_port()
Add __init annotation to dra7xx_add_pcie_port(), because
dra7xx_add_pcie_port() is called only by dra7xx_pcie_probe() which is
marked __init.  This patch fixes a section mismatch warning:

WARNING: drivers/pci/host/built-in.o(.text.unlikely+0xcc): Section mismatch in reference from the function dra7xx_add_pcie_port() to the function .init.text:dw_pcie_host_init()

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-13 09:49:15 -07:00
Jingoo Han
992e7bd2be PCI: spear: Add __init annotation to spear13xx_add_pcie_port()
Add __init annotation to spear13xx_add_pcie_port(), because
spear13xx_add_pcie_port() is called only by spear13xx_pcie_probe(), which
is marked __init.  This fixes a section mismatch warning:

WARNING: drivers/pci/host/built-in.o(.text.unlikely+0x94): Section mismatch in reference from the function spear13xx_add_pcie_port() to the function .init.text:dw_pcie_host_init()

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2014-11-13 09:46:47 -07:00
Jingoo Han
a9875d83a0 PCI: spear: Rename add_pcie_port(), pcie_init() to spear13xx_add_pcie_port(), etc.
The add_pcie_port() and pcie_init() functions are SPEAr13xx-specific.  Add
spear13xx prefix to avoid collision in global name space.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2014-11-13 09:43:26 -07:00
Jingoo Han
23926c8dbd PCI: dra7xx: Rename add_pcie_port() to dra7xx_add_pcie_port()
The add_pcie_port() function is dra7xx-specific.  Add dra7xx prefix to
avoid collision in global name space.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
2014-11-13 09:41:21 -07:00
Minghuan Lian
62d0ff83c6 PCI: layerscape: Add Freescale Layerscape PCIe driver
Add support for Freescale Layerscape PCIe controller.  This driver re-uses
the Synopsis DesignWare core code.

[bhelgaas: add Kconfig dependency on CONFIG_ARM]
Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-11-13 09:31:52 -07:00
Yijing Wang
c2791b8069 PCI/MSI: Rename "struct msi_chip" to "struct msi_controller"
"msi_chip" isn't very descriptive, so rename it to "msi_controller".  That
tells a little more about what it does and is already used in device tree
bindings.

No functional change.

[bhelgaas: changelog, change *only* the struct name so it's reviewable]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-11-12 07:49:38 -07:00
Lorenzo Pieralisi
dbf9826d57 PCI: generic: Convert to DT resource parsing API
In order to consolidate DT configuration for PCI host controllers in the
kernel, a new API, of_pci_get_host_bridge_resources(), was developed to
allow parsing and assigning IO/BUS/MEM resources from DT, removing
duplicated code present in the majority of PCI host driver implementations.

Convert the existing PCI generic host controller driver to the new API.
Most of the code parsing ranges and creating resources is now delegated to
the of_pci_get_host_bridge_resources() API.

The PCI host controller code filters the resulting resource list and maps
IO space by using the newly introduced pci_ioremap_iospace() API.

New code supports only one IO resource per generic host controller, which
should cater for all existing host controller configurations.

[bhelgaas: changelog]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Will Deacon <will.deacon@arm.com>
2014-11-05 16:57:41 -07:00
Lorenzo Pieralisi
a5525b2403 PCI: generic: Allocate config space windows after limiting bus number range
The number of config space windows allocated for the host bridge depends on
how many bus numbers are below the bridge.  Instead of first allocating the
windows and then limiting the bus resource, this patch reshuffles the code
so that if any limitation is applied to the bus resource, it is taken into
account in the windows allocation.

[bhelgaas: changelog]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Will Deacon <will.deacon@arm.com>
2014-11-05 16:49:24 -07:00
Greg Kroah-Hartman
a8a93c6f99 Merge branch 'platform/remove_owner' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux into driver-core-next
Remove all .owner fields from platform drivers
2014-11-03 19:53:56 -08:00
Richard Zhu
a2fa6f64c2 PCI: imx6: Wait for clocks to stabilize after ref_en
For boards without a reset GPIO we skip the delay between enabling the
pcie_ref_clk and touching the RC registers for configuration.  This hangs
the system if there isn't a proper delay to ensure the clocks are settled
in the DW PCIe core.

Also iMX6Q always needs an additional 10us delay to make sure the reset is
propagated through the core, as we don't have an explicitly controlled
reset input on this SoC.

This fixes a problem with 3fce0e882f ("PCI: imx6: Delay enabling
reference clock for SS until it stabilizes"): the kernel doesn't boot on
systems that don't pass the PCI GPIO reset in the DTB.  This regression
affects mx6 nitrogen boards.

[bhelgaas: add regression info in changelog]
Fixes: 3fce0e882f ("PCI: imx6: Delay enabling reference clock for SS until it stabilizes")
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Richard Zhu <richard.zhu@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
2014-10-29 10:11:54 -06:00
Jingoo Han
3c70637f75 PCI: rcar: Make rcar_pci static
Make rcar_pci static because it is used only in this file.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
2014-10-23 10:07:58 -06:00
Jingoo Han
5ba8368b7a PCI: keystone: Make ks_dw_pcie_msi_domain_ops static
Make ks_dw_pcie_msi_domain_ops static because it is used only in this file.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Santosh Shilimkar<ssantosh@kernel.org>
2014-10-23 10:07:02 -06:00
Jingoo Han
70b3e89aaf PCI: exynos: Add exynos prefix to add_pcie_port()/pcie_init()
The add_pcie_port() and pcie_init() functions are Exynos-specific.  Add
exynos prefix to avoid collision in global name space.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-10-23 10:00:06 -06:00
Wolfram Sang
e27a5130ab pci: host: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:21:20 +02:00
Linus Torvalds
80213c03c4 PCI changes for the v3.18 merge window:
Enumeration
     - Check Vendor ID only for Config Request Retry Status (Rajat Jain)
     - Enable Config Request Retry Status when supported (Rajat Jain)
     - Add generic domain handling (Catalin Marinas)
     - Generate uppercase hex for modalias interface class (Ricardo Ribalda Delgado)
 
   Resource management
     - Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() (Yinghai Lu)
     - Increase IBM ipr SAS Crocodile BARs to at least system page size (Douglas Lehr)
 
   PCI device hotplug
     - Prevent NULL dereference during pciehp probe (Andreas Noever)
     - Move _HPP & _HPX handling into core (Bjorn Helgaas)
     - Apply _HPP to PCIe devices as well as PCI (Bjorn Helgaas)
     - Apply _HPP/_HPX to display devices (Bjorn Helgaas)
     - Preserve SERR & PARITY settings when applying _HPP/_HPX (Bjorn Helgaas)
     - Preserve MPS and MRRS settings when applying _HPP/_HPX (Bjorn Helgaas)
     - Apply _HPP/_HPX to all devices, not just hot-added ones (Bjorn Helgaas)
     - Fix wait time in pciehp timeout message (Yinghai Lu)
     - Add more pciehp Slot Control debug output (Yinghai Lu)
     - Stop disabling pciehp notifications during init (Yinghai Lu)
 
   MSI
     - Remove arch_msi_check_device() (Alexander Gordeev)
     - Rename pci_msi_check_device() to pci_msi_supported() (Alexander Gordeev)
     - Move D0 check into pci_msi_check_device() (Alexander Gordeev)
     - Remove unused kobject from struct msi_desc (Yijing Wang)
     - Remove "pos" from the struct msi_desc msi_attrib (Yijing Wang)
     - Add "msi_bus" sysfs MSI/MSI-X control for endpoints (Yijing Wang)
     - Use __get_cached_msi_msg() instead of get_cached_msi_msg() (Yijing Wang)
     - Use __read_msi_msg() instead of read_msi_msg() (Yijing Wang)
     - Use __write_msi_msg() instead of write_msi_msg() (Yijing Wang)
 
   Power management
     - Drop unused runtime PM support code for PCIe ports (Rafael J.  Wysocki)
     - Allow PCI devices to be put into D3cold during system suspend (Rafael J. Wysocki)
 
   AER
     - Add additional AER error strings (Gong Chen)
     - Make <linux/aer.h> standalone includable (Thierry Reding)
 
   Virtualization
     - Add ACS quirk for Solarflare SFC9120 & SFC9140 (Alex Williamson)
     - Add ACS quirk for Intel 10G NICs (Alex Williamson)
     - Add ACS quirk for AMD A88X southbridge (Marti Raudsepp)
     - Remove unused pci_find_upstream_pcie_bridge(), pci_get_dma_source() (Alex Williamson)
     - Add device flag helpers (Ethan Zhao)
     - Assume all Mellanox devices have broken INTx masking (Gavin Shan)
 
   Generic host bridge driver
     - Fix ioport_map() for !CONFIG_GENERIC_IOMAP (Liviu Dudau)
     - Add pci_register_io_range() and pci_pio_to_address() (Liviu Dudau)
     - Define PCI_IOBASE as the base of virtual PCI IO space (Liviu Dudau)
     - Fix the conversion of IO ranges into IO resources (Liviu Dudau)
     - Add pci_get_new_domain_nr() and of_get_pci_domain_nr() (Liviu Dudau)
     - Add support for parsing PCI host bridge resources from DT (Liviu Dudau)
     - Add pci_remap_iospace() to map bus I/O resources (Liviu Dudau)
     - Add arm64 architectural support for PCI (Liviu Dudau)
 
   APM X-Gene
     - Add APM X-Gene PCIe driver (Tanmay Inamdar)
     - Add arm64 DT APM X-Gene PCIe device tree nodes (Tanmay Inamdar)
 
   Freescale i.MX6
     - Probe in module_init(), not fs_initcall() (Lucas Stach)
     - Delay enabling reference clock for SS until it stabilizes (Tim Harvey)
 
   Marvell MVEBU
     - Fix uninitialized variable in mvebu_get_tgt_attr() (Thomas Petazzoni)
 
   NVIDIA Tegra
     - Make sure the PCIe PLL is really reset (Eric Yuen)
     - Add error path tegra_msi_teardown_irq() cleanup (Jisheng Zhang)
     - Fix extended configuration space mapping (Peter Daifuku)
     - Implement resource hierarchy (Thierry Reding)
     - Clear CLKREQ# enable on port disable (Thierry Reding)
     - Add Tegra124 support (Thierry Reding)
 
   ST Microelectronics SPEAr13xx
     - Pass config resource through reg property (Pratyush Anand)
 
   Synopsys DesignWare
     - Use NULL instead of false (Fabio Estevam)
     - Parse bus-range property from devicetree (Lucas Stach)
     - Use pci_create_root_bus() instead of pci_scan_root_bus() (Lucas Stach)
     - Remove pci_assign_unassigned_resources() (Lucas Stach)
     - Check private_data validity in single place (Lucas Stach)
     - Setup and clear exactly one MSI at a time (Lucas Stach)
     - Remove open-coded bitmap operations (Lucas Stach)
     - Fix configuration base address when using 'reg' (Minghuan Lian)
     - Fix IO resource end address calculation (Minghuan Lian)
     - Rename get_msi_data() to get_msi_addr() (Minghuan Lian)
     - Add get_msi_data() to pcie_host_ops (Minghuan Lian)
     - Add support for v3.65 hardware (Murali Karicheri)
     - Fold struct pcie_port_info into struct pcie_port (Pratyush Anand)
 
   TI Keystone
     - Add TI Keystone PCIe driver (Murali Karicheri)
     - Limit MRSS for all downstream devices (Murali Karicheri)
     - Assume controller is already in RC mode (Murali Karicheri)
     - Set device ID based on SoC to support multiple ports (Murali Karicheri)
 
   Xilinx AXI
     - Add Xilinx AXI PCIe driver (Srikanth Thokala)
     - Fix xilinx_pcie_assign_msi() return value test (Dan Carpenter)
 
   Miscellaneous
     - Clean up whitespace (Quentin Lambert)
     - Remove assignments from "if" conditions (Quentin Lambert)
     - Move PCI_VENDOR_ID_VMWARE to pci_ids.h (Francesco Ruggeri)
     - x86: Mark DMI tables as initialization data (Mathias Krause)
     - x86: Move __init annotation to the correct place (Mathias Krause)
     - x86: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst (Mathias Krause)
     - x86: Constify pci_mmcfg_probes[] array (Mathias Krause)
     - x86: Mark PCI BIOS initialization code as such (Mathias Krause)
     - Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters (Megan Kamiya)
     - Remove unnecessary variable in pci_add_dynid() (Tobias Klauser)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUNWmJAAoJEFmIoMA60/r8GncP/3uHRoBrnaF6pv+S1l1p3Fs/
 l1kKH91/IuAAU7VJX8pkNybFqx02topWmiVVXAzqvD01PcRLGCLjPbWl5h+y5/Ja
 CHZH33AwHAmm0kt4BrOSOeHTLJhAigly2zV3P4F8jRIgyaeMoGZ6Ko4tkQUpm21k
 +ohrOd4cxYkmzzCjKwsZZhKnyRNpae8FmTk3VQBPuN8DbhvFPrqo5/+GeAdSZTdS
 HZHpfl2HL4095aY7uBVsZqNkjQyl6SnWwjkjLnuI8q3qA3BLgDZE/Jr8F/MNuW1V
 y01JIjerFWMDFyBIkpg7moYnODy6oP3KvczwYdKGmqsJja+0MQvYhLTwD+R/yTQS
 SewJA0mL3T3EJEfnFYkCiaIX27xIwk/FxHfaKPN91xgx/QM7xCVZNrU2/dXjhoX1
 GqLKxOEaFHhWWTyT5Dj27I0ZcElzFZ3tIwvrHfs8y22oAuAlsAypaUgvUwRfL4CO
 hOj4ITZa0t041sYWqxCoGAA9Fdp8HMzNKKS5F4mhADz4Ad9v6uPCNv/s/RoxVsbm
 jhZOtPYJ0/iCA+kNVX563S8Z3VpfPI+7bBjcj2WKdzW+IlICvOKT+kvwL2Tv/rE7
 w0hrNsbkgGsYbPldMx7LwCavsUtYFuNj0zoU6vkhP2jk6O2Tn5VXDmjrXH0v3iHI
 v03vlUtre0bQ26fzDyLQ
 =4Zv1
 -----END PGP SIGNATURE-----

Merge tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:
 "The interesting things here are:

   - Turn on Config Request Retry Status Software Visibility.  This
     caused hangs last time, but we included a fix this time.
   - Rework PCI device configuration to use _HPP/_HPX more aggressively
   - Allow PCI devices to be put into D3cold during system suspend
   - Add arm64 PCI support
   - Add APM X-Gene host bridge driver
   - Add TI Keystone host bridge driver
   - Add Xilinx AXI host bridge driver

  More detailed summary:

  Enumeration
    - Check Vendor ID only for Config Request Retry Status (Rajat Jain)
    - Enable Config Request Retry Status when supported (Rajat Jain)
    - Add generic domain handling (Catalin Marinas)
    - Generate uppercase hex for modalias interface class (Ricardo Ribalda Delgado)

  Resource management
    - Add missing MEM_64 mask in pci_assign_unassigned_bridge_resources() (Yinghai Lu)
    - Increase IBM ipr SAS Crocodile BARs to at least system page size (Douglas Lehr)

  PCI device hotplug
    - Prevent NULL dereference during pciehp probe (Andreas Noever)
    - Move _HPP & _HPX handling into core (Bjorn Helgaas)
    - Apply _HPP to PCIe devices as well as PCI (Bjorn Helgaas)
    - Apply _HPP/_HPX to display devices (Bjorn Helgaas)
    - Preserve SERR & PARITY settings when applying _HPP/_HPX (Bjorn Helgaas)
    - Preserve MPS and MRRS settings when applying _HPP/_HPX (Bjorn Helgaas)
    - Apply _HPP/_HPX to all devices, not just hot-added ones (Bjorn Helgaas)
    - Fix wait time in pciehp timeout message (Yinghai Lu)
    - Add more pciehp Slot Control debug output (Yinghai Lu)
    - Stop disabling pciehp notifications during init (Yinghai Lu)

  MSI
    - Remove arch_msi_check_device() (Alexander Gordeev)
    - Rename pci_msi_check_device() to pci_msi_supported() (Alexander Gordeev)
    - Move D0 check into pci_msi_check_device() (Alexander Gordeev)
    - Remove unused kobject from struct msi_desc (Yijing Wang)
    - Remove "pos" from the struct msi_desc msi_attrib (Yijing Wang)
    - Add "msi_bus" sysfs MSI/MSI-X control for endpoints (Yijing Wang)
    - Use __get_cached_msi_msg() instead of get_cached_msi_msg() (Yijing Wang)
    - Use __read_msi_msg() instead of read_msi_msg() (Yijing Wang)
    - Use __write_msi_msg() instead of write_msi_msg() (Yijing Wang)

  Power management
    - Drop unused runtime PM support code for PCIe ports (Rafael J.  Wysocki)
    - Allow PCI devices to be put into D3cold during system suspend (Rafael J. Wysocki)

  AER
    - Add additional AER error strings (Gong Chen)
    - Make <linux/aer.h> standalone includable (Thierry Reding)

  Virtualization
    - Add ACS quirk for Solarflare SFC9120 & SFC9140 (Alex Williamson)
    - Add ACS quirk for Intel 10G NICs (Alex Williamson)
    - Add ACS quirk for AMD A88X southbridge (Marti Raudsepp)
    - Remove unused pci_find_upstream_pcie_bridge(), pci_get_dma_source() (Alex Williamson)
    - Add device flag helpers (Ethan Zhao)
    - Assume all Mellanox devices have broken INTx masking (Gavin Shan)

  Generic host bridge driver
    - Fix ioport_map() for !CONFIG_GENERIC_IOMAP (Liviu Dudau)
    - Add pci_register_io_range() and pci_pio_to_address() (Liviu Dudau)
    - Define PCI_IOBASE as the base of virtual PCI IO space (Liviu Dudau)
    - Fix the conversion of IO ranges into IO resources (Liviu Dudau)
    - Add pci_get_new_domain_nr() and of_get_pci_domain_nr() (Liviu Dudau)
    - Add support for parsing PCI host bridge resources from DT (Liviu Dudau)
    - Add pci_remap_iospace() to map bus I/O resources (Liviu Dudau)
    - Add arm64 architectural support for PCI (Liviu Dudau)

  APM X-Gene
    - Add APM X-Gene PCIe driver (Tanmay Inamdar)
    - Add arm64 DT APM X-Gene PCIe device tree nodes (Tanmay Inamdar)

  Freescale i.MX6
    - Probe in module_init(), not fs_initcall() (Lucas Stach)
    - Delay enabling reference clock for SS until it stabilizes (Tim Harvey)

  Marvell MVEBU
    - Fix uninitialized variable in mvebu_get_tgt_attr() (Thomas Petazzoni)

  NVIDIA Tegra
    - Make sure the PCIe PLL is really reset (Eric Yuen)
    - Add error path tegra_msi_teardown_irq() cleanup (Jisheng Zhang)
    - Fix extended configuration space mapping (Peter Daifuku)
    - Implement resource hierarchy (Thierry Reding)
    - Clear CLKREQ# enable on port disable (Thierry Reding)
    - Add Tegra124 support (Thierry Reding)

  ST Microelectronics SPEAr13xx
    - Pass config resource through reg property (Pratyush Anand)

  Synopsys DesignWare
    - Use NULL instead of false (Fabio Estevam)
    - Parse bus-range property from devicetree (Lucas Stach)
    - Use pci_create_root_bus() instead of pci_scan_root_bus() (Lucas Stach)
    - Remove pci_assign_unassigned_resources() (Lucas Stach)
    - Check private_data validity in single place (Lucas Stach)
    - Setup and clear exactly one MSI at a time (Lucas Stach)
    - Remove open-coded bitmap operations (Lucas Stach)
    - Fix configuration base address when using 'reg' (Minghuan Lian)
    - Fix IO resource end address calculation (Minghuan Lian)
    - Rename get_msi_data() to get_msi_addr() (Minghuan Lian)
    - Add get_msi_data() to pcie_host_ops (Minghuan Lian)
    - Add support for v3.65 hardware (Murali Karicheri)
    - Fold struct pcie_port_info into struct pcie_port (Pratyush Anand)

  TI Keystone
    - Add TI Keystone PCIe driver (Murali Karicheri)
    - Limit MRSS for all downstream devices (Murali Karicheri)
    - Assume controller is already in RC mode (Murali Karicheri)
    - Set device ID based on SoC to support multiple ports (Murali Karicheri)

  Xilinx AXI
    - Add Xilinx AXI PCIe driver (Srikanth Thokala)
    - Fix xilinx_pcie_assign_msi() return value test (Dan Carpenter)

  Miscellaneous
    - Clean up whitespace (Quentin Lambert)
    - Remove assignments from "if" conditions (Quentin Lambert)
    - Move PCI_VENDOR_ID_VMWARE to pci_ids.h (Francesco Ruggeri)
    - x86: Mark DMI tables as initialization data (Mathias Krause)
    - x86: Move __init annotation to the correct place (Mathias Krause)
    - x86: Mark constants of pci_mmcfg_nvidia_mcp55() as __initconst (Mathias Krause)
    - x86: Constify pci_mmcfg_probes[] array (Mathias Krause)
    - x86: Mark PCI BIOS initialization code as such (Mathias Krause)
    - Parenthesize PCI_DEVID and PCI_VPD_LRDT_ID parameters (Megan Kamiya)
    - Remove unnecessary variable in pci_add_dynid() (Tobias Klauser)"

* tag 'pci-v3.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (109 commits)
  arm64: dts: Add APM X-Gene PCIe device tree nodes
  PCI: Add ACS quirk for AMD A88X southbridge devices
  PCI: xgene: Add APM X-Gene PCIe driver
  PCI: designware: Remove open-coded bitmap operations
  PCI/MSI: Remove unnecessary temporary variable
  PCI/MSI: Use __write_msi_msg() instead of write_msi_msg()
  MSI/powerpc: Use __read_msi_msg() instead of read_msi_msg()
  PCI/MSI: Use __get_cached_msi_msg() instead of get_cached_msi_msg()
  PCI/MSI: Add "msi_bus" sysfs MSI/MSI-X control for endpoints
  PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
  PCI/MSI: Remove unused kobject from struct msi_desc
  PCI/MSI: Rename pci_msi_check_device() to pci_msi_supported()
  PCI/MSI: Move D0 check into pci_msi_check_device()
  PCI/MSI: Remove arch_msi_check_device()
  irqchip: armada-370-xp: Remove arch_msi_check_device()
  PCI/MSI/PPC: Remove arch_msi_check_device()
  arm64: Add architectural support for PCI
  PCI: Add pci_remap_iospace() to map bus I/O resources
  of/pci: Add support for parsing PCI host bridge resources from DT
  of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
  ...

Conflicts:
	arch/arm64/boot/dts/apm-storm.dtsi
2014-10-09 15:03:49 -04:00
Bjorn Helgaas
f92d9ee3ab Merge branch 'pci/host-xgene' into next
* pci/host-xgene:
  arm64: dts: Add APM X-Gene PCIe device tree nodes
  PCI: xgene: Add APM X-Gene PCIe driver

Conflicts:
	drivers/pci/host/Kconfig
	drivers/pci/host/Makefile
2014-10-06 09:59:15 -06:00
Bjorn Helgaas
b9c9c2558b Merge branch 'pci/host-designware' into next
* pci/host-designware:
  PCI: designware: Remove open-coded bitmap operations
  PCI: designware: Setup and clear exactly one MSI at a time

Conflicts:
	drivers/pci/host/pcie-designware.c
2014-10-01 16:45:01 -06:00
Tanmay Inamdar
5f6b6ccdbe PCI: xgene: Add APM X-Gene PCIe driver
Add the AppliedMicro X-Gene SOC PCIe host controller driver.  The X-Gene
PCIe controller supports up to 8 lanes and GEN3 speed.  The X-Gene SOC
supports up to 5 PCIe ports.

[bhelgaas: folded in MAINTAINERS and bindings updates]
Tested-by: Ming Lei <ming.lei@canonical.com>
Tested-by: Dann Frazier <dann.frazier@canonical.com>
Signed-off-by: Tanmay Inamdar <tinamdar@apm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Liviu Dudau <Liviu.Dudau@arm.com> (driver)
2014-10-01 13:01:35 -06:00
Lucas Stach
c8df6ac945 PCI: designware: Remove open-coded bitmap operations
Replace them by using the standard kernel bitmap ops.  No functional
change, but makes the code a lot cleaner.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
2014-10-01 12:40:21 -06:00
Bjorn Helgaas
359c660e99 Merge branch 'pci/msi' into next
* pci/msi:
  PCI/MSI: Remove unnecessary temporary variable
  PCI/MSI: Use __write_msi_msg() instead of write_msi_msg()
  MSI/powerpc: Use __read_msi_msg() instead of read_msi_msg()
  PCI/MSI: Use __get_cached_msi_msg() instead of get_cached_msi_msg()
  PCI/MSI: Add "msi_bus" sysfs MSI/MSI-X control for endpoints
  PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
  PCI/MSI: Remove unused kobject from struct msi_desc
  PCI/MSI: Rename pci_msi_check_device() to pci_msi_supported()
  PCI/MSI: Move D0 check into pci_msi_check_device()
  PCI/MSI: Remove arch_msi_check_device()
  irqchip: armada-370-xp: Remove arch_msi_check_device()
  PCI/MSI/PPC: Remove arch_msi_check_device()

Conflicts:
	drivers/pci/host/pcie-designware.c
2014-10-01 12:31:46 -06:00
Bjorn Helgaas
07a7cbd3b8 Merge branch 'pci/host-generic' into next
* pci/host-generic:
  arm64: Add architectural support for PCI
  PCI: Add pci_remap_iospace() to map bus I/O resources
  of/pci: Add support for parsing PCI host bridge resources from DT
  of/pci: Add pci_get_new_domain_nr() and of_get_pci_domain_nr()
  PCI: Add generic domain handling
  of/pci: Fix the conversion of IO ranges into IO resources
  of/pci: Move of_pci_range_to_resource() to of/address.c
  ARM: Define PCI_IOBASE as the base of virtual PCI IO space
  of/pci: Add pci_register_io_range() and pci_pio_to_address()
  asm-generic/io.h: Fix ioport_map() for !CONFIG_GENERIC_IOMAP

Conflicts:
	drivers/pci/host/pci-tegra.c
2014-10-01 12:31:23 -06:00
Yijing Wang
48c3c38f00 PCI/MSI: Remove "pos" from the struct msi_desc msi_attrib
"msi_attrib.pos" is only used for MSI (not MSI-X), and we already cache the
MSI capability offset in "dev->msi_cap".

Remove "pos" from the struct msi_attrib and use "dev->msi_cap" directly.

[bhelgaas: changelog, fix whitespace]
Signed-off-by: Yijing Wang <wangyijing@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-10-01 12:21:23 -06:00
Liviu Dudau
0b0b0893d4 of/pci: Fix the conversion of IO ranges into IO resources
The ranges property for a host bridge controller in DT describes the
mapping between the PCI bus address and the CPU physical address.  The
resources framework however expects that the IO resources start at a pseudo
"port" address 0 (zero) and have a maximum size of IO_SPACE_LIMIT.  The
conversion from PCI ranges to resources failed to take that into account,
returning a CPU physical address instead of a port number.

Also fix all the drivers that depend on the old behaviour by fetching the
CPU physical address based on the port number where it is being needed.

Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Thierry Reding <thierry.reding@gmail.com>
CC: Simon Horman <horms@verge.net.au>
CC: Catalin Marinas <catalin.marinas@arm.com>
2014-09-30 17:08:40 -06:00
Lucas Stach
91f8ae823f PCI: designware: Setup and clear exactly one MSI at a time
The setup_irq function is supposed to set up exactly one MSI IRQ.  Multiple
IRQ setup is handled differently, to respect the choices made by the upper
layers.

Also only clear one MSI IRQ at a time; the PCI core will call into this
function multiple times if it has to tear down more than one MSI IRQ.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
2014-09-30 15:08:58 -06:00
Bjorn Helgaas
1104528bc7 Merge branch 'pci/host-designware' into next
* pci/host-designware:
  PCI: designware: Add get_msi_data() to pcie_host_ops
  PCI: designware: Rename get_msi_data() to get_msi_addr()
  PCI: designware: Fix IO resource end address calculation
  PCI: designware: Fix configuration base address when using 'reg'
  PCI: designware: Use NULL instead of false

[bhelgaas: Fixup keystone for "PCI: designware: Rename get_msi_data() to
get_msi_addr()"]
2014-09-29 13:24:24 -06:00
Bjorn Helgaas
b1bf295778 Merge branches 'pci/host-mvebu' and 'pci/host-spear' into next
* pci/host-mvebu:
  PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr()

* pci/host-spear:
  PCI: spear: Pass config resource through reg property
2014-09-25 13:51:55 -06:00
Minghuan Lian
24832b4de3 PCI: designware: Add get_msi_data() to pcie_host_ops
Add a struct pcie_host_ops .get_msi_data() method for platforms to return
their special MSI message data.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24 07:07:43 -06:00
Minghuan Lian
450e344e42 PCI: designware: Rename get_msi_data() to get_msi_addr()
The struct pcie_host_ops .get_msi_data() method returns the MSI message
address.  To accurately express its purpose, rename it to .get_msi_addr().

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24 07:04:39 -06:00
Minghuan Lian
0c61ea77cc PCI: designware: Fix IO resource end address calculation
End address should be equal to start_addr + size - 1.  Fix PCI IO resource
end address calculation.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24 07:04:01 -06:00
Minghuan Lian
ec98e9ab6f PCI: designware: Fix configuration base address when using 'reg'
The code has calculated cfg0_base and cfg1_base when parsing 'reg' or
'ranges' property of PCI DTS node, so remove duplicate calculation.  When
using 'reg', resource cfg is not used, so this code computed an incorrect
configuration base.

Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
2014-09-24 07:01:47 -06:00
Fabio Estevam
9f0dbe087b PCI: designware: Use NULL instead of false
of_get_address() expects pointers in the third and fourth parameters.

Pass NULL in order to fix the following sparse warnings:

  drivers/pci/host/pcie-designware.c:433:51: warning: Using plain integer as NULL pointer
  drivers/pci/host/pcie-designware.c:433:58: warning: Using plain integer as NULL pointer

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Jingoo Han <jg1.han@samsung.com>
2014-09-22 14:52:07 -06:00
Thomas Petazzoni
56fab6e189 PCI: mvebu: Fix uninitialized variable in mvebu_get_tgt_attr()
Geert Uytterhoeven reported a warning when building pci-mvebu:

  drivers/pci/host/pci-mvebu.c: In function 'mvebu_get_tgt_attr':
  drivers/pci/host/pci-mvebu.c:887:39: warning: 'rtype' may be used uninitialized in this function [-Wmaybe-uninitialized]
     if (slot == PCI_SLOT(devfn) && type == rtype) {
					 ^

And indeed, the code of mvebu_get_tgt_attr() may lead to the usage of rtype
when being uninitialized, even though it would only happen if we had
entries other than I/O space and 32 bits memory space.

This commit fixes that by simply skipping the current DT range being
considered, if it doesn't match the resource type we're looking for.

Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
CC: stable@vger.kernel.org	# v3.12+
2014-09-22 14:40:17 -06:00
Pratyush Anand
65aaae245a PCI: spear: Pass config resource through reg property
PCIe configuration space should be passed through reg property, rather than
through ranges property.  This patch does the correction for SPEAr13XX
SOCs.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-22 14:19:30 -06:00
Bjorn Helgaas
ef39ab79f7 Merge branches 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-tegra' and 'pci/host-xilinx' into next
* pci/host-designware:
  PCI: designware: Fold struct pcie_port_info into struct pcie_port

* pci/host-imx6:
  PCI: imx6: Delay enabling reference clock for SS until it stabilizes

* pci/host-keystone:
  PCI: keystone: Set device ID based on SoC to support multiple ports
  PCI: keystone: Assume controller is already in RC mode
  PCI: keystone: Limit MRSS for all downstream devices

* pci/host-tegra:
  PCI: tegra: Add Tegra124 support
  PCI: tegra: Make sure the PCIe PLL is really reset
  PCI: tegra: Fix extended configuration space mapping
  PCI: tegra: Clear CLKREQ# enable on port disable

* pci/host-xilinx:
  PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test
2014-09-22 12:31:10 -06:00
Linus Torvalds
b29f83aa8b PCI updates for v3.17:
Enumeration
     - Don't default exclusively to first video device (Bruno Prémont)
 
   PCI device hotplug
     - Remove "no hotplug settings from platform" warning (Bjorn Helgaas)
     - Add pci_ignore_hotplug() for VGA switcheroo (Bjorn Helgaas)
 
   Freescale i.MX6
     - Put LTSSM in "Detect" state before disabling (Lucas Stach)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUG7o9AAoJEFmIoMA60/r8hbYP/3gR3xHd2QKpkmBcM1lf1yiR
 osQQnAfRqEO4fzrpmOYrYbLIAOPwanK6Y36rmIYB+wHU2SUaffV7ZI9uW32shTud
 09+1N+OrSS6fwzVUWOuKsf1kv/jxpS+ic2fb+Qe1OXwJh5G+z1D9Kvd2EPLJdlgK
 ySyX4zSTrLni8CoclzREO7u82VVO5rTdvbujBxuvpOQTOdD5TFqV/uhb/y3gQz+u
 sG6IxUbdXsy4r24C6OnPrmmZ1Rk/lgCMyA+QSozc5Eu5PdGzcY9a6gcKlTnsbwBs
 qYLAb+/KCa3KgQh07NYmFfYdpoMZUXgSsEtD8gyvfJQHwUYwW8rsEMKxlSCQrzYr
 0OrpBSVTO6ta1r8SKOWtSYETQgPE3GUiJR1DuCyV+55RLZYp6Q8zH6dbgfWQbA/g
 R/kWHihR/tcD9YIlT99QrBppZtvG5nZ3y7aLSqdYYxEJqHE0tlbuxAu8hgwDf3Qp
 lKZJMyadLB1MS9lnrMj8DYqIOKbe62LOwcEYzhMJzaq8vCy+JWtjxOOgwBkT7P5v
 bhhYh3eqi5/MBONtw52V6RDUQId9vOLGHoiM5/akG4FFmWdhO9S0SbMBhAJyazKT
 n3IP5yj657XAi/fK939PUCQ3YuT5GqlCNcXDCqUzBZhGnt/Ln7LPmQI323519Lp4
 3vI3irFT0Fu2IFEBhc6l
 =xIYe
 -----END PGP SIGNATURE-----

Merge tag 'pci-v3.17-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fixes from Bjorn Helgaas:
 "These fix:

   - Boot video device detection on dual-GPU Apple systems
   - Hotplug fiascos on VGA switcheroo with radeon & nouveau drivers
   - Boot hang on Freescale i.MX6 systems
   - Excessive "no hotplug settings from platform" warnings

  In particular:

  Enumeration
    - Don't default exclusively to first video device (Bruno Prémont)

  PCI device hotplug
    - Remove "no hotplug settings from platform" warning (Bjorn Helgaas)
    - Add pci_ignore_hotplug() for VGA switcheroo (Bjorn Helgaas)

  Freescale i.MX6
    - Put LTSSM in "Detect" state before disabling (Lucas Stach)"

* tag 'pci-v3.17-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  vgaarb: Drop obsolete #ifndef
  vgaarb: Don't default exclusively to first video device with mem+io
  ACPIPHP / radeon / nouveau: Remove acpi_bus_no_hotplug()
  PCI: Remove "no hotplug settings from platform" warning
  PCI: Add pci_ignore_hotplug() to ignore hotplug events for a device
  PCI: imx6: Put LTSSM in "Detect" state before disabling it
  MAINTAINERS: Add Lucas Stach as co-maintainer for i.MX6 PCI driver
2014-09-19 10:50:30 -07:00
Dan Carpenter
f9dd0ce67d PCI: xilinx: Fix xilinx_pcie_assign_msi() return value test
We should be testing "hwirq" instead of "irq".  "irq" is unsigned so it's
never less than zero.  Also it's uninitialized.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Srikanth Thokala <sthokal@xilinx.com>
2014-09-16 17:41:52 -06:00
Thierry Reding
7f1f054b3f PCI: tegra: Add Tegra124 support
The PCIe controller on Tegra124 has two root ports that can be used in a
x4/x1 or x2/x1 configuration and can run at PCIe 2.0 link speeds (up to
5 GT/s).  The PHY programming has been moved into a separate controller, so
the driver now needs to request an external PHY referenced using the device
tree.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 16:55:49 -06:00
Eric Yuen
ec73276204 PCI: tegra: Make sure the PCIe PLL is really reset
Depending on the prior state of the controller, the PLL reset may not be
pulsed.  Clear the register bit and set it after a small delay to ensure
that the PLL is really reset.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Eric Yuen <eyuen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 16:55:33 -06:00
Peter Daifuku
8d41794c6f PCI: tegra: Fix extended configuration space mapping
The 16 chunks of 64 KiB that need to be stitched together to make up the
configuration space for one bus (1 MiB) are located 24 bits (== 16 MiB)
apart in physical address space.  This is determined by the start of the
extended register field (bits 24-27) in the physical mapping.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 16:55:10 -06:00
Thierry Reding
0d20d62192 PCI: tegra: Clear CLKREQ# enable on port disable
When a root port is disabled, disable the CLKREQ# signal if available.

Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 16:54:05 -06:00
Murali Karicheri
8665a482db PCI: keystone: Set device ID based on SoC to support multiple ports
K2E SoC has two PCI ports.  The SATA controller is connected to second PCI
port (port 1).  To support multiple port handling in Keystone PCI driver,
read the PCI device ID dynamically by iomap/read/unmap during probe and
save it in driver's private data and update it in host init code.  The PCI
device ID field in the RC's config space is not filled by default by the
hardware and has to be updated by the PCI driver by reading the same from
the SoC register indicated by reg index #2 in DT bindings.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 15:45:46 -06:00
Murali Karicheri
4455efc908 PCI: keystone: Assume controller is already in RC mode
Keystone PCI hardware supports both RC and EP modes and devcfg register has
bits to boot strap the device to either of these modes.  It seems proper to
add this functionality to the boot loader rather than in the driver as
device will be operating in either mode, not both any time.  Currently the
driver supports only RC mode and hence register configuration in the driver
is not needed and the driver can assume the hardware is in RC mode.

Also update the DT documentation accordingly.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-09-16 15:45:45 -06:00
Murali Karicheri
c15982dfa8 PCI: keystone: Limit MRSS for all downstream devices
Keystone PCIe controller has a limitation that memory read request size
must not exceed 256 bytes.  This is a hardware limitation.  Add a quirk to
force this limit on all downstream devices by updating MRRS.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-16 15:31:21 -06:00
Pratyush Anand
adf70fc087 PCI: designware: Fold struct pcie_port_info into struct pcie_port
The struct pcie_port_info doesn't contain any exclusive information
compared to other elements of struct pcie_port.  So, keeping a separate
structure does not seem very logical.  Therefore remove this struct and
embed its elements directly into struct pcie_port.

Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-05 17:48:54 -06:00
Tim Harvey
3fce0e882f PCI: imx6: Delay enabling reference clock for SS until it stabilizes
According to the IMX6 reference manuals, REF_SSP_EN (Reference clock enable
for SS function) must remain deasserted until the reference clock is
running at the appropriate frequency.

Delay enabling the reference clock for the SS function until it has
stabilized.  This prevents a high link failure rate (>5%) on certain IMX6
boards at various temperatures.

[bhelgaas: reword changelog slightly]
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
2014-09-05 11:16:41 -06:00
Bjorn Helgaas
a2351efeb3 Merge branches 'pci/misc', 'pci/pm', 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-tegra' and 'pci/host-xilinx' into next
* pci/misc:
  PCI/AER: Make <linux/aer.h> standalone includable
  PCI: Remove unnecessary variable in pci_add_dynid()

* pci/pm:
  PCI/PM: Allow PCI devices to be put into D3cold during system suspend
  PCI/PM: Drop unused runtime PM support code for PCIe ports

* pci/host-designware:
  PCI: designware: Check private_data validity in single place
  PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
  PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
  PCI: designware: Parse bus-range property from devicetree
  PCI: designware: Add support for v3.65 hardware

* pci/host-imx6:
  PCI: imx6: Probe in module_init(), not fs_initcall()
  PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
  PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
  PCI: designware: Parse bus-range property from devicetree
  PCI: imx6: Put LTSSM in "Detect" state before disabling it
  MAINTAINERS: Add Lucas Stach as co-maintainer for i.MX6 PCI driver
  PCI: designware: Add support for v3.65 hardware

* pci/host-keystone:
  PCI: keystone: Add TI Keystone PCIe driver
  PCI: designware: Add support for v3.65 hardware

* pci/host-tegra:
  PCI: tegra: Implement a proper resource hierarchy
  PCI: tegra: Add missing cleanup in error path and tegra_msi_teardown_irq()
  resources: Add device-managed request/release_resource()

* pci/host-xilinx:
  PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver

Conflicts:
	drivers/pci/host/Kconfig
	drivers/pci/host/Makefile
2014-09-05 10:57:20 -06:00
Lucas Stach
84a263f394 PCI: designware: Check private_data validity in single place
The driver had checks for this sprinkled all over.  As we call
sys_to_pcie() before every instance of this check, we can move the
check to this single location to make things clear.

Removing the statements after BUG[_ON]() is safe as the kernel is halted at
this point anyway.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-05 09:37:55 -06:00
Lucas Stach
61da50da90 PCI: imx6: Probe in module_init(), not fs_initcall()
This effectively reverts f216f57ffe ("PCI: imx6: Probe the PCIe in
fs_initcall()") as the resource allocation issue that prevented the driver
from working properly at module_initcall level is now fixed in
pcie-designware.c.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Richard Zhu <r65037@freescale.com>
2014-09-05 09:36:48 -06:00
Bjorn Helgaas
c346a54a6f Merge branch 'pci/host-designware' into pci/host-imx6
* pci/host-designware:
  PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
  PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
  PCI: designware: Parse bus-range property from devicetree
  PCI: designware: Add support for v3.65 hardware
2014-09-05 09:28:08 -06:00
Lucas Stach
8ddebc4103 PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init()
The pci_common_init_dev() call right before will already handle the device
resource allocation, so this call was a no-op.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-04 14:58:48 -06:00
Lucas Stach
92483df2ba PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus()
Use pci_create_root_bus() similar to other PCI host controller drivers.

The main problem with pci_scan_root_bus() is that it not only creates the
root bus, but also activates all devices on the bus.  This triggers PCI
device driver probe routines, which fail because resources haven't been
allocated.

To work around this we made sure that the host controller driver is probed
early and finishes resource allocation before any other device drivers are
registered.  Switching to pci_create_root_bus() allows us to get rid of
this special handling.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-04 14:58:48 -06:00
Lucas Stach
4f2ebe0059 PCI: designware: Parse bus-range property from devicetree
This allows to explicitly specify the covered bus numbers in the
devicetree, which will come in handy once we see a SoC with more than one
PCIe host controller instance.

Previously the driver relied on the behavior of pci_scan_root_bus() to fill
in a range of 0x00-0xff if no valid range was found.  We fall back to the
same range if no valid DT entry was found to keep backwards compatibility,
but now do it explicitly.

[bhelgaas: use %pR in error message to avoid duplication]
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
2014-09-04 14:58:48 -06:00
Murali Karicheri
0c4ffcfe1f PCI: keystone: Add TI Keystone PCIe driver
The Keystone PCIe controller is based on v3.65 version of the Designware
h/w.  Main differences are:

    1. No ATU support
    2. Legacy and MSI IRQ functions are implemented in application register
       space
    3. MSI interrupts are multiplexed over 8 IRQ lines to the Host side.

All of the application register space handing code is organized into
pci-keystone-dw.c and the functions are called from pci-keystone.c to
implement PCI controller driver.  Also add necessary DT documentation and
update the MAINTAINERS file for the driver.

[bhelgaas: spelling and whitespace fixes]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Mohit Kumar <mohit.kumar@st.com>
CC: Pratyush Anand <pratyush.anand@st.com>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
2014-09-04 14:58:21 -06:00
Thierry Reding
41534e5378 PCI: tegra: Implement a proper resource hierarchy
Currently the resource hierarchy generated from the PCIe host bridge is
completely flat:

    $ cat /proc/iomem
    00000000-00000fff : /pcie-controller@00003000/pci@1,0
    00003000-000037ff : pads
    00003800-000039ff : afi
    10000000-1fffffff : cs
    28000000-28003fff : r8169
    28004000-28004fff : r8169
    ...

The host bridge driver doesn't request all the resources that are used.
Windows allocated to each of the root ports aren't tracked, so there is no
way for resources allocated to individual devices to be matched up with the
correct parent resource by the PCI core.

This patch addresses this in two steps.  It first takes the union of all
regions associated with the PCIe host bridge (control registers, root port
registers, configuration space, I/O and prefetchable as well as non-
prefetchable memory regions) and uses it as the new root of the resource
hierarchy.

Subsequently, regions are allocated from within this new root resource so
that the resource tree looks much more like what's expected:

    # cat /proc/iomem
    00000000-3fffffff : /pcie-controller@00003000
      00000000-00000fff : /pcie-controller@00003000/pci@1,0
      00003000-000037ff : pads
      00003800-000039ff : afi
      10000000-1fffffff : cs
      20000000-27ffffff : non-prefetchable
      28000000-3fffffff : prefetchable
        28000000-280fffff : PCI Bus 0000:01
          28000000-28003fff : 0000:01:00.0
            28000000-28003fff : r8169
          28004000-28004fff : 0000:01:00.0
            28004000-28004fff : r8169
    ...

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-09-04 14:49:26 -06:00
Jisheng Zhang
019fa46ebc PCI: tegra: Add missing cleanup in error path and tegra_msi_teardown_irq()
We should call tegra_msi_free() to free the MSI bit if irq_create_mapping()
fails.  And we need to dispose the IRQ mapping during IRQ teardown.

[bhelgaas: made irqd_to_hwirq() change suggested by Thierry]
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
2014-09-04 14:49:24 -06:00
Lucas Stach
3e3e406e38 PCI: imx6: Put LTSSM in "Detect" state before disabling it
This fixes a boot hang observed when the bootloader already enabled the
PCIe link for its own use.  The fundamental problem is that Freescale
forgot to wire up the core reset, so software doesn't have a sane way to
get the core into a defined state.

According to the DW PCIe core reference manual, configuration of the core
may only happen when the LTSSM is disabled, so this is one of the first
things we need to do.  Apparently this isn't safe to do when the LTSSM is in
any state other than "detect" as we observe an instant machine hang when
trying to do so while the link is already up.

As a workaround, force LTSSM into detect state right before hitting the
disable switch.  There is still a race window because the LTSSM may
transition out of "detect" before we can disable it, but it's the best
we can do for now.

[bhelgaas: mention race window]
Link: http://lkml.kernel.org/r/1406830565-23450-3-git-send-email-l.stach@pengutronix.de
Reported-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
2014-09-04 07:32:21 -06:00
Srikanth Thokala
8961def568 PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP.

[bhelgaas: minor whitespace fixes]
Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2014-09-04 07:30:14 -06:00
Linus Torvalds
f16c15a0e0 PCI update for v3.17:
ST Microelectronics SPEAr13xx
     - Remove module option (Sachin Kamat)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUBgQ2AAoJEFmIoMA60/r8V7IP/2Tb5CXrGANsY31FCy5G2eJf
 Oe36ZBZjDWWgzdqNZXOH17J5Udi/MStuq/MKcGuK88lxEWxn0b3QMPy1ghsqIbWL
 Dh239GHdNudQV9TiSBb99jHP1LiYLVvwwbwSSJTYAT1U34uzLOHVtax5K2DKeklc
 1Qe95szTFeWhI9vu7oIhyAGEK7B9qOY2A32WRTqOlXesvvj9EL4mr9+IJiIza9Ns
 UKY3ycnvlLT3aeboCIabACqDLbPMuRmf8weARmUbUxejN16XKReBi+6lHtd38GmU
 18AaTATbGusmxSjnT4nhtU88DTXBtKagbF8eTGO1mi1ZZiTt6AHuBfNXJ3hy95si
 dsOy2CcU3DJjJGH+W1YKjDnUnZBhTQtof1UKS0o1oVzMy0ss5k8AWkZc1I8Ns/0h
 E9B6Jb9QT6W6v/v9hZYRRr9C8x0HqHqPAKCklCS+uKGO8dgEo5cShMrJ2gkPT6pz
 HJpEKAQKXR+GrZQabZOOjpWE6pBmZaaxoI45t5k316PTwqyIfYuHDbMZ2Ld2SRDq
 MuDcNqTaUsO9APl66JMhhEvBrvhXFDXPm3ukVjb4FLu90kh6BcwAvozTEz69nHfD
 6uuTXjJ7xlRJTsgK9CHuWMNoRuXi+WIzLY3ELqUK3yVhQJzuNceNBdTq6F58J46j
 +ns5JJBLUHnPsLcYb+MC
 =mEoh
 -----END PGP SIGNATURE-----

Merge tag 'pci-v3.17-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI fix from Bjorn Helgaas:
 "This fixes an ARM allmodconfig build problem:

  Remove module option for ST Microelectronics SPEAr13xx"

* tag 'pci-v3.17-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: spear: Remove module option
2014-09-03 08:45:48 -07:00
Murali Karicheri
b14a3d1784 PCI: designware: Add support for v3.65 hardware
The Keystone PCI controller is based on v3.65 DesignWare hardware.  This
version differs from newer versions of the hardware in functional areas
discussed below that make it necessary to change dw_pcie_host_init() to
support v3.65 based PCI controller.

    1. No support for ATU port.  Any ATU-specific resource handling code is
       to be bypassed for v3.65 h/w.

    2. MSI controller uses application space to implement MSI and 32 MSI
       interrupts are multiplexed over 8 IRQs to the host.  Hence the code
       to process MSI IRQ needs to be different.  This patch allows
       platform driver to provide its own irq_domain_ops ptr to
       irq_domain_add_linear() through an API callback from the DesignWare
       core driver.

    3. MSI interrupt generation requires EP to write to the RC's
       application register.  So enhance the driver to allow setup of
       inbound access to MSI IRQ register as a post scan bus API callback.

Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit KUMAR <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Jingoo Han <jg1.han@samsung.com>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
2014-09-02 17:25:41 -06:00
Linus Torvalds
f17a6f7859 PCI changes for v3.17 (part 3):
Marvell MVEBU
     - Remove ARCH_KIRKWOOD dependency (Andrew Lunn)
 
   NVIDIA Tegra
     - Add debugfs support (Thierry Reding)
 
   Synopsys DesignWare
     - Look for configuration space in 'reg', not 'ranges' (Kishon Vijay Abraham I)
     - Program ATU with untranslated address (Kishon Vijay Abraham I)
     - Add config access-related pcie_host_ops for v3.65 hardware (Murali Karicheri)
     - Add MSI-related pcie_host_ops for v3.65 hardware (Murali Karicheri)
 
   TI DRA7xx
     - Add TI DR7xx PCIe driver (Kishon Vijay Abraham I)
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJT8s0TAAoJEFmIoMA60/r853cQALnowzIdDhd0jq+IEpEq3PaO
 6e1fssstRbCWV+UoV09EgcRAGbehscnqGi+Ug3y0k+orqBE8R5mkUrJ13ddTlMrP
 WCYsxDWrAwiEI0R/YZ189yeWMyzzYWG+FtwR/iLAYZihz/edHz5P9Qb3gc+rg0S+
 /1hj50CrpXfUACQfyqCXSI6MNFyoSYo4z+BG9y/6A8/xg3nMRhxV93MjkurXW9Kn
 KqsF8xtKvhI//EFwGPGpN30pZdYoRxjbqcOd/XranZ9oZ7egQtV3NJyXzkXGkAwj
 rOR5usn9Cyi5MU0N79vPxxQYJXIJnPdHe5tpWXQoxOBTZ48crOP6aFRH6AFLteLW
 KLRuZKeKBdTXIJx5BIj+gEesnG8HAlv263+2Uzoyw7Qiz7dT6zl4+Z7YGonMxSAW
 HxhQhF8MPUfwBP738hIcM5L2pIJsDrHuhVi4Ff/ndqdFfnN6qx75avVO4l4gmjpl
 6RdsJnb8LjwTQpG8fQcojzEqmxrOSRei0fG8vmw0hCBQq23aNpe2TARBgxY8T3cO
 l7tBY4VyiJy7Q8zfhqGDKqv9QT4gQbwLZx+xZrbDgTkkt+dHCb6eqATbRqCpQ02X
 yuKAuj9eqFcZVscSNddRg1p/1iBaZHzpgWRUUXtJ7hBtWol9dFtFcnp+ibPPZy+4
 uZ3TmYr/Yb408FbUHBJB
 =XIzM
 -----END PGP SIGNATURE-----

Merge tag 'pci-v3.17-changes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI changes from Bjorn Helgaas:
 "Marvell MVEBU
    - Remove ARCH_KIRKWOOD dependency (Andrew Lunn)

  NVIDIA Tegra
    - Add debugfs support (Thierry Reding)

  Synopsys DesignWare
    - Look for configuration space in 'reg', not 'ranges' (Kishon Vijay Abraham I)
    - Program ATU with untranslated address (Kishon Vijay Abraham I)
    - Add config access-related pcie_host_ops for v3.65 hardware (Murali Karicheri)
    - Add MSI-related pcie_host_ops for v3.65 hardware (Murali Karicheri)

  TI DRA7xx
    - Add TI DR7xx PCIe driver (Kishon Vijay Abraham I)"

* tag 'pci-v3.17-changes-3' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci:
  PCI: designware: Add MSI-related pcie_host_ops for v3.65 hardware
  PCI: designware: Add config access-related pcie_host_ops for v3.65 hardware
  PCI: dra7xx: Add TI DRA7xx PCIe driver
  PCI: designware: Program ATU with untranslated address
  PCI: designware: Look for configuration space in 'reg', not 'ranges'
  PCI: tegra: Add debugfs support
  PCI: mvebu: Remove ARCH_KIRKWOOD dependency
2014-08-19 09:45:31 -05:00
Sachin Kamat
8d7004a690 PCI: spear: Remove module option
We get the following error when built as a module. Though the general fix
would be in this case to export the below mentioned symbols, considering
that dw_pcie_host_init() is marked with __init and other PCI drivers do not
support modular build, I have disabled building this driver as a module
too.

  ERROR: "dw_pcie_host_init" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_handle_msi_irq" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_msi_init" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_cfg_write" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_cfg_read" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_setup_rc" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  ERROR: "dw_pcie_link_up" [drivers/pci/host/pcie-spear13xx.ko] undefined!
  make[1]: *** [__modpost] Error 1
  make: *** [modules] Error 2

Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
2014-08-17 22:09:16 -06:00
Linus Torvalds
10c8e05620 ARM: SoC driver changes for 3.17
A handful of driver-related changes. We've had a bunch of them going in through
 other branches as well, so it's only a part of what we really have this release.
 
 Larger pieces are:
 
 * Removal of a now unused PWM driver for atmel
   - This includes AVR32 changes that have been appropriately acked.
 * Performance counter support for the arm CCN interconnect
 * OMAP mailbox driver cleanups and consolidation
 * PCI and SATA PHY drivers for SPEAr 13xx platforms
 * Redefinition (with backwards compatibility!) of PCI DT bindings for Tegra to
   better model regulators/power.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJT5DrJAAoJEIwa5zzehBx3wkkP/iwEfEK5mMon9KEe4DcKTKNq
 Z6xyWuMQNHKdfBFpABs6AsHQCKDc7KK6gN3+2zLLHEJ4XGDPZ2g2NaX3oRPJlaay
 BDK7rQfIZyi4tmbOnlEv1BDTYgirYBPMwk9RyNo/04Ug3W+Y67aSVo44zkNFBWaJ
 GbcX/zYsrsfvdawuQMW6V/A835s3Kq5Zhv1ikPr8gDDjswZRBAT6i7FYpBSHQ8K8
 bH6C1891Xit6rxXSLXJyrtM8CAet7PtLTqNr/IKdUaJnGD+fJm5EonxW+g8gvhN8
 gOEkm3nM60++kdDlzZCQVNr0m1+ih6NNCr6bDLO6rIRpAJM2O+YrN1rWuZaJOu1A
 pIvifk+wWHT+o52pXk8g9fK4n/ZJydK3IBzDePHMrIROOEiW5tLE3WA+u3NSfMfH
 WegMt9E2dcB+5gXPeejZ9gFbAHnh2S1oVTZfCYXtuOHrYiEU9U0FA3eRYvJEE2po
 k8sdiOn7Vc65O1QZ+xZNbLABpAHaye7X2evOJyhSutzHE/AtUvT4vuCAZ0tggXyD
 E1qVKngVW/NvcoFbwYeidq4bOVgiAEn3idZgF5gEq1mq7LzetXUQAcZAOQfLWHLQ
 RrXufS7Ez8pSCG74y0AFReVfQH2PgWHPqGUGj99NXgQauexc/vR1Hc5Iqb8liGNJ
 n6i8RqvvQ4KYcmHEXDIT
 =fsP6
 -----END PGP SIGNATURE-----

Merge tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver changes from Olof Johansson:
 "A handful of driver-related changes.  We've had a bunch of them going
  in through other branches as well, so it's only a part of what we
  really have this release.

  Larger pieces are:

   - Removal of a now unused PWM driver for atmel
     [ This includes AVR32 changes that have been appropriately acked ]
   - Performance counter support for the arm CCN interconnect
   - OMAP mailbox driver cleanups and consolidation
   - PCI and SATA PHY drivers for SPEAr 13xx platforms
   - Redefinition (with backwards compatibility!) of PCI DT bindings for
     Tegra to better model regulators/power"

Note: this merge also fixes up the semantic conflict with the new
calling convention for devm_phy_create(), see commit f0ed817638 ("phy:
core: Let node ptr of PHY point to PHY and not of PHY provider") that
came in through Greg's USB tree.

Semantic merge patch by Stephen Rothwell <sfr@canb.auug.org.au> through
the next tree.

* tag 'drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (38 commits)
  bus: arm-ccn: Fix error handling at event allocation
  mailbox/omap: add a parent structure for every IP instance
  mailbox/omap: remove the private mailbox structure
  mailbox/omap: consolidate OMAP mailbox driver
  mailbox/omap: simplify the fifo assignment by using macros
  mailbox/omap: remove omap_mbox_type_t from mailbox ops
  mailbox/omap: remove OMAP1 mailbox driver
  mailbox/omap: use devm_* interfaces
  bus: ARM CCN: add PERF_EVENTS dependency
  bus: ARM CCN PMU driver
  PCI: spear: Remove spear13xx_pcie_remove()
  PCI: spear: Fix Section mismatch compilation warning for probe()
  ARM: tegra: Remove legacy PCIe power supply properties
  PCI: tegra: Remove deprecated power supply properties
  PCI: tegra: Implement accurate power supply scheme
  ARM: SPEAr13xx: Update defconfigs
  ARM: SPEAr13xx: Add pcie and miphy DT nodes
  ARM: SPEAr13xx: Add bindings and dt node for misc block
  ARM: SPEAr13xx: Fix static mapping table
  phy: Add drivers for PCIe and SATA phy on SPEAr13xx
  ...
2014-08-08 11:34:32 -07:00
Linus Torvalds
44c916d58b ARM: SoC cleanups for 3.17
This merge window brings a good size of cleanups on various
 platforms. Among the bigger ones:
 
 * Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have
   lacked active support for quite a while, and after asking around nobody
   showed interest in keeping them around. If needed, they could be
   resurrected in the future but it's more likely that we would prefer
   reintroduction of them as DT and multiplatform-enabled platforms
   instead.
 * OMAP4 controller code register define diet. They defined a lot of registers
   that were never actually used, etc.
 * Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate)
   to drivers/soc so it can be shared with 64-bit code. This also converts them
   over to traditional driver models where possible.
 * Removal of legacy gpio-samsung driver, since the last users have been
   removed (moved to pinctrl)
 
 Plus a bunch of smaller changes for various platforms that sort of
 dissapear in the diffstat for the above. clps711x cleanups, shmobile
 header file refactoring/moves for multiplatform friendliness, some misc
 cleanups, etc.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJT5DYPAAoJEIwa5zzehBx37egQAIiatNiLLqZnfo3rwGADRz/a
 POfPovktj68aPcobyzoyhFtToMqGvi9PpysyFTIQD2HJFG+5BtiIAuqtg0875zDe
 EpBWgsfugrm0YktJWAtUerj60oAmNPbKfaEm1cOOWuM2lb2mV+QkRrwSTAgsqkT7
 927BzMXKKBRPOVLL0RYhoF8EXa0Eg8kCqAHP8fJrzVYkRp+UrZJDnGiUP1XmWJN+
 VXQMu5SEjcPMtqT7+tfX455RfREHJfBcJ1ZN/dPF8HMWDwClQG0lyc6hifh1MxwO
 8DjIZNkfZeKqgDqVyC17re7pc7p8md5HL8WXbrKpK0A9vQ5bRexbPHxcwJ1T/C2Y
 465H+st5XXbuzV1gbMwjK1/ycsH0tCyffckk8Yl/2e1Fs7GgPNbAELtTdl+5vV1Y
 xmDXkyo/9WlRM3LQ23IGKwW7VzN86EfWVuShssfro0fO7xDdb4OOYLdQI+4bCG+h
 ytQYun1vU32OEyNik5RVNQuZaMrv2c93a3bID4owwuPHPmYOPVUQaqnRX/0E51eA
 aHZYbk2GlUOV3Kq5aSS4iyLg1Yj+I9/NeH9U+A4nc+PQ5FlgGToaVSCuYuw4DqbP
 AAG+sqQHbkBMvDPobQz/yd1qZbAb4eLhGy11XK1t5S65rApWI55GwNXnvbyxqt8x
 wpmxJTASGxcfuZZgKXm7
 =gbcE
 -----END PGP SIGNATURE-----

Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Olof Johansson:
 "This merge window brings a good size of cleanups on various platforms.
  Among the bigger ones:

   - Removal of Samsung s5pc100 and s5p64xx platforms.  Both of these
     have lacked active support for quite a while, and after asking
     around nobody showed interest in keeping them around.  If needed,
     they could be resurrected in the future but it's more likely that
     we would prefer reintroduction of them as DT and
     multiplatform-enabled platforms instead.

   - OMAP4 controller code register define diet.  They defined a lot of
     registers that were never actually used, etc.

   - Move of some of the Tegra platform code (PMC, APBIO, fuse,
     powergate) to drivers/soc so it can be shared with 64-bit code.
     This also converts them over to traditional driver models where
     possible.

   - Removal of legacy gpio-samsung driver, since the last users have
     been removed (moved to pinctrl)

  Plus a bunch of smaller changes for various platforms that sort of
  dissapear in the diffstat for the above.  clps711x cleanups, shmobile
  header file refactoring/moves for multiplatform friendliness, some
  misc cleanups, etc"

* tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits)
  drivers: CCI: Correct use of ! and &
  video: clcd-versatile: Depend on ARM
  video: fix up versatile CLCD helper move
  MAINTAINERS: Add sdhci-st file to ARCH/STI architecture
  ARM: EXYNOS: Fix build breakge with PM_SLEEP=n
  MAINTAINERS: Remove Kirkwood
  ARM: tegra: Convert PMC to a driver
  soc/tegra: fuse: Set up in early initcall
  ARM: tegra: Always lock the CPU reset vector
  ARM: tegra: Setup CPU hotplug in a pure initcall
  soc/tegra: Implement runtime check for Tegra SoCs
  soc/tegra: fuse: fix dummy functions
  soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
  soc/tegra: Add efuse and apbmisc bindings
  soc/tegra: Add efuse driver for Tegra
  ARM: tegra: move fuse exports to soc/tegra/fuse.h
  ARM: tegra: export apb dma readl/writel
  ARM: tegra: Use a function to get the chip ID
  ARM: tegra: Sort includes alphabetically
  ARM: tegra: Move includes to include/soc/tegra
  ...
2014-08-08 11:00:26 -07:00
Bjorn Helgaas
981c191778 Merge branches 'pci/host-designware', 'pci/host-mvebu' and 'pci/host-tegra' into next
* pci/host-designware:
  PCI: designware: Add MSI-related pcie_host_ops for v3.65 hardware
  PCI: designware: Add config access-related pcie_host_ops for v3.65 hardware
  PCI: dra7xx: Add TI DRA7xx PCIe driver
  PCI: designware: Program ATU with untranslated address
  PCI: designware: Look for configuration space in 'reg', not 'ranges'

* pci/host-mvebu:
  PCI: mvebu: Remove ARCH_KIRKWOOD dependency

* pci/host-tegra:
  PCI: tegra: Add debugfs support
2014-07-22 17:55:50 -06:00
Murali Karicheri
2f37c5a81c PCI: designware: Add MSI-related pcie_host_ops for v3.65 hardware
DesignWare v3.65 hardware implements MSI controller registers in
application space.  This requires updates to the DesignWare core to
support controllers based on this older hardware.

Add msi_irq_set()/clear() interfaces to allow Set/Clear MSI IRQ enable bit
in the application register.  Also, v3.65 hardware uses the MSI_IRQ
register in application register space to raise MSI IRQ to the RC from EP.
Current code uses the standard mechanism as per PCI spec.  So add
get_msi_data() to get the address of this register so common code can
work on both v3.65 and newer hardware.

[bhelgaas: changelog]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
2014-07-22 16:47:29 -06:00
Murali Karicheri
a1c0ae9c24 PCI: designware: Add config access-related pcie_host_ops for v3.65 hardware
DesignWare v3.65 hardware requires application space registers to be
configured to access the remote EP config space.

To support this, add rd_other_conf() and wr_other_conf() to pcie_host_ops.

[bhelgaas: changelog]
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Pratyush Anand <pratyush.anand@st.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
CC: Russell King <linux@arm.linux.org.uk>
CC: Grant Likely <grant.likely@linaro.org>
CC: Rob Herring <robh+dt@kernel.org>
CC: Richard Zhu <r65037@freescale.com>
CC: Kishon Vijay Abraham I <kishon@ti.com>
CC: Marek Vasut <marex@denx.de>
CC: Arnd Bergmann <arnd@arndb.de>
CC: Pawel Moll <pawel.moll@arm.com>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
CC: Kumar Gala <galak@codeaurora.org>
CC: Randy Dunlap <rdunlap@infradead.org>
CC: Grant Likely <grant.likely@linaro.org>
2014-07-22 16:03:54 -06:00
Kishon Vijay Abraham I
47ff3de911 PCI: dra7xx: Add TI DRA7xx PCIe driver
Add support for PCIe controller in DRA7xx.  This driver re-uses the
designware core code that is already present in kernel.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Mohit Kumar <mohit.kumar@st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
2014-07-22 15:26:24 -06:00
Kishon Vijay Abraham I
f4c55c5a3f PCI: designware: Program ATU with untranslated address
In DRA7, the CPU sees 32-bit addresses, but the PCIe controller can see
only 28-bit addresses.  So whenever the CPU issues a read/write request,
the 4 most significant bits are used by L3 to determine the target
controller.  For example, the CPU reserves [mem 0x20000000-0x2fffffff]
for the PCIe controller but the PCIe controller will see only
[0x00000000-0x0fffffff].  For programming the outbound translation
window the *base* should be programmed as 0x00000000.  Whenever we try to
write to, e.g., 0x20000000, it will be translated to whatever we have
programmed in the translation window with base as 0x00000000.

This is needed when the dt node is modelled something like this:

    axi {
        compatible = "simple-bus";
        #size-cells = <1>;
        #address-cells = <1>;
        ranges = <0x0        0x20000000 0x10000000 // 28-bit bus
                  0x51000000 0x51000000 0x3000>;
        pcie@51000000 {
                reg = <0x1000 0x2000>, <0x51002000 0x14c>, <0x51000000 0x2000>;
                reg-names = "config", "ti_conf", "rc_dbics";
                #address-cells = <3>;
                #size-cells = <2>;
                ranges = <0x81000000 0 0          0x03000 0 0x00010000
                          0x82000000 0 0x20013000 0x13000 0 0xffed000>;
        };
    };

Here the CPU address for configuration space is 0x20013000 and the
controller address for configuration space is 0x13000.  The controller
address should be used while programming the ATU (in order for translation
to happen properly in DRA7xx).

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Mohit Kumar <mohit.kumar@st.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Jingoo Han <jg1.han@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
2014-07-22 15:26:24 -06:00
Kishon Vijay Abraham I
4dd964df36 PCI: designware: Look for configuration space in 'reg', not 'ranges'
The configuration address space has so far been specified in *ranges*,
however it should be specified in *reg* making it a platform MEM resource.
Hence used 'platform_get_resource_*' API to get configuration address space
in the designware driver.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Mohit Kumar <mohit.kumar@st.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Cc: Jason Gunthorpe <jgunthorpe@obsidianresearch.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Arnd Bergmann <arnd@arndb.de>
2014-07-22 14:17:47 -06:00
Thierry Reding
2cb989f6e9 PCI: tegra: Add debugfs support
Provide a debugfs file ("pcie/ports") that shows the current link status
for each root port.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2014-07-22 12:30:46 -06:00
Andrew Lunn
c27602086d PCI: mvebu: Remove ARCH_KIRKWOOD dependency
mach-kirkwood has been removed, now that kirkwood lives in mach-mvebu.
ARCH_MVEBU is sufficient.

Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
2014-07-22 12:25:22 -06:00
Viresh Kumar
779ae55bd8 PCI: spear: Remove spear13xx_pcie_remove()
Following compilation warning occurs when compiled with:
CONFIG_DEBUG_SECTION_MISMATCH=y

 WARNING: vmlinux.o(.init.data+0x3338): Section mismatch in reference from the
 variable spear13xx_pcie_driver to the function
 .exit.text:spear13xx_pcie_remove()

This driver isn't allowed to unload, and so doesn't have a *_exit() routine. But
it still has spear13xx_pcie_remove() marked with __exit.

As this driver can't unload, .remove() would never be called, right? So get rid
of it.

Fixes: 51b66a6ce1 (PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx)
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-20 12:27:50 -07:00
Viresh Kumar
6675ef212d PCI: spear: Fix Section mismatch compilation warning for probe()
Following compilation warning occurs when compiled with:
CONFIG_DEBUG_SECTION_MISMATCH=y

 WARNING: drivers/pci/host/built-in.o(.data+0xc0): Section mismatch in
 reference from the variable spear13xx_pcie_driver to the function
 .init.text:spear13xx_pcie_probe()

Both .probe() and pcie_init() are marked with __init, but spear13xx_pcie_driver
isn't. And so section mismatch.

Fix it by marking spear13xx_pcie_driver with __initdata.

Fixes: 51b66a6ce1 (PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx)
Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-20 12:27:29 -07:00
Olof Johansson
b776eec135 ARM: tegra: rework PCIe regulators
This branch reworks the set of regulators that the Tegra PCIe driver
 uses, so that the driver and DT bindings more correctly model what's
 really going on in HW. For backwards-compatibility the driver will
 fallback to using the old set of regulators if the new ones can't be
 found.
 
 I've made this a separate branch in case it needs to be pulled into the
 PCIe tree to resolve any conflicts.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJTyRXmAAoJEN0jrNd/PrOhpcIP/1bhFxw7a0HjG1Cwtj27uJKo
 2S9z28sFbVERmOTy4Sfy/bf3EEBNZajgYJ0kOIJbrVRkpGV6BU/3nNVmqR9G1jOY
 9wVr7e9Z0lWQ8r8e9jXIRpTOO1PUFfx3AhyjD1kT5bUsI8m5dcDmryyLqsvh2UDn
 F1S2JpAeylVSFzZLspqnuc1HgG6V4xMxt7JCKQqQo4uTTs2LVWpLWRqQEOhpsmVW
 WDSzovSXBThm4wXvZlrTij7HuOqYbwG3wLpzJMVVfhysRZDfIO8i7hK2kAQ8+3O6
 0yS8HsfzrjhGvNgbGUt+hGTYg+omHp3i0RJf/AxhOIOrA5fIs4pOTC2HSqq+kG4x
 K2OWCUboaTbMpJ/+TwcY83Ohk/r+Qj3Ay9loyIbQ5e2ORbkmpvbBALiQLTFwswaf
 zPsuwSXW8imVnPsduo+7qnvq2sbQ45Wy30wZMPRKYSfQzNY40AK0hzvRtW1BfMHY
 3P35z+9uIygiOr4KlwvbnTjL/nNWa5aVO8CYDfAxDa81SUJn/4vGkJNLNw6z1zo8
 Jvem210R6G0dca257NFWZ9w7hB9bfX3AVR8ZovDkg7tiOOlaOwq8HJrVU8oM3dtu
 /ztRVYKo/XqRtKyCcUnCtoF6CswlhfT4u4JOmo/5KwD9VBmxQPWHEkUwMl9j6eu3
 5dNKF79ROlQ1Idk0jjDZ
 =48cL
 -----END PGP SIGNATURE-----

Merge tag 'tegra-for-3.17-pcie-regulators' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers

Merge "ARM: tegra: rework PCIe regulators" from Thierry Reding:

This branch reworks the set of regulators that the Tegra PCIe driver
uses, so that the driver and DT bindings more correctly model what's
really going on in HW. For backwards-compatibility the driver will
fallback to using the old set of regulators if the new ones can't be
found.

I've made this a separate branch in case it needs to be pulled into the
PCIe tree to resolve any conflicts.

* tag 'tegra-for-3.17-pcie-regulators' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: Remove legacy PCIe power supply properties
  PCI: tegra: Remove deprecated power supply properties
  PCI: tegra: Implement accurate power supply scheme
  ARM: tegra: Add new PCIe regulator properties
  PCI: tegra: Overhaul regulator usage

Signed-off-by: Olof Johansson <olof@lixom.net>
2014-07-19 12:35:45 -07:00
Thierry Reding
077fb1580d PCI: tegra: Implement accurate power supply scheme
The current description of power supplies doesn't match the hardware.
Instead it's designed to support the needs of current designs, which
will break as soon as a new design appears that cannot be described
using the current assumptions.

In order to fully support all possible future designs, all power supply
inputs to the PCIe block need to be accurately described and separately
configurable.

Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
2014-07-18 11:20:03 +02:00
Thierry Reding
7232398abc ARM: tegra: Convert PMC to a driver
This commit converts the PMC support code to a platform driver. Because
the boot process needs to call into this driver very early, also set up
a minimal environment via an early initcall.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17 14:58:43 +02:00
Thierry Reding
306a7f9139 ARM: tegra: Move includes to include/soc/tegra
In order to not clutter the include/linux directory with SoC specific
headers, move the Tegra-specific headers out into a separate directory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-07-17 13:26:47 +02:00
Bjorn Helgaas
792688fde4 Merge branches 'pci/host-generic', 'pci/host-mvebu', 'pci/host-rcar', 'pci/host-tegra', 'pci/msi', 'pci/misc', 'pci/resource' and 'pci/virtualization' into next
* pci/host-generic:
  PCI: generic: Fix GPL v2 license string typo

* pci/host-mvebu:
  PCI: mvebu: Fix GPL v2 license string typo

* pci/host-rcar:
  PCI: rcar: Fix GPL v2 license string typo

* pci/host-tegra:
  PCI: tegra: Fix GPL v2 license string typo

* pci/msi:
  PCI/MSI: Use irq_get_msi_desc() to simplify code
  PCI/MSI: Remove unused list access in __pci_restore_msix_state()
  PCI/MSI: Retrieve first MSI IRQ from msi_desc rather than pci_dev
  PCI/MSI: Remove unused function msi_remove_pci_irq_vectors()
  PCI/MSI: Add msi_setup_entry() to clean up MSI initialization

* pci/misc:
  PCI: Configure ASPM when enabling device
  x86: don't exclude low BIOS area when allocating address space for non-PCI cards
  PCI: Add include guard to include/linux/pci_ids.h
  x86, ia64: Move EFI_FB vga_default_device() initialization to pci_vga_fixup()

* pci/resource:
  PCI: Tidy resource assignment messages
  PCI: Return conventional error values from pci_revert_fw_address()
  PCI: Cleanup control flow
  PCI: Support BAR sizes up to 128GB
  PCI: Keep original resource if we fail to expand it

* pci/virtualization:
  powerpc/pci: Remove duplicate logic
  PCI: Make resetting secondary bus logic common
2014-07-16 17:09:47 -06:00
Bjorn Helgaas
eed6542dd5 PCI: generic: Fix GPL v2 license string typo
Per license_is_gpl_compatible(), the MODULE_LICENSE() string for GPL v2 is
"GPL v2", not "GPLv2".  Use "GPL v2" so this module doesn't taint the
kernel.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Will Deacon <will.deacon@arm.com>
2014-07-15 15:07:46 -06:00
Bjorn Helgaas
68947eb175 PCI: rcar: Fix GPL v2 license string typo
Per license_is_gpl_compatible(), the MODULE_LICENSE() string for GPL v2 is
"GPL v2", not "GPLv2".  Use "GPL v2" so this module doesn't taint the
kernel.

Based-on-work-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2014-07-15 15:06:12 -06:00
Thierry Reding
d975cb5703 PCI: tegra: Fix GPL v2 license string typo
Per license_is_gpl_compatible(), the MODULE_LICENSE() string for GPL v2 is
"GPL v2", not "GPLv2".  Use "GPL v2" so this module doesn't taint the
kernel.

[bhelgaas: changelog]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
2014-07-15 15:02:49 -06:00
Thierry Reding
505d8655f7 PCI: mvebu: Fix GPL v2 license string typo
Per license_is_gpl_compatible(), the MODULE_LICENSE() string for GPL v2 is
"GPL v2", not "GPLv2".  Use "GPL v2" so this module doesn't taint the
kernel.

[bhelgaas: changelog]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
2014-07-15 15:01:05 -06:00
Pratyush Anand
51b66a6ce1 PCI: spear: Add PCIe driver for ST Microelectronics SPEAr13xx
ARM based ST Microelectronics's SPEAr1310 and SPEAr1340 SOCs have onchip
designware PCIe controller. To make that usable, this patch adds a wrapper
driver based on existing designware driver.

Adds bindings for this new driver and update MAINTAINERS as well.

Cc: linux-pci@vger.kernel.org
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Pratyush Anand <pratyush.anand@st.com>
Signed-off-by: Mohit Kumar <mohit.kumar@st.com>
[viresh: fixed logs/cclist/checkpatch warnings, broken into smaller patches]
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2014-07-14 10:30:39 +05:30
Phil Edworthy
0549252a1d PCI: rcar: Remove rcar_pcie_setup_window() resource argument
rcar_pcie_setup_window() took both the window number and the resource,
which was redundant because we can look up the resource from the window
number.

Remove the "res" argument.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
2014-07-05 12:00:00 -06:00
Phil Edworthy
b77188495d PCI: rcar: Cleanup style and formatting
This patch just makes symbol and function name changes to avoid potential
conflicts, along with minor formatting changes.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
2014-07-05 11:59:16 -06:00
Phil Edworthy
2c3fd4c935 PCI: rcar: Use correct initial HW settings
Although the R-Car PCIe driver works as it is, there are a number of
incorrect settings that this patch corrects. It corrects:
 - enabling the PCI Express Extended Cap ID.
 - setting Data Link Layer Link Active Reporting Capable.
 - terminating list of capabilities.

It also removes enabling the MAC data scrambling as this is the default HW
setting, and removes incorrect code to enable slave bus mastering as this
is done by the PCI core.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
2014-07-05 11:58:12 -06:00