Commit Graph

966 Commits

Author SHA1 Message Date
Ralf Baechle
cb418b34ca Merge branch 'ralf-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next 2012-09-28 16:29:55 +02:00
Ralf Baechle
77a0d763c4 Merge branch 'rixi-3.7' of git://git.linux-mips.org/pub/scm/sjhill/linux-sjhill into mips-for-linux-next 2012-09-28 16:25:52 +02:00
Ralf Baechle
8922c9b4b2 Merge branch 'broadcom' of git://dev.phrozen.org/mips-next into mips-for-linux-next 2012-09-27 18:09:45 +02:00
Ralf Baechle
73d155b304 Merge branch 'ath79' of git://dev.phrozen.org/mips-next into mips-for-linux-next 2012-09-27 18:09:12 +02:00
Ralf Baechle
35a041e77a Merge branch 'lantiq' of git://dev.phrozen.org/mips-next into mips-for-linux-next 2012-09-27 18:07:25 +02:00
Ralf Baechle
e33fd70bae Merge branch 'cn6xxx-mgmt' of git://git.linux-mips.org/pub/scm/daney/upstream-daney into mips-for-linux-next 2012-09-27 18:00:34 +02:00
Ralf Baechle
9b11d4370c Merge branch 'cn68xx-ciu2' of git://git.linux-mips.org/pub/scm/daney/upstream-daney into mips-for-linux-next 2012-09-27 18:00:07 +02:00
Ralf Baechle
ce71d24cff MIPS: Wire kcmp syscall.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-09-26 11:24:28 +02:00
Steven J. Hill
b30fdd6f73 MIPS: MIPSsim: Remove the MIPSsim platform.
The MIPSsim platform is no longer supported or used.

[ralf@linux-mips.org: Also remove mipssim from arch/mips/Kbuild.platforms
and delete arch/mips/include/asm/mach-mipssim/*.]

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4350/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-09-25 16:04:54 +02:00
Al Viro
b1c561845d MIPS: NOTIFY_RESUME is not needed in TIF masks
If it's set, SIGPENDING is also set.  And SIGPENDING is present in
the masks...

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-09-22 15:47:40 +02:00
Al Viro
0b894bd8e4 MIPS: Unobfuscate _TIF..._MASK
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-09-22 15:47:17 +02:00
Steven J. Hill
05857c64ec MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
Remove usage of the 'kernel_uses_smartmips_rixi' macro from all files
and use new 'cpu_has_rixi' instead.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Acked-by: David Daney <david.daney@cavium.com>
2012-09-13 17:00:34 -05:00
Steven J. Hill
b2ab4f08e8 MIPS: Add base architecture support for RI and XI.
Originally both Read Inhibit (RI) and Execute Inhibit (XI) were
supported by the TLB only for a SmartMIPS core. The MIPSr3(TM)
Architecture now defines an optional feature to implement these
TLB bits separately. Support for one or both features can be
checked by looking at the Config3.RXI bit.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
Acked-by: David Daney <david.daney@cavium.com>
2012-09-13 16:55:53 -05:00
Steven J. Hill
e6de1a09a2 MIPS: uasm: Add INS and EXT instructions.
These are MIPS32R2 instructions for merging and extracting bit fields
from one GPR into another.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
2012-09-13 15:43:53 -05:00
Steven J. Hill
2299c49d60 MIPS: Code clean-ups for the GIC.
Fix whitespace, beautify the code and remove debug statements.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
2012-09-13 15:43:48 -05:00
Steven J. Hill
0b271f5600 MIPS: Make GIC code platform independent.
The GIC interrupt code is used by multiple platforms and the
current code was half Malta dependent code. These changes
abstract away the platform specific differences.

Signed-off-by: Steven J. Hill <sjhill@mips.com>
2012-09-13 15:43:47 -05:00
Steven J. Hill
3070033a16 MIPS: Add core files for MIPS SEAD-3 development platform.
More information about the SEAD-3 platform can be found at
<http://www.mips.com/products/development-kits/mips-sead-3/>
on MTI's site. Currently, the M14K family of cores is what
the SEAD-3 is utilised with.

Signed-off-by: Douglas Leung <douglas@mips.com>
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Steven J. Hill <sjhill@mips.com>
2012-09-13 15:43:46 -05:00
Steven J. Hill
006a851b10 MIPS: Add support for the 1074K core.
Signed-off-by: Steven J. Hill <sjhill@mips.com>
2012-09-13 15:21:47 -05:00
John Crispin
6a88a0f762 MIPS: lantiq: make use of __gpio_to_irq
The gpio_chip struct allows us to set a .to_irq callback. Once this is set
we can rely on the generic __gpio_to_irq() function to map gpio->irq allowing
more than one gpio_chip to register an interrupt

Signed-off-by: John Crispin <blogic@openwrt.org>
2012-09-13 10:30:59 +02:00
John Crispin
e316cb2b16 OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
of up to 32 pins.

Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
2012-09-13 10:30:58 +02:00
David Daney
70a26a219c MIPS: Octeon: Add octeon_io_clk_delay() function.
Also cleanup and fix octeon_init_cvmcount()

Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Acked-by: David S. Miller <davem@davemloft.net>
2012-08-31 11:48:48 -07:00
David Daney
88fd85892a MIPS: OCTEON: Add support for cn68XX interrupt controller.
The cn68XX has a new interrupt controller named CIU2, add support for
this, and use it if cn68XX detected at runtime.

Signed-off-by: David Daney <david.daney@cavium.com>
2012-08-31 10:46:54 -07:00
David Daney
9787c56ee3 MIPS: OCTEON: Add OCTEON_IRQ_* definitions for cn68XX chips.
There are 64 workqueue, 32 watchdog, and 4 mbox.

Signed-off-by: David Daney <david.daney@cavium.com>
2012-08-31 10:46:54 -07:00
David Daney
c5aa59e88f MIPS: OCTEON: Update register definitions.
Add support for cn68xx, cn61xx, cn63xx, cn66xx and cnf71XX.

Add little-endian register layouts.

Patch cvmx-interrupt-rsl.c for changed definition.

Signed-off-by: David Daney <david.daney@cavium.com>
2012-08-31 10:46:53 -07:00
David Daney
5cf02e5554 MIPS: OCTEON: Add detection of cnf71xx parts.
Also add cvmx_get_octeon_family().

Both of these are needed by the upcoming register definition refresh
patch.

Signed-off-by: David Daney <david.daney@cavium.com>
2012-08-31 10:46:01 -07:00
Kevin Cernekee
22df90f6bb MIPS: BCM63XX: Create platform_device for USBD
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Reviewed-by: Jonas Gorski <jonas.gorski@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4111/
Signed-off-by: John Crispin <blogic@openwrt.org>
2012-08-30 20:15:52 +02:00
Kevin Cernekee
5fd66c2b2b MIPS: BCM63XX: Add register and IRQ definitions for USB 2.0 device
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4084/
Signed-off-by: John Crispin <blogic@openwrt.org>
2012-08-30 20:15:52 +02:00
Kevin Cernekee
a56e853805 MIPS: BCM63XX: Fix USB IRQ definitions for 6328
OHCI/EHCI are in the high (second) word.  Not currently used by any
driver.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4026/
Signed-off-by: John Crispin <blogic@openwrt.org>
2012-08-30 20:15:52 +02:00
Kevin Cernekee
18ec0e7079 MIPS: BCM63XX: Add register definitions for USBD dependencies
The USB 2.0 device depends on some functionality in other blocks, such
as GPIO and USBH.  Add those register definitions here.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4025/
Signed-off-by: John Crispin <blogic@openwrt.org>
2012-08-30 20:15:52 +02:00
Kevin Cernekee
6f9423454a MIPS: BCM63XX: Add new IUDMA definitions needed for USBD
Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4083/
Signed-off-by: John Crispin <blogic@openwrt.org>
2012-08-30 20:15:52 +02:00
Kevin Cernekee
932e30b6ea MIPS: BCM63XX: Move DMA descriptor definition into common header file
The "IUDMA" engine used by bcm63xx_enet is also used by other blocks,
such as the USB 2.0 device.  Move the definitions into a common file so
that they do not need to be duplicated in each driver.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Patchwork: http://patchwork.linux-mips.org/patch/4082/
Signed-off-by: John Crispin <blogic@openwrt.org>
2012-08-30 20:15:52 +02:00
Gabor Juhos
00ffed582f MIPS: ath79: add USB platform setup code for AR934X
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4172/
Signed-off-by: John Crispin <blogic@openwrt.org>
2012-08-28 12:29:57 +02:00
John Crispin
61fa969f27 MIPS: lantiq: split up IRQ IM ranges
Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
the SVIP we need to support IM ranges that are scattered inside the register range.

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4237/
2012-08-23 00:08:17 +02:00
Gabor Juhos
00dc5ce2a6 MIPS: ath79: don't hardcode the unavailability of the DSP ASE
The ath79 platform code allows to run a single kernel image on various
SoCs which are based on the 24Kc and 74Kc cores.  The current code
explicitely disables the DSP ASE, but that is available in the 74Kc core.

Remove the override in order to let the kernel to detect the availability
of the DSP ASE at runtime.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4222/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-08-17 10:57:29 +02:00
Jayachandran C
cf9bfe55f2 MIPS: Synchronize MIPS count one CPU at a time
The current implementation of synchronise_count_{master,slave} blocks
slave CPUs in early boot until all of them come up. This no longer
works because blocking a CPU with interrupts off after notifying the
CPU to be online causes problems with the current kernel.

Specifically, after the workqueue changes
(commit a08489c569 "Pull workqueue changes from Tejun Heo")
the CPU_ONLINE notification callback workqueue_cpu_up_callback()
will hang on wait_for_completion(&idle_rebind.done), if the slave
CPUs are blocked for synchronize_count_slave().

The changes are to update synchronize_count_{master,slave}() to handle
one CPU at a time and to call synchronise_count_master() in __cpu_up()
so that the CPU_ONLINE notification goes out only after the COP0 COUNT
register is synchronized.

[ralf@linux-mips.org: This matter only to those few platforms which are
using the cp0 counter as their clocksource which are XLP, XLR and MIPS'
CMP solution.]

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4216/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-08-17 10:57:28 +02:00
Florian Fainelli
5a6704454a MIPS: BCM63xx: Fix SPI message control register handling for BCM6338/6348.
BCM6338 and BCM6348 have a message control register width of 8 bits, instead
of 16-bits like what the SPI driver assumes right now. Also the SPI message
type shift value of 14 is actually 6 for these SoCs.
This resulted in transmit FIFO corruption because we were writing 16-bits
to an 8-bits wide register, thus spanning on the first byte of the transmit
FIFO, which had already been filed in bcm63xx_spi_fill_txrx_fifo().

Fix this by passing the message control register width and message type
shift through platform data back to the SPI driver so that it can use
it properly.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Cc: linux-mips@linux-mips.org
Cc: grant.likely@secretlab.ca
Cc: spi-devel-general@lists.sourceforge.net
Cc: jonas.gorski@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/3983/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-08-17 10:57:28 +02:00
Ralf Baechle
861667dc82 MIPS: Fix race condition in module relocation code.
The relocation code was essentially taken from the 2.4 modutils which
perform relocation in userspace.  In 2.6 relocation of multiple modules
may be performed in parallel by the in-kernel loader so the global
variable mips_hi16_list won't fly anymore.  Fix race by moving it into
mod_arch_specific.

[ralf@linux-mips.org: folded in Tony's followup fix.  Thanks Tony!]

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Tony Wu <tung7970@gmail.com>
Cc:  linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/4189/
2012-08-17 10:57:28 +02:00
Gabor Juhos
b4da14abf2 MIPS: ath79: Fix number of GPIO lines for AR724[12]
The AR724[12] SoCs have more GPIO lines than the AR7240.

Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Cc: linux-mips@linux-mips.org
Patchwork: https://http://patchwork.linux-mips.org/patch/4167/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-08-17 10:57:26 +02:00
David Daney
87161ccdc6 MIPS: Octeon: Fix broken interrupt controller code.
Since 3.6.0-rc1,  We are getting many messages like:

WARNING: at kernel/irq/irqdomain.c:444 irq_domain_associate_many+0x23c/0x260()
Modules linked in:
Call Trace:
[<ffffffff814cb698>] dump_stack+0x8/0x34
[<ffffffff81133d00>] warn_slowpath_common+0x78/0xa8
[<ffffffff81187e44>] irq_domain_associate_many+0x23c/0x260
[<ffffffff81187f38>] irq_create_mapping+0xd0/0x220
[<ffffffff81188104>] irq_create_of_mapping+0x7c/0x158
[<ffffffff813e5f08>] irq_of_parse_and_map+0x28/0x40
.
.
.

Both the CIU and GPIO interrupt domains were somewhat screwed up.

For the CIU domain, we need to call irq_domain_associate() for each of
the preassigned irq numbers.  For the GPIO domain, we were applying
the register bit offset in octeon_irq_gpio_xlat, but it should be done
in octeon_irq_gpio_map instead.

Also: Reserve all 8 'core' irqs for the 'core' irq_chip so that they
don't get used by the other domains.  Remove unused OCTEON_IRQ_*
symbols.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4190/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-08-17 10:57:26 +02:00
Ralf Baechle
95cf1468f7 MIPS: Loongson 2: Sort out clock managment.
For unexplainable reasons the Loongson 2 clock API was implemented in a
module so fixing this involved shifting large amounts of code around.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-08-01 18:10:06 +02:00
Linus Torvalds
27c1ee3f92 Merge branch 'akpm' (Andrew's patch-bomb)
Merge Andrew's first set of patches:
 "Non-MM patches:

   - lots of misc bits

   - tree-wide have_clk() cleanups

   - quite a lot of printk tweaks.  I draw your attention to "printk:
     convert the format for KERN_<LEVEL> to a 2 byte pattern" which
     looks a bit scary.  But afaict it's solid.

   - backlight updates

   - lib/ feature work (notably the addition and use of memweight())

   - checkpatch updates

   - rtc updates

   - nilfs updates

   - fatfs updates (partial, still waiting for acks)

   - kdump, proc, fork, IPC, sysctl, taskstats, pps, etc

   - new fault-injection feature work"

* Merge emailed patches from Andrew Morton <akpm@linux-foundation.org>: (128 commits)
  drivers/misc/lkdtm.c: fix missing allocation failure check
  lib/scatterlist: do not re-write gfp_flags in __sg_alloc_table()
  fault-injection: add tool to run command with failslab or fail_page_alloc
  fault-injection: add selftests for cpu and memory hotplug
  powerpc: pSeries reconfig notifier error injection module
  memory: memory notifier error injection module
  PM: PM notifier error injection module
  cpu: rewrite cpu-notifier-error-inject module
  fault-injection: notifier error injection
  c/r: fcntl: add F_GETOWNER_UIDS option
  resource: make sure requested range is included in the root range
  include/linux/aio.h: cpp->C conversions
  fs: cachefiles: add support for large files in filesystem caching
  pps: return PTR_ERR on error in device_create
  taskstats: check nla_reserve() return
  sysctl: suppress kmemleak messages
  ipc: use Kconfig options for __ARCH_WANT_[COMPAT_]IPC_PARSE_VERSION
  ipc: compat: use signed size_t types for msgsnd and msgrcv
  ipc: allow compat IPC version field parsing if !ARCH_WANT_OLD_COMPAT_IPC
  ipc: add COMPAT_SHMLBA support
  ...
2012-07-30 17:25:34 -07:00
Will Deacon
c1d7e01d78 ipc: use Kconfig options for __ARCH_WANT_[COMPAT_]IPC_PARSE_VERSION
Rather than #define the options manually in the architecture code, add
Kconfig options for them and select them there instead.  This also allows
us to select the compat IPC version parsing automatically for platforms
using the old compat IPC interface.

Reported-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Chris Metcalf <cmetcalf@tilera.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2012-07-30 17:25:21 -07:00
Ralf Baechle
68d8848567 Merge branches 'next/generic', 'next/alchemy', 'next/bcm63xx', 'next/cavium', 'next/jz4740', 'next/lantiq', 'next/loongson1b' and 'next/netlogic' into mips-for-linux-next 2012-07-25 16:37:46 +02:00
Kelvin Cheung
ca585cf9fb MIPS: Loongson 1B: Add board support
Adds basic platform devices for Loongson 1B, including serial port,
ethernet, USB, RTC and interrupt handler.

The Loongson 1B UART is compatible with NS16550A, the Loongson 1B GMAC is
built around a Synopsys IP Core.

Use normal instead of enhanced descriptors.

Thanks to Giuseppe for updating the normal descriptor in stmmac driver.
Thanks to Zhao Zhang for implementing the RTC driver.

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: linux-kernel@vger.kernel.org
Cc: wuzhangjin@gmail.com
Cc: zhzhl555@gmail.com
Cc: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/4133/
Patchwork: https://patchwork.linux-mips.org/patch/4134/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-25 16:17:24 +02:00
Jayachandran C
1005f281fa MIPS: Netlogic: remove cpu_has_dc_aliases define for XLP
On XLP, the dcache size depends on the number of enabled threads in
core. There are no dcache aliases if the pagesize is large enough or
if enough threads are enabled in the core.

Remove the #define for cpu_has_dc_aliases and leave it to be computed
at runtime.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/4099/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-24 17:28:55 +02:00
Jayachandran C
57d7cdb630 MIPS: Netlogic: Add IRQ mappings for more devices
Add IRT to IRQ translation for the MMC and I2C IRQs.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3761/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-24 17:28:54 +02:00
Ganesan Ramalingam
1004165f34 MIPS: Netlogic: USB support for XLP
The XLP USB controller appears as a device on the internal SoC PCIe
bus, the block has 2 EHCI blocks and 4 OHCI blocks. Change are to:

* Add files netlogic/xlp/usb-init.c and asm/netlogic/xlp-hal/usb.h
  to initialize the USB controller and define PCI fixups. The PCI
  fixups are to setup interrupts and DMA mask.
* Update include/asm/xlp-hal/{iomap.h,pic.h,xlp.h} to add interrupt
  mapping for EHCI/OHCI interrupts.

Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3756/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-24 17:28:54 +02:00
Ganesan Ramalingam
9bac624b0f MIPS: Netlogic: XLP PCIe controller support.
Adds support for the XLP on-chip PCIe controller. On XLP, the
on-chip devices(including the 4 PCIe links) appear in the PCIe
configuration space of the XLP as PCI devices.

The changes are to initialize and register the PCIe controller,
enable hardware byte swap in the PCIe IO and MEM space, and to
enable PCIe interrupts.

Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3760/
Patchwork: https://patchwork.linux-mips.org/patch/4104/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-24 17:28:54 +02:00
Ganesan Ramalingam
3a2f9b9905 MIPS: Netlogic: Platform NAND/NOR flash support
Changes to add support for the boot NOR flash on XLR boards and the
boot NAND/NOR flash drivers on the XLS boards.

Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3758/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-24 17:28:54 +02:00
Jayachandran C
c5a48ff81e MIPS: Netlogic: Remove NETLOGIC_ prefix
Remove NETLOGIC_ prefix from gpio register definitions, this will
bring it in-line with the other Netlogic headers.

Having NETLOGIC prefix here is misleading because these are XLR/XLS
specific register definitions.

Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3754/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2012-07-24 17:28:53 +02:00