This patch fixes the following DTC warnings for many boards:
"Node /fixedregulator@0 has a unit name, but no reg property"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The NAND Ready/Busy# line is connected to GPMC_WAIT0 pin and
can't be used for wait state insertion for NAND I/O read/write.
So disable read/write wait monitoring as per Reference Manual's
suggestion [1].
[1] dm816x TRM: SPRUGX8C: 9.2.4.12.2 NAND Device-Ready Pin
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add compatible id, GPMC register resource and interrupt
resource to NAND controller nodes.
The GPMC node will provide an interrupt controller for the
NAND IRQs.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As always, this tends to be one of our bigger branches. There are lots of
updates this release, but not that many jumps out as something that needs
more detailed coverage. Some of the highlights are:
- DTs for the new Annapurna Labs Alpine platform
- More graphics DT pieces falling into place on Exynos, bridges, clocks.
- Plenty of DT updates for Qualcomm platforms for various IP blocks
- Some churn on Tegra due to switch-over to tool-generated pinctrl data
- Misc fixes and updates for Atmel at91 platforms
- Various DT updates to add IP block support on Broadcom's Cygnus platforms
- More updates for Renesas platforms as DT support is added for various IP
blocks (IPMMU, display, audio, etc).
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJVNzKFAAoJEIwa5zzehBx3JtEP/1g89CW7iZHAUyIiC+jtgqck
ASoplr13DLD0HWjjWITX3zm7J/iY57YjEv14tHH/xmrh5YCCZ+mRLqiD/Plnv0Zv
JdJRRJv/NMnMlu/tA1aBO326JOt2Vw+3YngmYayDpoRzVifx2YTJLbu2difa+6rM
vN6FpOE6U5jkvM16+gqxKxyx0tGIQz9cTn+9q2V1fDS++vZ2VvqfB5pTNul3BKAF
OVCNFJ/EUE9EPMPbmgDjYmNE/POj64kF32n7NBEQz2Z+nwDNxDAecfF356hV7o5g
JsFLNK+4c2QQqBL775xzCf5kK+n/V2cFEpDica+hU70AdWsjdAlUFrbOsWGUJLRi
4Blrv8GRxEKeOCs8AFKYCM+z3zf2ais7JMteD2VW26ywCwpUt+QEZTUVHRHU3NYQ
BMI7uyTGIH2GyLyS+Av3vikza8IbDIwlYuuDpXhCJSXXgKSnbzCrpjkhyGLccBJR
k3qgUwPJVw9hP1qaaNgvb7p9oNhTP2yLl3fQ68WqI7QWIupW0/s12INhzFFgt6zU
Nzcx010ku9yMeMMGtfiNgA3cMln+Ysfs1UIUOMQ36zP1PCtHJkZgwtZzTsBE4A04
KqmiLL/+7qsconEhEanmDzTpeXiNzERnOKSSqVN7Fwp89GEFJLrWpHSXI+8SBTHC
fB54LRTNYdlcoN0QshcT
=wqhB
-----END PGP SIGNATURE-----
Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM DT updates from Olof Johansson:
"As always, this tends to be one of our bigger branches. There are
lots of updates this release, but not that many jumps out as something
that needs more detailed coverage. Some of the highlights are:
- DTs for the new Annapurna Labs Alpine platform
- more graphics DT pieces falling into place on Exynos, bridges,
clocks.
- plenty of DT updates for Qualcomm platforms for various IP blocks
- some churn on Tegra due to switch-over to tool-generated pinctrl
data
- misc fixes and updates for Atmel at91 platforms
- various DT updates to add IP block support on Broadcom's Cygnus
platforms
- more updates for Renesas platforms as DT support is added for
various IP blocks (IPMMU, display, audio, etc)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (231 commits)
ARM: dts: alpine: add internal pci
Revert "ARM: dts: mt8135: Add pinctrl/GPIO/EINT node for mt8135."
ARM: mvebu: use 0xf1000000 as internal registers on Armada 370 DB
ARM: dts: qcom: Add idle state device nodes for 8064
ARM: dts: qcom: Add idle states device nodes for 8084
ARM: dts: qcom: Add idle states device nodes for 8974/8074
ARM: dts: qcom: Update power-controller device node for 8064 Krait CPUs
ARM: dts: qcom: Add power-controller device node for 8084 Krait CPUs
ARM: dts: qcom: Add power-controller device node for 8074 Krait CPUs
devicetree: bindings: Document qcom,idle-states
devicetree: bindings: Update qcom,saw2 node bindings
dt-bindings: Add #defines for MSM8916 clocks and resets
arm: dts: qcom: Add LPASS Audio HW to IPQ8064 device tree
arm: dts: qcom: Add APQ8084 chipset SPMI PMIC's nodes
arm: dts: qcom: Add 8x74 chipset SPMI PMIC's nodes
arm: dts: qcom: Add SPMI PMIC Arbiter nodes for APQ8084 and MSM8974
arm: dts: qcom: Add LCC nodes
arm: dts: qcom: Add TCSR support for MSM8960
arm: dts: qcom: Add TCSR support for MSM8660
arm: dts: qcom: Add TCSR support for IPQ8064
...
On dm816x we have no PIN_INPUT vs PIN_OUTPUT configuration, there
are just pulls. Let's remove the bogus flags.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit a54879a008 ("ARM: dts: Fix USB dts configuration for dm816x")
attempted to fix the USB features introduced by commit 7800064ba5
("ARM: dts: Add basic dm816x device tree configuration") but obviously
I did not read the dmesg as more USB issues still keep trickling in.
It should be usb1_pins instead not usb0_pins for the second interface
to avoid warnings from pinctrl framework.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit 7800064ba5 ("ARM: dts: Add basic dm816x device tree
configuration") added basic devices for dm816x, but I was not able
to test the GPIO interrupts earlier until I found some suitable pins
to test with. We can mux the MMC card detect and write protect pins
from SD_SDCD and SD_SDWP mode to use a normal GPIO interrupts that
are also suitable for the MMC subsystem.
This turned out several issues that need to be fixed:
- I set the GPIO type wrong to be compatible with omap3 instead
of omap4. The GPIO controller on dm816x has EOI interrupt
register like omap4 and am335x.
- I got the GPIO interrupt numbers wrong as each bank has two
and we only use one. They need to be set up the same way as
on am335x.
- The gpio banks are missing interrupt controller related
properties.
With these changes the GPIO interrupts can be used with the
MMC card detect pin, so let's wire that up. Let's also mux all
the MMC lines for completeness while at it.
For the first GPIO bank I tested using GPMC lines temporarily
muxed to GPIOs on the dip switch 10.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit 7800064ba5 ("ARM: dts: Add basic dm816x device tree
configuration") added basic devices for dm816x, but I was not able
to test the USB completely because of an unconfigured USB phy, and
I only tested it to make sure the Mentor chips are detected and
clocked without a phy.
After testing the USB with actual devices I noticed a few issues
that should be fixed to avoid confusion:
- The USB id pin on dm8168-evm is hardwired and can be changed
only by software. As there are two USB-A type connectors, let's
start both in host mode instead of otg.
- The Mentor core is configured in such a way on dm8168-evm that
it's not capable of multipoint at least on revision c board
that I have.
- We need ranges for the syscon to properly set up the phy as
children of the SCM syscon area.
- Let's not disable the second interface, the board specific
dts files can do that if really needed. Most boards should
just keep it enabled to ensure the device is idled properly.
Note that also a phy and several musb fixes are still needed to
make the USB to work properly in addition to this fix.
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This allows booting the device with basic functionality.
Note that at least on my revision c board the DDR3 does
not seem to work properly and only some of the memory
can be reliably used.
Also, the mainline u-boot does not seem to properly
initialize the ethernet, so I've been using the old TI
u-boot at:
http://arago-project.org/git/projects/?p=u-boot-omap3.git;a=summary
Cc: Brian Hutchinson <b.hutchman@gmail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
