Commit Graph

216 Commits

Author SHA1 Message Date
Zhen Lei
aa3ac9469c iommu/iova: Make dma_32bit_pfn implicit
Now that the cached node optimisation can apply to all allocations, the
couple of users which were playing tricks with dma_32bit_pfn in order to
benefit from it can stop doing so. Conversely, there is also no need for
all the other users to explicitly calculate a 'real' 32-bit PFN, when
init_iova_domain() can happily do that itself from the page granularity.

CC: Thierry Reding <thierry.reding@gmail.com>
CC: Jonathan Hunter <jonathanh@nvidia.com>
CC: David Airlie <airlied@linux.ie>
CC: Sudeep Dutt <sudeep.dutt@intel.com>
CC: Ashutosh Dixit <ashutosh.dixit@intel.com>
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Zhen Lei <thunder.leizhen@huawei.com>
Tested-by: Nate Watterson <nwatters@codeaurora.org>
[rm: use iova_shift(), rewrote commit message]
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-09-27 17:09:57 +02:00
Dave Airlie
3aadb888b1 drm/tegra: Changes for v4.14-rc1
This contains a couple of fixes and improvements for host1x, with some
 preparatory work for Tegra186 support.
 
 The remainder is cleanup and minor bugfixes for Tegra DRM along with
 enhancements to debuggability.
 
 There have also been some enhancements to the kernel interfaces for
 host1x job submissions and support for mmap'ing PRIME buffers directly,
 all of which get the interfaces very close to ready for serious work.
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Merge tag 'drm/tegra/for-4.14-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v4.14-rc1

This contains a couple of fixes and improvements for host1x, with some
preparatory work for Tegra186 support.

The remainder is cleanup and minor bugfixes for Tegra DRM along with
enhancements to debuggability.

There have also been some enhancements to the kernel interfaces for
host1x job submissions and support for mmap'ing PRIME buffers directly,
all of which get the interfaces very close to ready for serious work.

* tag 'drm/tegra/for-4.14-rc1' of git://anongit.freedesktop.org/tegra/linux: (21 commits)
  drm/tegra: Prevent BOs from being freed during job submission
  drm/tegra: gem: Implement mmap() for PRIME buffers
  drm/tegra: Support render node
  drm/tegra: sor: Trace register accesses
  drm/tegra: dpaux: Trace register accesses
  drm/tegra: dsi: Trace register accesses
  drm/tegra: hdmi: Trace register accesses
  drm/tegra: dc: Trace register accesses
  drm/tegra: sor: Use unsigned int for register offsets
  drm/tegra: hdmi: Use unsigned int for register offsets
  drm/tegra: dsi: Use unsigned int for register offsets
  drm/tegra: dpaux: Use unsigned int for register offsets
  drm/tegra: dc: Use unsigned int for register offsets
  drm/tegra: Fix NULL deref in debugfs/iova
  drm/tegra: switch to drm_*_get(), drm_*_put() helpers
  drm/tegra: Set MODULE_FIRMWARE for the VIC
  drm/tegra: Add CONFIG_OF dependency
  gpu: host1x: Support sub-devices recursively
  gpu: host1x: fix error return code in host1x_probe()
  gpu: host1x: Fix bitshift/mask multipliers
  ...
2017-08-21 17:37:33 +10:00
Thierry Reding
25ae30d2a8 gpu: host1x: Support sub-devices recursively
The display architecture in Tegra186 changes slightly compared to
earlier Tegra generations, which requires that we recursively scan
host1x sub-devices from device tree.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17 17:57:08 +02:00
Gustavo A. R. Silva
7b2c63de20 gpu: host1x: fix error return code in host1x_probe()
platform_get_irq() returns an error code, but the host1x driver
ignores it and always returns -ENXIO. This is not correct and,
prevents -EPROBE_DEFER from being propagated properly.

Notice that platform_get_irq() no longer returns 0 on error:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=e330b9a6bb35dc7097a4f02cb1ae7b6f96df92af

Print and propagate the return value of platform_get_irq on failure.

This issue was detected with the help of Coccinelle.

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17 17:57:07 +02:00
Mikko Perttunen
4ac45eb8d1 gpu: host1x: Fix bitshift/mask multipliers
Some parts of Host1x uses BIT_WORD/BIT_MASK/BITS_PER_LONG to calculate
register or field offsets. This worked fine on ARMv7, but now that
BITS_PER_LONG is 64 but our registers are still 32-bit things are
broken.

Fix by replacing..
- BIT_WORD with (x / 32)
- BIT_MASK with BIT(x % 32)
- BITS_PER_LONG with 32

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17 17:57:06 +02:00
Mikko Perttunen
18b3f5ac6b gpu: host1x: Don't fail on NULL bo physical address
Pinning a Host1x BO currently cannot fail and zero is a valid address
for a BO when IOMMU is enabled. To avoid false errors remove checks
for NULL BO physical addresses.

Fixes: 404bfb78da ("gpu: host1x: Add IOMMU support")
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-08-17 17:57:06 +02:00
Dave Airlie
0c697fafc6 Linux 4.13-rc5
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Backmerge tag 'v4.13-rc5' into drm-next

Linux 4.13-rc5

There's a really nasty nouveau collision, hopefully someone can take a look
once I pushed this out.
2017-08-15 16:16:58 +10:00
Sean Paul
acadb3dddb gpu/host1x: Remove excess parameter in host1x_subdev_add docs
Fixes the following warning when building docs:
../drivers/gpu/host1x/bus.c:50: warning: Excess function parameter 'driver' description in 'host1x_subdev_add'

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170720174746.29100-4-seanpaul@chromium.org
2017-07-31 14:24:37 +02:00
Paul Kocialkowski
fea2099597 gpu: host1x: Free the IOMMU domain when there is no device to attach
When there is no device to attach to the IOMMU domain, as may be the
case when the device-tree does not contain the proper iommu node, it is
best to keep going without IOMMU support rather than failing.
This allows the driver to probe and function instead of taking down
all of the tegra drm driver, leading to missing display support.

Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Fixes: 404bfb78da ("gpu: host1x: Add IOMMU support")
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170710193305.5987-1-contact@paulk.fr
2017-07-27 16:57:34 +02:00
Dave Airlie
6d61e70ccc Linux 4.12-rc7
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Backmerge tag 'v4.12-rc7' into drm-next

Linux 4.12-rc7

Needed at least rc6 for drm-misc-next-fixes, may as well go to rc7
2017-06-27 08:28:30 +10:00
Sean Paul
b15cdca5b5 Merge remote-tracking branch 'airlied/drm-next' into drm-misc-next-fixes
Backmerging airlied/drm-next
2017-06-20 11:50:41 -04:00
Dave Airlie
4a525bad68 drm/tegra: Changes for v4.13-rc1
This starts off with the addition of more documentation for the host1x
 and DRM drivers and finishes with a slew of fixes and enhancements for
 the staging IOCTLs as a result of the awesome work done by Dmitry and
 Erik on the grate reverse-engineering effort.
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Merge tag 'drm/tegra/for-4.13-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v4.13-rc1

This starts off with the addition of more documentation for the host1x
and DRM drivers and finishes with a slew of fixes and enhancements for
the staging IOCTLs as a result of the awesome work done by Dmitry and
Erik on the grate reverse-engineering effort.

* tag 'drm/tegra/for-4.13-rc1' of git://anongit.freedesktop.org/tegra/linux:
  gpu: host1x: At first try a non-blocking allocation for the gather copy
  gpu: host1x: Refactor channel allocation code
  gpu: host1x: Remove unused host1x_cdma_stop() definition
  gpu: host1x: Remove unused 'struct host1x_cmdbuf'
  gpu: host1x: Check waits in the firewall
  gpu: host1x: Correct swapped arguments in the is_addr_reg() definition
  gpu: host1x: Forbid unrelated SETCLASS opcode in the firewall
  gpu: host1x: Forbid RESTART opcode in the firewall
  gpu: host1x: Forbid relocation address shifting in the firewall
  gpu: host1x: Do not leak BO's phys address to userspace
  gpu: host1x: Correct host1x_job_pin() error handling
  gpu: host1x: Initialize firewall class to the job's one
  drm/tegra: dc: Disable plane if it is invisible
  drm/tegra: dc: Apply clipping to the plane
  drm/tegra: dc: Avoid reset asserts on Tegra20
  drm/tegra: Check syncpoint ID in the 'submit' IOCTL
  drm/tegra: Correct copying of waitchecks and disable them in the 'submit' IOCTL
  drm/tegra: Check for malformed offsets and sizes in the 'submit' IOCTL
  drm/tegra: Add driver documentation
  gpu: host1x: Flesh out kerneldoc
2017-06-20 11:07:03 +10:00
Dmitry Osipenko
43240bbd87 gpu: host1x: At first try a non-blocking allocation for the gather copy
The blocking gather copy allocation is a major performance downside of the
Host1x firewall, it may take hundreds milliseconds which is unacceptable
for the real-time graphics operations. Let's try a non-blocking allocation
first as a least invasive solution, it makes opentegra (Xorg driver)
performance indistinguishable with/without the firewall.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:25:56 +02:00
Mikko Perttunen
8474b02531 gpu: host1x: Refactor channel allocation code
This is largely a rewrite of the Host1x channel allocation code, bringing
several changes:

- The previous code could deadlock due to an interaction
  between the 'reflock' mutex and CDMA timeout handling.
  This gets rid of the mutex.
- Support for more than 32 channels, required for Tegra186
- General refactoring, including better encapsulation
  of channel ownership handling into channel.c

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:25:38 +02:00
Dmitry Osipenko
03f0de770e gpu: host1x: Remove unused host1x_cdma_stop() definition
There is no host1x_cdma_stop() in the code, let's remove its definition
from the header file.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:25:18 +02:00
Dmitry Osipenko
03ebcaa3de gpu: host1x: Remove unused 'struct host1x_cmdbuf'
The struct host1x_cmdbuf is unused, let's remove it.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:24:59 +02:00
Dmitry Osipenko
a47ac10e6e gpu: host1x: Check waits in the firewall
Check waits in the firewall in a way it is done for relocations.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:24:41 +02:00
Dmitry Osipenko
0f563a4bf6 gpu: host1x: Forbid unrelated SETCLASS opcode in the firewall
Several channels could be made to write the same unit concurrently via
the SETCLASS opcode, trusting userspace is a bad idea. It should be
possible to drop the per-client channel reservation and add a per-unit
locking by inserting MLOCK's to the command stream to re-allow the
SETCLASS opcode, but it will be much more work. Let's forbid the
unit-unrelated class changes for now.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:23:50 +02:00
Dmitry Osipenko
ef81624994 gpu: host1x: Forbid RESTART opcode in the firewall
The RESTART opcode terminates the gather and restarts the CDMA fetching
from a specified word << 2 relative to the CDMA start address. That
shouldn't be allowed to be done by userspace.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:23:18 +02:00
Dmitry Osipenko
571cbf70c1 gpu: host1x: Forbid relocation address shifting in the firewall
Incorrectly shifted relocation address will cause a lower memory
corruption and likely a hang on a write or a read of an arbitrary data
in case of IOMMU absence. As of now, there is no known use for the
address shifting and adding a proper shifts / sizes validation is a much
more work. Let's forbid shifts in the firewall till a proper validation
is implemented.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:22:32 +02:00
Dmitry Osipenko
47f89c10dd gpu: host1x: Do not leak BO's phys address to userspace
Perform gathers coping before patching them, so that original gathers are
left untouched. That's not as bad as leaking kernel addresses, but still
doesn't feel right.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:22:03 +02:00
Dmitry Osipenko
e5855aa3e6 gpu: host1x: Correct host1x_job_pin() error handling
In case of relocations / waitchecks patching failure the jobs pins stay
referenced till DRM file get closed, wasting memory. Add the missed
unpinning.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:21:46 +02:00
Dmitry Osipenko
3833d16f16 gpu: host1x: Initialize firewall class to the job's one
The commands stream is prepended by the jobs class on the CDMA
submission, so that explicitly setting a module class in the commands
stream isn't necessary. The firewall initializes its class to 0 and the
command stream that doesn't explicitly specify the class effectively
bypasses the firewall.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Erik Faye-Lund <kusmabite@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:21:23 +02:00
Dmitry Osipenko
d0fbbdff2e drm/tegra: Correct copying of waitchecks and disable them in the 'submit' IOCTL
The waitchecks along with multiple syncpoints per submit are not ready
for use yet, let's forbid them for now.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 14:16:37 +02:00
Christophe JAILLET
59e04bc20d gpu: host1x: Fix error handling
If 'devm_reset_control_get' returns an error, then we erroneously return
success because error code is taken from 'host->clk' instead of
'host->rst'.

Fixes: b386c6b73a ("gpu: host1x: Support module reset")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170410202922.17665-1-christophe.jaillet@wanadoo.fr
2017-06-15 14:06:49 +02:00
Thierry Reding
466749f13e gpu: host1x: Flesh out kerneldoc
Improve kerneldoc for the public parts of the host1x infrastructure in
preparation for adding driver-specific part to the GPU documentation.

Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-06-15 13:58:43 +02:00
Arnd Bergmann
52499a6ad2 gpu: host1x: select IOMMU_IOVA
When IOMMU_IOVA is not built-in but host1x is, we get a link error:

drivers/gpu/host1x/dev.o: In function `host1x_remove':
dev.c:(.text.host1x_remove+0x50): undefined reference to `put_iova_domain'
drivers/gpu/host1x/dev.o: In function `host1x_probe':
dev.c:(.text.host1x_probe+0x31c): undefined reference to `init_iova_domain'
dev.c:(.text.host1x_probe+0x38c): undefined reference to `put_iova_domain'
drivers/gpu/host1x/cdma.o: In function `host1x_cdma_init':
cdma.c:(.text.host1x_cdma_init+0x238): undefined reference to `alloc_iova'
cdma.c:(.text.host1x_cdma_init+0x2c0): undefined reference to `__free_iova'
drivers/gpu/host1x/cdma.o: In function `host1x_cdma_deinit':
cdma.c:(.text.host1x_cdma_deinit+0xb0): undefined reference to `free_iova'

This adds the same select statement that we have for drm_tegra.

Fixes: 404bfb78da ("gpu: host1x: Add IOMMU support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170419182449.885312-1-arnd@arndb.de
2017-05-18 10:41:28 -04:00
Arnd Bergmann
b12f601fe5 gpu: host1x: select IOMMU_IOVA
When IOMMU_IOVA is not built-in but host1x is, we get a link error:

drivers/gpu/host1x/dev.o: In function `host1x_remove':
dev.c:(.text.host1x_remove+0x50): undefined reference to `put_iova_domain'
drivers/gpu/host1x/dev.o: In function `host1x_probe':
dev.c:(.text.host1x_probe+0x31c): undefined reference to `init_iova_domain'
dev.c:(.text.host1x_probe+0x38c): undefined reference to `put_iova_domain'
drivers/gpu/host1x/cdma.o: In function `host1x_cdma_init':
cdma.c:(.text.host1x_cdma_init+0x238): undefined reference to `alloc_iova'
cdma.c:(.text.host1x_cdma_init+0x2c0): undefined reference to `__free_iova'
drivers/gpu/host1x/cdma.o: In function `host1x_cdma_deinit':
cdma.c:(.text.host1x_cdma_deinit+0xb0): undefined reference to `free_iova'

This adds the same select statement that we have for drm_tegra.

Fixes: 404bfb78da ("gpu: host1x: Add IOMMU support")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: http://patchwork.freedesktop.org/patch/msgid/20170419182449.885312-1-arnd@arndb.de
2017-05-18 10:17:43 -04:00
Thierry Reding
b0d36daa0a gpu: host1x: Fix host1x driver shutdown
Shutting down a host1x device currently crashes if the device has failed
to probe. The root cause is that the host1x shutdown is implemented as a
struct bus_type callback, but in turn relies on the driver bound to the
device. On failure to probe, no driver will be bound and cause the code
to crash.

Fix this by moving the ->probe(), ->remove() and ->shutdown() callbacks
to the driver rather than the bus.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-05 18:11:50 +02:00
Thierry Reding
b386c6b73a gpu: host1x: Support module reset
Newer versions of Tegra come with early boot software that aggressively
puts various modules in reset. Add support to the host1x driver to take
the module out of reset on probe, and assert reset on removal.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-05 18:11:50 +02:00
Thierry Reding
7e7d432c5a gpu: host1x: Sort includes alphabetically
Sorting includes alphabetically makes it easier and less conflict-prone
to add new includes subsequently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-05 18:11:49 +02:00
Mikko Perttunen
404bfb78da gpu: host1x: Add IOMMU support
Add support for the Host1x unit to be located behind
an IOMMU. This is required when gather buffers may be
allocated non-contiguously in physical memory, as can
be the case when TegraDRM is also using the IOMMU.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-05 18:11:43 +02:00
Thierry Reding
8cadb01d2c gpu: host1x: Fix potential out-of-bounds access
The check for valid syncpoint IDs is off by one. While at it, rewrite
the check to make it more easily understandable.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-04-04 19:18:47 +02:00
Thierry Reding
7b1d418505 gpu: host1x: Set OF node for new host1x devices
We use the OF node of the host1x device's parent because it's the
closest we have.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2017-01-30 11:47:44 +01:00
Arto Merilainen
d4b5781890 gpu: host1x: Add locking to syncpt
Currently syncpoints are not locked by mutex and this causes races
if we are aggressively freeing and allocating syncpoints.

This patch adds missing mutex protection to syncpoint structures.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Shridhar Rasal <srasal@nvidia.com>
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
[treding@nvidia.com: use better label names, don't reset local variable]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-11 15:33:13 +01:00
Arto Merilainen
f08ef2d1a1 gpu: host1x: Store device address to all bufs
Currently job pinning is optimized to handle only the first buffer
using a certain host1x_bo object and all subsequent buffers using
the same host1x_bo are considered done.

In most cases this is correct, however, in case the same host1x_bo
is used in multiple gathers inside the same job, we skip also
storing the device address (physical or iova) to this buffer.

This patch reworks the host1x_job_pin() to store the device address
to all gathers.

Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-11-11 15:21:07 +01:00
Thierry Reding
87904c3e82 drm/tegra: dsi: Enhance runtime power management
The MIPI DSI output on Tegra SoCs requires some external logic to
calibrate the MIPI pads before a video signal can be transmitted. This
MIPI calibration logic requires to be powered on while the MIPI pads are
being used, which is currently done as part of the DSI driver's probe
implementation.

This is suboptimal because it will leave the MIPI calibration logic
powered up even if the DSI output is never used.

On Tegra114 and earlier this behaviour also causes the driver to hang
while trying to power up the MIPI calibration logic because the power
partition that contains the MIPI calibration logic will be powered on
by the display controller at output pipeline configuration time. Thus
the power up sequence for the MIPI calibration logic happens before
it's power partition is guaranteed to be enabled.

Fix this by splitting up the API into a request/free pair of functions
that manage the runtime dependency between the DSI and the calibration
modules (no registers are accessed) and a set of enable, calibrate and
disable functions that program the MIPI calibration logic at points in
time where the power partition is really enabled.

While at it, make sure that the runtime power management also works in
ganged mode, which is currently also broken.

Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-08-24 15:58:57 +02:00
Thierry Reding
4b92e2948f gpu: host1x: Remove useless local variable
The local 'val' variable is used to store a value and immediately return
it to its caller, and hence serves no purpose. Just drop it and directly
return the value.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:33 +02:00
Thierry Reding
9f2e57cada gpu: host1x: Constify array of action handlers
This array never needs to be modified and therefore can be read-only
data.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:31 +02:00
Thierry Reding
813a9d4ecd gpu: host1x: Remove redundant parentheses
There's no need to wrap the BIT() macro into an extra set of parentheses
because it's already implemented to use its own set.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:31 +02:00
Thierry Reding
0b8070d12e gpu: host1x: Whitespace cleanup for readability
Insert a number of blank lines in places where they increase readability
of the code. Also collapse various variable declarations to shorten some
functions and finally rewrite some code for readability.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:30 +02:00
Thierry Reding
6df633d0dc gpu: host1x: Fix a couple of checkpatch warnings
Fix a couple of occurrences where no blank line was used to separate
variable declarations from code or where block comments were wrongly
formatted.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:28 +02:00
Thierry Reding
b47a049196 gpu: host1x: syncpt: Use kcalloc() instead of kzalloc()
Use kcalloc() to allocate arrays rather than passing the product of the
size per element by the number of elements to kzalloc().

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:28 +02:00
Thierry Reding
ebb2475c47 gpu: host1x: cdma: Drop unnecessary local variable
The local 'pos' variable doesn't serve any purpose other than being a
shortcut for pb->pos, but the result doesn't remove much, so simply drop
the local variable.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:27 +02:00
Thierry Reding
e18e33afa4 gpu: host1x: channel: Use correct type
find_first_zero_bit() returns an unsigned long, so make the local
variable that stores the result the same type for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:26 +02:00
Thierry Reding
5c0d8d386b gpu: host1x: Use unsigned int consistently for IDs
IDs can never be negative so use unsigned int. In some instances an
explicitly sized type (such as u32) was used for no particular reason,
so turn those into unsigned int as well for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:24 +02:00
Thierry Reding
14c95fc896 gpu: host1x: Consistently use unsigned int for counts
The number of channels, syncpoints, bases and mlocks can never be
negative, so use unsigned int instead of int. Also make loop variables
the same type for consistency.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:23 +02:00
Bhaktipriya Shridhar
57574bd779 gpu: host1x: hw: intr_hw: Remove create_workqueue
System workqueues have been able to handle high level of concurrency
for a long time now and there's no reason to use dedicated workqueues
just to gain concurrency. Since the workqueue host->intr_wq is involved
in sync point interrupts, and sync point wait and is not being used on
a memory reclaim path, dedicated host->intr_wq has been replaced with the
use of system_wq.

Unlike a dedicated per-cpu workqueue created with create_workqueue(),
system_wq allows multiple work items to overlap executions even on
the same CPU; however, a per-cpu workqueue doesn't have any CPU
locality or global ordering guarantees unless the target CPU is
explicitly specified and thus the increase of local concurrency
shouldn't make any difference.

cancel_work_sync() has been used  in _host1x_free_syncpt_irq() to ensure
that no work is pending by the time exit path runs.

Signed-off-by: Bhaktipriya Shridhar <bhaktipriya96@gmail.com>
Acked-by: Tejun Heo <tj@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-06-23 11:59:22 +02:00
Arnd Bergmann
287980e49f remove lots of IS_ERR_VALUE abuses
Most users of IS_ERR_VALUE() in the kernel are wrong, as they
pass an 'int' into a function that takes an 'unsigned long'
argument. This happens to work because the type is sign-extended
on 64-bit architectures before it gets converted into an
unsigned type.

However, anything that passes an 'unsigned short' or 'unsigned int'
argument into IS_ERR_VALUE() is guaranteed to be broken, as are
8-bit integers and types that are wider than 'unsigned long'.

Andrzej Hajda has already fixed a lot of the worst abusers that
were causing actual bugs, but it would be nice to prevent any
users that are not passing 'unsigned long' arguments.

This patch changes all users of IS_ERR_VALUE() that I could find
on 32-bit ARM randconfig builds and x86 allmodconfig. For the
moment, this doesn't change the definition of IS_ERR_VALUE()
because there are probably still architecture specific users
elsewhere.

Almost all the warnings I got are for files that are better off
using 'if (err)' or 'if (err < 0)'.
The only legitimate user I could find that we get a warning for
is the (32-bit only) freescale fman driver, so I did not remove
the IS_ERR_VALUE() there but changed the type to 'unsigned long'.
For 9pfs, I just worked around one user whose calling conventions
are so obscure that I did not dare change the behavior.

I was using this definition for testing:

 #define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \
       unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO))

which ends up making all 16-bit or wider types work correctly with
the most plausible interpretation of what IS_ERR_VALUE() was supposed
to return according to its users, but also causes a compile-time
warning for any users that do not pass an 'unsigned long' argument.

I suggested this approach earlier this year, but back then we ended
up deciding to just fix the users that are obviously broken. After
the initial warning that caused me to get involved in the discussion
(fs/gfs2/dir.c) showed up again in the mainline kernel, Linus
asked me to send the whole thing again.

[ Updated the 9p parts as per Al Viro  - Linus ]

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Andrzej Hajda <a.hajda@samsung.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Link: https://lkml.org/lkml/2016/1/7/363
Link: https://lkml.org/lkml/2016/5/27/486
Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-05-27 15:26:11 -07:00
Linus Torvalds
266c73b777 Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie:
 "This is the main drm pull request for 4.6 kernel.

  Overall the coolest thing here for me is the nouveau maxwell signed
  firmware support from NVidia, it's taken a long while to extract this
  from them.

  I also wish the ARM vendors just designed one set of display IP, ARM
  display block proliferation is definitely increasing.

  Core:
     - drm_event cleanups
     - Internal API cleanup making mode_fixup optional.
     - Apple GMUX vga switcheroo support.
     - DP AUX testing interface

  Panel:
     - Refactoring of DSI core for use over more transports.

  New driver:
     - ARM hdlcd driver

  i915:
     - FBC/PSR (framebuffer compression, panel self refresh) enabled by default.
     - Ongoing atomic display support work
     - Ongoing runtime PM work
     - Pixel clock limit checks
     - VBT DSI description support
     - GEM fixes
     - GuC firmware scheduler enhancements

  amdkfd:
     - Deferred probing fixes to avoid make file or link ordering.

  amdgpu/radeon:
     - ACP support for i2s audio support.
     - Command Submission/GPU scheduler/GPUVM optimisations
     - Initial GPU reset support for amdgpu

  vmwgfx:
     - Support for DX10 gen mipmaps
     - Pageflipping and other fixes.

  exynos:
     - Exynos5420 SoC support for FIMD
     - Exynos5422 SoC support for MIPI-DSI

  nouveau:
     - GM20x secure boot support - adds acceleration for Maxwell GPUs.
     - GM200 support
     - GM20B clock driver support
     - Power sensors work

  etnaviv:
     - Correctness fixes for GPU cache flushing
     - Better support for i.MX6 systems.

  imx-drm:
     - VBlank IRQ support
     - Fence support
     - OF endpoint support

  msm:
     - HDMI support for 8996 (snapdragon 820)
     - Adreno 430 support
     - Timestamp queries support

  virtio-gpu:
     - Fixes for Android support.

  rockchip:
     - Add support for Innosilicion HDMI

  rcar-du:
     - Support for 4 crtcs
     - R8A7795 support
     - RCar Gen 3 support

  omapdrm:
     - HDMI interlace output support
     - dma-buf import support
     - Refactoring to remove a lot of legacy code.

  tilcdc:
     - Rewrite of pageflipping code
     - dma-buf support
     - pinctrl support

  vc4:
     - HDMI modesetting bug fixes
     - Significant 3D performance improvement.

  fsl-dcu (FreeScale):
     - Lots of fixes

  tegra:
     - Two small fixes

  sti:
     - Atomic support for planes
     - Improved HDMI support"

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (1063 commits)
  drm/amdgpu: release_pages requires linux/pagemap.h
  drm/sti: restore mode_fixup callback
  drm/amdgpu/gfx7: add MTYPE definition
  drm/amdgpu: removing BO_VAs shouldn't be interruptible
  drm/amd/powerplay: show uvd/vce power gate enablement for tonga.
  drm/amd/powerplay: show uvd/vce power gate info for fiji
  drm/amdgpu: use sched fence if possible
  drm/amdgpu: move ib.fence to job.fence
  drm/amdgpu: give a fence param to ib_free
  drm/amdgpu: include the right version of gmc header files for iceland
  drm/radeon: fix indentation.
  drm/amd/powerplay: add uvd/vce dpm enabling flag to fix the performance issue for CZ
  drm/amdgpu: switch back to 32bit hw fences v2
  drm/amdgpu: remove amdgpu_fence_is_signaled
  drm/amdgpu: drop the extra fence range check v2
  drm/amdgpu: signal fences directly in amdgpu_fence_process
  drm/amdgpu: cleanup amdgpu_fence_wait_empty v2
  drm/amdgpu: keep all fences in an RCU protected array v2
  drm/amdgpu: add number of hardware submissions to amdgpu_fence_driver_init_ring
  drm/amdgpu: RCU protected amd_sched_fence_release
  ...
2016-03-21 13:48:00 -07:00
Dave Airlie
0e5dc9a8ee drm/tegra: Changes for v4.6-rc1
Only two cleanups this time around. One fixes reference counting of
 device tree nodes, the other changes the return value of a function
 from an unsigned int to an int to reflect that it will return error
 codes.
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Merge tag 'drm/tegra/for-4.6-rc1' of http://anongit.freedesktop.org/git/tegra/linux into drm-next

drm/tegra: Changes for v4.6-rc1

Only two cleanups this time around. One fixes reference counting of
device tree nodes, the other changes the return value of a function
from an unsigned int to an int to reflect that it will return error
codes.

* tag 'drm/tegra/for-4.6-rc1' of http://anongit.freedesktop.org/git/tegra/linux:
  gpu: host1x: Use a signed return type for do_relocs()
  gpu: host1x: bus: Add missing of_node_put()
2016-03-17 08:08:57 +10:00
Markus Elfring
341917fe2b gpu: host1x: Use a signed return type for do_relocs()
The return type "unsigned int" was used by the do_relocs() function
despite the fact that it will eventually return a negative error code.
Use a signed integer instead to accomodate for error codes.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-16 13:45:44 +01:00
Amitoj Kaur Chawla
93ec302976 gpu: host1x: bus: Add missing of_node_put()
for_each_child_of_node() performs an of_node_get() on each iteration, so
to break out of the loop an of_node_put() is required.

Found using Coccinelle. The semantic patch used for this is as follows:

// <smpl>
@@
expression e;
local idexpression n;
@@

 for_each_child_of_node(..., n) {
   ... when != of_node_put(n)
       when != e = n
(
   return n;
|
+  of_node_put(n);
?  return ...;
)
   ...
 }
// </smpl>

Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-16 13:45:43 +01:00
Luis R. Rodriguez
f6e45661f9 dma, mm/pat: Rename dma_*_writecombine() to dma_*_wc()
Rename dma_*_writecombine() to dma_*_wc(), so that the naming
is coherent across the various write-combining APIs. Keep the
old names for compatibility for a while, these can be removed
at a later time. A guard is left to enable backporting of the
rename, and later remove of the old mapping defines seemlessly.

Build tested successfully with allmodconfig.

The following Coccinelle SmPL patch was used for this simple
transformation:

@ rename_dma_alloc_writecombine @
expression dev, size, dma_addr, gfp;
@@

-dma_alloc_writecombine(dev, size, dma_addr, gfp)
+dma_alloc_wc(dev, size, dma_addr, gfp)

@ rename_dma_free_writecombine @
expression dev, size, cpu_addr, dma_addr;
@@

-dma_free_writecombine(dev, size, cpu_addr, dma_addr)
+dma_free_wc(dev, size, cpu_addr, dma_addr)

@ rename_dma_mmap_writecombine @
expression dev, vma, cpu_addr, dma_addr, size;
@@

-dma_mmap_writecombine(dev, vma, cpu_addr, dma_addr, size)
+dma_mmap_wc(dev, vma, cpu_addr, dma_addr, size)

We also keep the old names as compatibility helpers, and
guard against their definition to make backporting easier.

Generated-by: Coccinelle SmPL
Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: airlied@linux.ie
Cc: akpm@linux-foundation.org
Cc: benh@kernel.crashing.org
Cc: bhelgaas@google.com
Cc: bp@suse.de
Cc: dan.j.williams@intel.com
Cc: daniel.vetter@ffwll.ch
Cc: dhowells@redhat.com
Cc: julia.lawall@lip6.fr
Cc: konrad.wilk@oracle.com
Cc: linux-fbdev@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: luto@amacapital.net
Cc: mst@redhat.com
Cc: tomi.valkeinen@ti.com
Cc: toshi.kani@hp.com
Cc: vinod.koul@intel.com
Cc: xen-devel@lists.xensource.com
Link: http://lkml.kernel.org/r/1453516462-4844-1-git-send-email-mcgrof@do-not-panic.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-03-09 14:57:51 +01:00
Alexandre Courbot
c95469aa5a gpu: host1x: Set DMA ops on device creation
Currently host1x-instanciated devices have their dma_ops left to NULL,
which makes any DMA operation (like buffer import) on ARM64 fallback
to the dummy_dma_ops and fail with an error.

This patch calls of_dma_configure() with the host1x node when creating
such a device, so the proper DMA operations are set.

Suggested-by: Thierry Reding <thierry.reding@gmail.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-04 16:24:57 +01:00
Alexandre Courbot
097452e613 gpu: host1x: Set DMA mask
The default DMA mask covers a 32 bits address range, but host1x devices
can address a larger range on TK1 and TX1. Set the DMA mask to the range
addressable when we use the IOMMU to prevent the use of bounce buffers.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-03-04 16:24:56 +01:00
Thierry Reding
a134789a67 gpu: host1x: Add Tegra210 support
The host1x unit found in Tegra210 SoCs is very similar to the unit in
Tegra124, but it has 2 additional channels for a total of 14 channels.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14 10:50:33 +01:00
Thierry Reding
e3e70814ce gpu: host1x: Remove core driver on unregister
When unregistering a host1x driver, make sure to unregister the core
driver as well to prevent it from sticking around and oppose reloading
of the driver.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14 10:50:33 +01:00
Thierry Reding
28fae81f93 gpu: host1x: Use platform_register/unregister_drivers()
These new helpers simplify implementing multi-driver modules and
properly handle failure to register one driver by unregistering all
previously registered drivers.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-12-14 10:50:32 +01:00
Dmitry Osipenko
3fe2c7d4c8 gpu: host1x: Fix MLOCK's debug info
MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK
owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted
value, while unshifted should be used. Fix it by changing '_F' to '_V'.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-By: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-10-02 14:40:12 +02:00
Thierry Reding
15372d4be7 gpu: host1x: mipi: Power down regulators when unused
Keep track of the number of users of DSI and CSI pads and power down the
regulators that supply the bricks when all users are gone.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:21 +02:00
Thierry Reding
5e7752436e gpu: host1x: mipi: Add Tegra210 support
Some changes are needed to the configuration settings for some lanes. In
addition, the clock lanes for the CSI pads can no longer be calibrated.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:20 +02:00
Thierry Reding
7fd3ecad3f gpu: host1x: mipi: Add Tegra132 support
While Tegra132 has the same pads as Tegra124, some configuration values
need to be programmed slightly differently.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:19 +02:00
Thierry Reding
c22fb79099 gpu: host1x: mipi: Constify OF match table
This table is never modified and can therefore reside in read-only
memory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:18 +02:00
Thierry Reding
2ed264bf91 gpu: host1x: mipi: Clear calibration status
Before starting a new calibration cycle, make sure to clear the current
status by writing a 1 to the various "calibration done" bits.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:17 +02:00
Thierry Reding
8ed5c06232 gpu: host1x: mipi: Fix clock lane register for DSI
Use more consistent names for the clock lane configuration registers and
fix the offset of the upper clock lane configuration register for the
first DSI pad.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:16 +02:00
Thierry Reding
83a3c223cc gpu: host1x: mipi: Parameterize to support future SoCs
Parameterize more of the register programming to accomodate for changes
required by future SoC generations.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-08-13 13:47:15 +02:00
Thierry Reding
b4a20144e0 gpu: host1x: Export host1x_syncpt_read()
This function is used to read the current value of the syncpt and is
useful in situations where drivers don't schedule work and wait for the
syncpoint to increment. One particular use-case is using the syncpoint
as a VBLANK counter.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-04-02 18:46:20 +02:00
Thierry Reding
f4c5cf88fb gpu: host1x: Provide a proper struct bus_type
Previously the struct bus_type exported by the host1x infrastructure was
only a very basic skeleton. Turn that implementation into a more full-
fledged bus to support proper probe ordering and power management.

Note that the bus infrastructure needs to be available before any of the
drivers can be registered. This is automatically ensured if all drivers
are built as loadable modules (via symbol dependencies). If all drivers
are built-in there are no such guarantees and the link order determines
the initcall ordering. Adjust drivers/gpu/Makefile to make sure that the
host1x bus infrastructure is initialized prior to any of its users (only
drm/tegra currently).

v2: Fix building host1x and tegra-drm as modules
    Reported-by: Dave Airlie <airlied@gmail.com>

Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Mark Zhang <markz@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-27 10:09:14 +01:00
Thierry Reding
99d2cd81d7 gpu: host1x: Factor out __host1x_device_del()
This function is needed in several places, so factor it out.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-23 12:07:01 +01:00
Thierry Reding
38d98de433 gpu: host1x: Call host1x_device_add() under lock
Instead of locking within host1x_device_add(), call it under the lock to
make the locking more consistent.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-23 12:07:01 +01:00
Thierry Reding
536e171522 gpu: host1x: Call ->remove() only when a device is bound
When a driver's ->probe() function fails, the host1x bus must not call
its ->remove() function because the driver will already have cleaned up
in the error handling path in ->probe().

Signed-off-by: Thierry Reding <treding@nvidia.com>
2015-01-23 12:07:00 +01:00
Sean Paul
b298e98ef6 gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 register
During calibration, sets the "internal reference level for drive pull-
down" to the value specified in the Tegra TRM.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:57 +01:00
Sean Paul
08a15cc34d gpu: host1x: mipi: Calibrate clock lanes
Include the clock lanes when calibrating the MIPI PHY on Tegra124
compatible devices.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
[treding@nvidia.com: bikeshedding]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:54 +01:00
Sean Paul
26f7a92a3a gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRL
By paving the CTRL reg value, the current code changes MIPI_CAL_PRESCALE
("Auto-cal calibration step prescale") from 1us to 0.1us (val=0). In the
description for PHY's noise filter (MIPI_CAL_NOISE_FLT), the TRM states
that if the value of the prescale is 0 (or 0.1us), the filter should be
set between 2-5. However, the current code sets it to 0.

For now, let's keep the prescale and filter values as-is, which is most
likely the power-on-reset values of 0x2 and 0xa, respectively.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:51 +01:00
Thierry Reding
57b17ae71f gpu: host1x: mipi: Registers are 32 bits wide
On 64-bit platforms an unsigned long would be 64 bit and cause
unnecessary casting when being passed to writel() or returned from
readl(). Make register values 32 bits wide to avoid that.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:48 +01:00
Thierry Reding
3880e95f27 gpu: host1x: Make gather offsets unsigned
Use the u32 type for the offset in the host1x_job_gather structure for
consistentcy with other structures. Negative offsets don't make sense in
this context.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:44 +01:00
Thierry Reding
ba73fbc2ca gpu: host1x: Print address/offset pairs consistently
Consistently use a format of %pad+%#x to print address/offset in debug
messages.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:41 +01:00
Thierry Reding
7f27d60b28 gpu: host1x: Fix typo in comment
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:38 +01:00
Thierry Reding
0169b93f44 gpu: host1x: Make mapped field of push buffers void *
This reduces the amount of casting that needs to be done to get rid of
annoying warnings on 64-bit builds.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:35 +01:00
Thierry Reding
b40d02bf96 gpu: host1x: Use struct host1x_bo pointers in traces
Rather than cast to a u32 use the struct host1x_bo pointers directly.
This avoid annoying warnings for 64-bit builds.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-13 16:11:32 +01:00
Thierry Reding
961e3beae3 drm/tegra: Make job submission 64-bit safe
Job submission currently relies on the fact that struct drm_tegra_reloc
and struct host1x_reloc are the same size and uses a simple call to the
copy_from_user() function to copy them to kernel space. This causes the
handle to be stored in the buffer object field, which then needs a cast
to a 32 bit integer to resolve it to a proper buffer object pointer and
store it back in the buffer object field.

On 64-bit architectures that will no longer work, since pointers are 64
bits wide whereas handles will remain 32 bits. This causes the sizes of
both structures to because different and copying will no longer work.

Fix this by adding a new function, host1x_reloc_get_user(), that copies
the structures field by field.

While at it, use substructures for the command and target buffers in
struct host1x_reloc for better readability. Also use unsized types to
make it more obvious that this isn't part of userspace ABI.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-08-04 10:07:36 +02:00
Thierry Reding
0c7dfd36b7 gpu: host1x: Rename internal functions for clarity
The internal host1x_{,un}register_client() functions can potentially be
confused with public the host1x_client_{,un}register() functions.

Rename them to host1x_{add,del}_client() to remove some of the possible
confusion.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-06-05 23:10:30 +02:00
Stephen Warren
22bbd5d949 gpu: host1x: handle the correct # of syncpt regs
BIT_WORD() truncates rather than rounds, so the loops in
syncpt_thresh_isr() and _host1x_intr_disable_all_syncpt_intrs() use <=
rather than < in an attempt to process the correct number of registers
when rounding of the conversion of count of bits to count of words is
necessary. However, when rounding isn't necessary because the value is
already a multiple of the divisor (as is the case for all values of
nb_pts the code actually sees), this causes one too many registers to
be processed.

Solve this by using and explicit DIV_ROUND_UP() call, rather than
BIT_WORD(), and comparing with < rather than <=.

Fixes: 7ede0b0bf3 ("gpu: host1x: Add syncpoint wait and interrupts")
Cc: <stable@vger.kernel.org> # 3.10
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-16 17:11:04 +02:00
Dave Airlie
82c68b6ccd drm/tegra: Changes for v3.15-rc1
Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap()
 operations.
 
 A symbol that is required for upcoming V4L2 support is now exported by
 the host1x driver.
 
 Relicense drivers under the GPL v2 for consistency. One exception is the
 public header file, which is relicensed under MIT to abide by the common
 rule.
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Merge tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux into drm-next

drm/tegra: Changes for v3.15-rc1

Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap()
operations.

A symbol that is required for upcoming V4L2 support is now exported by
the host1x driver.

Relicense drivers under the GPL v2 for consistency. One exception is the
public header file, which is relicensed under MIT to abide by the common
rule.

* tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux:
  drm/tegra: Use standard GPL v2 license text
  drm/tegra: Relicense under GPL v2
  drm/tegra: Relicense public header under MIT
  drm/tegra: Add eDP support
  gpu: host1x: export host1x_syncpt_incr_max() function
  drm/tegra: prime: Add vmap support
2014-04-05 16:13:08 +10:00
Bryan Wu
64400c3791 gpu: host1x: export host1x_syncpt_incr_max() function
Tegra V4L2 camera driver needs this function to do frame capture.

Signed-off-by: Bryan Wu <pengw@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-04-04 09:12:49 +02:00
Erik Faye-Lund
89e6e8c85f gpu: host1x: do not check previously handled gathers
When patching gathers, we don't need to check against
gathers with lower indices than the current one, as
they are guaranteed to already have been handled.

Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com>
Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-02-12 07:50:37 +01:00
Thierry Reding
be2cd59b80 gpu: host1x: Remove unnecessary include
Nothing from the asm/mach/irq.h header is needed in this file, so there
is no need to include it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-01-14 14:39:45 +01:00
Thierry Reding
e6fff4aaf9 gpu: host1x: Add Tegra124 support
Tegra124 has 192 syncpoints whereas its predecessors had 32 syncpoints.
This required changes to the hardware register layout.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:52 +01:00
Thierry Reding
8e0d788c6f gpu: host1x: Fix build warnings
When debugfs support isn't enabled, gcc complains about some variables
being unused. To avoid further #ifdefery, move debugfs specific setup
code into static functions and use IS_ENABLED(CONFIG_DEBUG_FS) to have
the compiler, rather than the preprocessor, discard them when unused.
The advantage of doing it this way is that all the code will be
compile-tested whether or not debugfs support is enabled.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:52 +01:00
Thierry Reding
6f44c2b528 gpu: host1x: Increase compile test coverage
The ARCH_MULTIPLATFORM dependency was introduced back when Tegra didn't
support multiplatform yet as a means to allow the driver to be easily
compile-tested along with other DRM drivers. In the meantime, the new
COMPILE_TEST Kconfig option has been introduced for exactly that
purpose, so use that instead to clarify the intention.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:51 +01:00
Thierry Reding
aef03d3fa5 gpu: host1x: Fix more sparse warnings
Include the linux/host1x.h and dev.h headers so that function prototypes
are visible to keep sparse from suggesting that their implementations be
made static.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:51 +01:00
Thierry Reding
18b94f1cfb gpu: host1x: Use the correct HW headers for host1x02
An earlier patch added a subset of the required HW specific header files
but didn't actually include the right ones when compiling for host1x02.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:51 +01:00
Thierry Reding
fae798a156 gpu: host1x: Export public API
Make the public API symbols visible so that depending drivers can be
built as a module.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:50 +01:00
Thierry Reding
4de6a2d6ac gpu: host1x: Add MIPI pad calibration support
This driver adds support to perform calibration of the MIPI pads for CSI
and DSI.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-19 09:29:43 +01:00
Thierry Reding
d24b2898ce gpu: host1x: Fix a few sparse warnings
Include the bus.h header, so that various function declarations are
visible in the source file that implements those functions. This keeps
sparse from suggesting that they should be made static.

Make the host1x_bus_type variable static since it isn't used globally.

Finally replace the slightly unsafe dev_set_name(dev, name) by the more
secure dev_set_name(dev, "%s", name).

Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-12-03 10:06:29 +01:00
Olof Johansson
43dd5554fc gpu: host1x: Silence a few warnings with LPAE=y
When building with LPAE=y (64-bit dma_addr_t), the following warnings are seen:

drivers/gpu/host1x/hw/cdma_hw.c:57:3: warning: format '%x' expects
  argument of type 'unsigned int', but argument 5 has type 'dma_addr_t'

drivers/gpu/host1x/hw/debug_hw.c:167:10: warning: format '%x' expects
  argument of type 'unsigned int', but argument 3 has type 'dma_addr_t'

The agreed-to solution for this is upcast to u64 and using %llx.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-11-28 15:13:47 +01:00
Arto Merilainen
f5a954fed9 gpu: host1x: Add syncpoint base support
This patch adds support for hardware syncpoint bases. This creates
a simple mechanism to stall the command FIFO until an operation is
completed.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:48 +01:00
Arto Merilainen
8736fe8153 gpu: host1x: Add 'flags' field to syncpt request
Functions host1x_syncpt_request() and _host1x_syncpt_alloc() have
been taking a separate boolean flag ('client_managed') for indicating
if the syncpoint value should be tracked by the host1x driver.

This patch converts the field into generic 'flags' field so that
we can easily add more information while requesting a syncpoint.
Clients are adapted to use the new interface accordingly.

Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:47 +01:00
Wei Yongjun
9c78c4c38e gpu: host1x: Disable clock on probe failure
Add a missing clk_disable_unprepare() before returning from the driver's
.probe() function on error.

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2013-10-31 09:55:46 +01:00