Change the READ/WRITE to FSL_READ/FSL_WRITE to resolve any possible
namespace collisions with READ/WRITE macros (e.g., from <linux/fs.h>).
Problems have been seen, for example, on mips:
>> drivers/mtd/spi-nor/fsl-quadspi.c:186:5: error: 'LUT_0' undeclared (first use in this function)
((LUT_##ins) << INSTR0_SHIFT))
^
>> drivers/mtd/spi-nor/fsl-quadspi.c:188:30: note: in expansion of macro 'LUT0'
On SPARC:
drivers/mtd/spi-nor/fsl-quadspi.c: In function 'fsl_qspi_init_lut':
drivers/mtd/spi-nor/fsl-quadspi.c:369:1: error: 'LUT_0' undeclared (first use in this function)
drivers/mtd/spi-nor/fsl-quadspi.c:418:1: error: pasting "LUT_" and "(" does not give a valid preprocessing token
drivers/mtd/spi-nor/fsl-quadspi.c:418:2: error: implicit declaration of function 'LUT_'
And surely on others.
Fixes: d26a22d067 ("mtd: fsl-quadspi: allow building for other ARCHes with COMPILE_TEST")
Reported-by: Guenter Roeck <linux@roeck-us.net>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Han Xu <b45815@freescale.com>
[Brian: rewrote commit description]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Building for x86 results in the following build errors:
drivers/mtd/spi-nor/fsl-quadspi.c: In function 'fsl_qspi_init_lut':
>> drivers/mtd/spi-nor/fsl-quadspi.c:355:21: error: 'SZ_16M' undeclared (first use in this function)
if (q->nor_size <= SZ_16M) {
^
drivers/mtd/spi-nor/fsl-quadspi.c:355:21: note: each undeclared identifier is reported only once for each function it appears in
drivers/mtd/spi-nor/fsl-quadspi.c: In function 'fsl_qspi_read':
>> drivers/mtd/spi-nor/fsl-quadspi.c:208:27: error: 'SZ_4M' undeclared (first use in this function)
#define QUADSPI_MIN_IOMAP SZ_4M
^
>> drivers/mtd/spi-nor/fsl-quadspi.c:845:25: note: in expansion of macro 'QUADSPI_MIN_IOMAP'
q->memmap_len = len > QUADSPI_MIN_IOMAP ? len : QUADSPI_MIN_IOMAP;
Explicitly include <linux/sizes.h> to fix the problem.
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This driver doesn't actually need ARCH_MXC to compile. Relax the
constraints.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Han xu <han.xu@freescale.com>
Seen when compile-testing on non-32-bit arch:
CC drivers/mtd/spi-nor/fsl-quadspi.o
drivers/mtd/spi-nor/fsl-quadspi.c: In function 'fsl_qspi_read':
drivers/mtd/spi-nor/fsl-quadspi.c:873:2: warning: format '%d' expects argument of type 'int', but argument 6 has type 'size_t' [-Wformat=]
dev_dbg(q->dev, "cmd [%x],read from 0x%p, len:%d\n",
^
Also drop the '0x' prefixing to the '%p' formatter, since %p already
knows how to format pointers appropriately.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Han xu <han.xu@freescale.com>
Many other flash share the same features as ST Micro. I've tested some
Winbond flash, so add them.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This enables ioctl(MEMISLOCKED). Status can now be reported in the
mtdinfo or flash_lock utilities found in mtd-utils.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This code was a bit sloppy, would produce a lot of copy-and-paste, and
did not always provide a sensible interface:
* It didn't validate the length for LOCK and the offset for UNLOCK, so
we were essentially discarding half of the user-supplied data and
assuming what they wanted to lock/unlock
* It didn't do very good error checking
* It didn't make use of the fact that this operation works on
power-of-two dimensions
So, rewrite this to do proper bit arithmetic rather than a bunch of
hard-coded condition tables. Now we have:
* More comments on how this was derived
* Notes on what is (and isn't) supported
* A more exendible function, so we could add support for other
protection ranges
* More accurate locking - e.g., suppose the top quadrant is locked (75%
to 100%); then in the following cases, case (a) will succeed but (b)
will not (return -EINVAL):
(a) user requests lock 3rd quadrant (50% to 75%)
(b) user requests lock 3rd quadrant, minus a few blocks (e.g., 50%
to 73%)
Case (b) *should* fail, since we'd have to lock blocks that weren't
requested. But the old implementation didn't know the difference and
would lock the entire second half (50% to 100%)
This refactoring work will also help enable the addition of
mtd_is_locked() support and potentially the support of bottom boot
protection (TB=1).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The N25Q032A is identical to the N25Q032 except it has a different
supply voltage range. Therefore, it has a new JEDEC ID.
Signed-off-by: Aurelien Chanot <chanot.a@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
This patch fixes timeout issues seen on large NOR flash (e.g., 16MB
w25q128fw) when using ioctl(MEMERASE) with offset=0 and length=16M. The
input parameters matter because spi_nor_erase() uses a different code
path for full-chip erase, where we use the SPINOR_OP_CHIP_ERASE (0xc7)
opcode.
Fix: use a different timeout for full-chip erase than for other
commands.
While most operations can be expected to perform relatively similarly
across a variety of NOR flash types and sizes (and therefore might as
well use a similar timeout to keep things simple), full-chip erase is
unique, because the time it typically takes to complete:
(1) is much larger than most operations and
(2) scales with the size of the flash.
Let's base our timeout on the original comments stuck here -- that a 2MB
flash requires max 40s to erase.
Small survey of a few flash datasheets I have lying around:
Chip Size (MB) Max chip erase (seconds)
---- -------- ------------------------
w25q32fw 4 50
w25q64cv 8 30
w25q64fw 8 100
w25q128fw 16 200
s25fl128s 16 ~256
s25fl256s 32 ~512
From this data, it seems plenty sufficient to say we need to wait for
40 seconds for each 2MB of flash.
After this change, it might make some sense to decrease the timeout for
everything else, as even the most extreme operations (single block
erase?) shouldn't take more than a handful of seconds. But for safety,
let's leave it as-is. It's only an error case, after all, so we don't
exactly need to optimize it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
It is a 512KiB flash with 4 KiB erase sectors.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
s25fl016k can be found on Embedded Artists' LPC4357 Developer's Kit
where is used in quad mode by the LPC4357 SPIFI controller.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The 'write_enable' argument is unused and unneeded, so remove it from
the API.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Han Xu <han.xu@freescale.com>
[Brian: fixed for nxp-spifi.c]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Use existing write_sr() call instead of decoding and
calling nor->write_reg separately.
Signed-off-by: Jagan Teki <jteki@openedev.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The problem this patch is trying to address is such, that SPI NOR flash
devices attached to a dedicated SPI NOR controller cannot read their
properties from the associated struct device_node.
A couple of facts first:
1) Each SPI NOR flash has a struct spi_nor associated with it.
2) Each SPI NOR flash has certain device properties associated
with it, for example the OF property 'm25p,fast-read' is a
good pick. These properties are used by the SPI NOR core to
select which opcodes are sent to such SPI NOR flash. These
properties are coming from spi_nor .dev->of_node .
The problem is, that for SPI NOR controllers, the struct spi_nor .dev
element points to the struct device of the SPI NOR controller, not the
SPI NOR flash. Therefore, the associated dev->of_node also is the
one of the controller and therefore the SPI NOR core code is trying to
parse the SPI NOR controller's properties, not the properties of the
SPI NOR flash.
Note: The m25p80 driver is not affected, because the controller and
the flash are the same device, so the associated device_node
of the controller and the flash are the same.
This patch adjusts the SPI NOR core such that the device_node is not
picked from spi_nor .dev directly, but from a new separate spi_nor
.flash_node element. This let's the SPI NOR controller drivers set up
a different spi_nor .flash_node element for each SPI NOR flash.
This patch also fixes the controller drivers to be compatible with
this modification and correctly set the spi_nor .flash_node element.
This patch is inspired by 5844feeaa4
mtd: nand: add common DT init code
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We don't really need the flash information from the device tree here.
Let's stick with autodetection here instead.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Acked-by: Han Xu <han.xu@freescale.com>
Tested-by: Han Xu <han.xu@freescale.com>
This reflects the proper layering, so let's do it.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Layering suggests that the SPI NOR layer (not the hardware driver)
should be initializing the MTD layer.
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Tested-by: Joachim Eastwood <manabian@gmail.com>
This chip can be found on Hitex LPC4350 Evaluation Board.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
According to the datasheet[1], both S25FL129P0 (256kB sectors) and
S25FL129P1 (64kB sectors) support dual read, quad read, dual i/o read
and quad i/o read.
I have verified dual read to be working for S25FL129P1 on a dual
capable spi controller. Quad as well as S25FL129P0 is untested, lacking
hardware to verify.
[1] http://www.spansion.com/Support/Datasheets/S25FL129P_00.pdf
Signed-off-by: Jonas Gorski <jogo@openwrt.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
It is a 256KiB flash with 4 KiB erase sectors
and 64KiB overlay blocks.
This is the one available on Hardkernel's Odroid U3 shield.
Signed-off-by: Alexis Ballier <aballier@gentoo.org>
[Brian: seems like this does NOT require the usual SST_WRITE hacks]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add Micron (n25q064a) 8MB flash to the list of supported chips.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
[Brian: fixup context]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Using struct spi_device_id for storing list of flash devices comes from
early SPI NOR framework days. Thanks to the commit 70f3ce0510 ("mtd:
spi-nor: make spi_nor_scan() take a chip type name, not spi_device_id")
we can stop using spi_device_id and just switch to our own struct.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The current "We only connect the NOR to this controller now." text
is not very clear, so explain it better by saying that generic SPI
is not supported by SPI_FSL_QUADSPI and only SPI NOR is.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add SPI-NOR driver for the SPI Flash Interface (SPIFI)
controller that is found on newer NXP MCU devices.
The controller supports serial SPI Flash devices with 1-, 2-
and 4-bit width in either SPI mode 0 or 3. The controller
can operate in either command or memory mode. In memory mode
the Flash is exposed as normal memory and can be directly
accessed by the CPU.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Erase function will use cmd 0x20 (SPINOR_OP_BE_4K) if kenrel enable option
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
This command is not in fsl-quadspi driver LUT. So driver continue report
fsl-quadspi 21e0000.qspi: Unsupported cmd 0x20.
This patch fix this issue.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Acked-by: Han Xu <Han.xu@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
The uboot may run the QuadSpi controler with command:
#sf probe
So we should reset the module in the probe.
This patch also clear the pending interrupts which arised by the uboot
code.
Signed-off-by: Huang Shijie <shijie8@gmail.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
QSPI1 cannot wake up CCM from WAIT mode on SX ARD board, add pmqos to
let PM NOT enter WAIT mode when accessing QSPI1, refer to TKT245618.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Han Xu <Han.xu@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
We found there is a low probability(5%) QSPI access timeout issue,
usually it happened on kernel boot stage, the first time kernel tried to
access QSPI chip. The READ_ID command was sent but not executed,
consequently the probe function failed.
The root cause is that the divider is not glitchless in i.MX6SX chip.
If qspi clock enabled then change clock frequency by call clk_set_rate,
there will be glitch at low possiblity rate and pass to qspi controller.
The controler will be hang by this glitch.
Based on the new clock flag(CLK_SET_RATE_GATE) and new framework, we
need to change the approach of seting clock rate.
1. Disable clock.
2. call clk_set_rate.
3. Enable clock again.
Signed-off-by: Han Xu <han.xu@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add i.mx6ul chip support
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Acked-by: Han xu <han.xu@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Support i.mx7d.
quadspi in i.mx7d increase rxfifo.
require fill at least 16byte to trigger data transfer.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Han Xu <han.xu@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
add several quirk to distinguish different version of qspi module.
Signed-off-by: Han Xu <han.xu@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
QSPI may failed to map enough memory (256MB) for AHB read in
previous implementation, especially in 3G/1G memory layout kernel.
Dynamically map memory to avoid such issue.
This implementation generally map QUADSPI_MAX_IOMAP (default 4MB) memory
for AHB read, it should be enough for common scenarios, and the side
effect (0.6% performance drop) is minor.
Previous implementation
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=1K count=32K
32768+0 records in
32768+0 records out
33554432 bytes (34 MB) copied, 2.16006 s, 15.5 MB/s
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=32M count=1
1+0 records in
1+0 records out
33554432 bytes (34 MB) copied, 1.43149 s, 23.4 MB/s
After applied the patch
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=1K count=32K
32768+0 records in
32768+0 records out
33554432 bytes (34 MB) copied, 2.1743 s, 15.4 MB/s
root@imx6qdlsolo:~# dd if=/dev/mtd0 of=/dev/null bs=32M count=1
1+0 records in
1+0 records out
33554432 bytes (34 MB) copied, 1.43158 s, 23.4 MB/s
Signed-off-by: Han Xu <han.xu@freescale.com>
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
When we added the "jedec,spi-nor" compatible string for use in this
driver, we added it as a modalias option. The modalias can be derived in
different ways for platform devices vs. device tree (of_*) matching. But
for device tree matching (the primary target of this identifier string),
the modalias is determined from the first entry in the 'compatible'
property. IOW, the following properties would bind to this driver:
// Option (a), modalias = "spi-nor"
compatible = "jedec,spi-nor";
// Option (b), modalias = "spi-nor"
compatible = "idontknowwhatimdoing,spi-nor";
But the following would not:
// Option (c), modalias = "shinynewdevice"
compatible = "myvendor,shinynewdevice", "jedec,spi-nor";
So, we'd like to match (a) and (c) (even when we don't have an explicit
entry for "shinynewdevice"), and we'd rather not allow (b).
To do this, we
(1) always (for devices without specific platform data) pass the
modalias to the spi-nor library;
(2) rework the spi-nor library to not reject "bad" names, and
instead just fall back to autodetection; and
(3) add the .of_match_table to properly catch all "jedec,spi-nor".
This allows (a) and (c) without warnings, and rejects (b).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
QUADSPI_MCR_CLR_TXF_MASK is the correct mask for clearing the TX FIFO.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Add supports for simultaneous access to multiple chips. Need to lock
the mutex before any quad spi operations and unlock the mutex after
operations complete.
Signed-off-by: Han Xu <b45815@freescale.com>
[Brian: reworked err path in fsl_qspi_prep()]
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Few recently added entries are missing SECT_4K flag despite of these
flashes supporting 4 KiB erase sectors and 0x20 erase command.
Also add a comment to help avoiding such mistakes in the future.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Cc: Knut Wohlrab <knut.wohlrab@de.bosch.com>
Cc: Huang Shijie <shijie.huang@intel.com>
Cc: Shengzhou Liu <shengzhou.liu@freescale.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
of_device_id is always used as const.
(See driver.of_match_table and open firmware functions)
Signed-off-by: Fabian Frederick <fabf@skynet.be>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
