Commit Graph

51422 Commits

Author SHA1 Message Date
mark mcgarrity
c00800c46e drm/amd/display: 3.2.17
Signed-off-by: mark mcgarrity <mark.mcgarrity@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-06 13:30:36 -05:00
Murton Liu
e6d2421343 drm/amd/display: PIP overlay corruption
[Why]
When moving mouse onto or off of pip plane,
screen would flash briefly due to garbage negative
pos values being programmed for cursor.
Also, text flashes due to PIP flips taking too long.

[How]
When negative pos value seen, default to 0 and adjust by modifying cursor hotspot.
For flip issue, only do post update when optimize required vs all the time.

Signed-off-by: Murton Liu <murton.liu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-06 13:30:28 -05:00
Anthony Koo
de00d253bc drm/amd/display: link_rate_set should index into table
[Why]
Current implementation that maps link_rate_set value to
actual link rate is incorrect.

[How]
Fix this implementation, such that link_rate_set indexes into
the supported_link_rate table.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Acked-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-06 13:30:21 -05:00
Eryk Brol
00fbeb4e2f drm/amd/display: DC VM Fixes
[Why]
VM_helper needs to be intialized with the dc struct in order to fix
an unallocated memory issue. System aperture settings should be
initialized to 0 and guarded with a check to make sure vm_config
is valid.

[How]
Allocate and free memory for vm_helper with other dc members.
Check whether the vm_config valid bit is set before initializing
aperture settings.

Signed-off-by: Eryk Brol <eryk.brol@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-06 13:30:12 -05:00
Wesley Chalmers
b9d4b33059 drm/amd/display: Disable Stutter for Stereo 3D
[WHY]
Bandwidth calculation formulas currently do not take Stereo 3D + Stutter
properly into account. Disable stutter feature when we detect a Stereo
3D mode as a temporary workaround.

Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Martin Leung <Martin.Leung@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-06 13:30:04 -05:00
Yongqiang Sun
810ece19ee drm/amd/display: Calc vline position in dc.
We need to calcualte vline position in DC for DCN.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-06 13:29:56 -05:00
Jerry (Fangzhi) Zuo
3f01f098a4 drm/amd/display: Clear dc_sink after it gets released
[Why]
The dc_sink was released but the pointer on the aconnector was
not cleared.

[How]
Clear it.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-06 13:29:48 -05:00
Nicholas Kazlauskas
5062b797db drm/amd/display: Don't re-program planes for DPMS changes
[Why]
There are opt1c lock warnings and CRTC read timeouts when running the
"igt@kms_plane@plane-position-hole-dpms-pipe-*" tests. These are
caused by trying to reprogram planes that are not in the current
context.

DPMS off removes the stream from the context. In this case:

new_crtc_state->active_changed = true
new_crtc_state->mode_changed = false

The planes are reprogrammed before the stream is removed from the
context because stream_state->mode_changed = false.

For DPMS adds the stream and planes back to the context:

new_crtc_state->active_changed = true
new_crtc_state->mode_changed = false

The planes are also reprogrammed here before the stream is added to the
context because stream_state->mode_changed = true. They were not
previously in the current context so warnings occur here.

[How]
Set stream_state->mode_changed = true when
new_crtc_state->active_changed = true too.

This prevents reprogramming before the context is applied in DC. The
programming will be done after the context is applied.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-06 13:29:39 -05:00
Pratik Vishwakarma
ba345a0242 drm/amdgpu/display: fix compiler errors [-Werror,-Wparentheses-equality]
Remove extraneous parentheses around the comparison
to silence this warning

Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-06 13:29:19 -05:00
Nicholas Kazlauskas
77476360f1 drm/amd/display: Disconnect mpcc when changing tg
[Why]
This fixes an mpc programming error for the following sequence of
atomic commits when pipe split is enabled:

Commit 1: CRTC0 (plane 4, plane 3)

Pipe 0: old_plane_state = A0, new_plane_state = A1,   new_tg = T0
Pipe 1: old_plane_state = B0, new_plane_state = B1,   new_tg = T0
Pipe 2: old_plane_state = A0, new_plane_state = A1,   new_tg = T0
Pipe 3: old_plane_state = B0, new_plane_state = B1,   new_tg = T0

Commit 2: CRTC0 (plane 3), CRTC1 (plane 2)

Pipe 0: old_plane_state = A1, new_plane_state = A2,   new_tg = T0
Pipe 1: old_plane_state = B1, new_plane_state = B2,   new_tg = T1
Pipe 2: old_plane_state = A1, new_plane_state = NULL, new_tg = NULL
Pipe 3: old_plane_state = B1, new_plane_state = NULL, new_tg = NULL

In the second commit the assertion for mpcc in use is hit because
mpcc disconnect never occurs for pipe 1. This is because the stream
changes for pipe 1 and the opp_list is empty.

This sequence occurs when running the
"igt@kms_plane_multiple@atomic-pipe-A-tiling-none" test with two
displays connected.

[How]
Expand the reset condition to include:

"old_pipe_ctx->stream_res.tg != new_pipe_ctx->stream_res.tg"

...but only when the plane state is non-NULL for both old and new.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Jerry (Fangzhi) Zuo
e3fa5c4cf1 drm/amd/display: Apply fake sink back to MST sequence
[Why]
It fixes the failure to create stream for sink in the scenario
when hotplug SST and MST in sequence, and disconnect MST.

[How]
Add the fake sink back after the majority of MST rework is done.

Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Tony Cheng <Tony.Cheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Dmytro Laktyushkin
49782c638f drm/amd/display: add a debug flag to force odm combine
Adding a bit vector to allow forcing odm on specific otgs

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Su Sung Chung
8dac4e7d89 drm/amd/display: store timing sync info in dc_stream_status
in program_timing_sync, after all the pipes are
grouped, store timing sync info in dc_stream_status

Signed-off-by: Su Sung Chung <Su.Chung@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Josip Pavic
4f69bc8c16 drm/amd/display: Modify ABM 2.2 Max Reduction
[Why]
Reduced backlight for ABM 2.2 at levels 1 and 2 is desired for
power savings.

[How]
Reduce the max reduction parameters for ABM 2.2

Signed-off-by: Josip Pavic <Josip.Pavic@amd.com>
Reviewed-by: Josip Pavic <Josip.Pavic@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Yongqiang Sun
056f05f65b drm/amd/display: pass vline_config parameter by reference.
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Chiawen Huang
ac627caf6b drm/amd/display: add gpio lock/unlock
[Why]
When querying HPD via GPIO flow,
it will create a new gpio object then free in the end of query.
There is a irql issue for HPD querying at ISR level.

[How]
Therefore, creating the HPD gpio object in dc_link and set it as unlcok in default.
1. reducing unnecessary malloc/free when HPD querying.
2. reducing init GPIO flow.
3. add lock/unlock to prevent multi gpio service running.

Signed-off-by: Chiawen Huang <chiawen.huang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Steven Chiu
cf7d98d254 drm/amd/display: 3.2.16
Signed-off-by: Steven Chiu <steven.chiu@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Wenjing Liu
5fc0cbfad4 drm/amd/display: determine if a pipe is synced by plane state
[why]
is_blanked is not a general indicator of if a pipe is synced
for all asics.
plane state is more accurate and applicable for all asics.

[how]
Remove is_blanked call and
add checking plane_state against NULL instead.

Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Krunoslav Kovac
8f01591227 drm/amd/display: DGAM enabled for HDR
[Why]
On HW that doesn't have input LUT, we may combine degamma with OS ramp
Problem here is that it assumes DGAM is inverse of PQ or SRGB. It doesn't
handle linear case, it would default to sRGB and always enable DGAM..

[How] Add handling for linear case. Also check for null ramp and instead of
blowing up, assume it's identity.

Signed-off-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Ilya Bakoulin
a057ec460a drm/amd/display: Check that vrefresh is in freesync range
[Why]
Setting monitor refresh rate below freesync range would cause the
monitor to go blank indefinitely with freesync enabled

[How]
Set vrr_supported and ignore_msa_timing_param according to whether
the refresh rate is above or below the minimum freesync frequency.

Signed-off-by: Ilya Bakoulin <Ilya.Bakoulin@amd.com>
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Paul Hsieh
22d7663f47 drm/amd/display: dmcu is blocking due to wrong disable ABM command
[Why]
Second screen to clone/extend mode, driver will send ABM pipe
command to DMCU. Change mode from clone/extend to second
screen only, driver send ABM level command to disable ABM but
this command will not clear ABM pipe data. At this time, change
second screen to PC screen only, driver will send first command
"ABM_LEVEL", it will turn on ABM with incorrect ABM pile so that
DMCU is blocking.

[How]
When driver try to disable ABM, change command from "ABM LEVEL"
to "ABM PIPE" so that it will clear ABM pile data.

Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Anthony Koo
b21e09d055 drm/amd/display: fix issue with DC brightness low with VB
[Why]
The problem is that we accidentally stopped loading some of the IRAM bytes
used for the backlight ramping mechanism. This happened when we
started reserving some region of IRAM as DMCU FW write only.

[How]
This change will define a start+end region for the IRAM read only region.
So the parameters needed for the backlight operation will be loaded
since it will be defined outside of the read only region.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Xiaodong Yan
a4f1d2b8a5 drm/amd/display: Add monitor patch for backlight off
[Why]
Different panel need different time from backlight disable to end of valid video data,
if the time is too short, panel will flash when dpms off

[How]
Add monitor patch to control the time from backlight disable to end of valid video data,

Signed-off-by: Xiaodong Yan <Xiaodong.Yan@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:23 -05:00
Nicholas Kazlauskas
385d7eeaf1 drm/amd/display: Remove FreeSync timing changed debug output
[Why]
This provides little debug value and creates a lot of dmesg noise.

[How]
Remove it.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:22 -05:00
Nicholas Kazlauskas
c448a53aaf drm/amd/display: Initialize stream_update to zero
[Why]
The stream_update struct is left unitialized but DC will access
its fields. This usually results in global state validation occur
during any atomic commit with state->allow_modeset = true.

[How]
Initialize the struct to zero for every stream we check.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:22 -05:00
Nicholas Kazlauskas
c744e974a2 drm/amd/display: Reformat dm_determine_update_type_for_commit
[Why]
The indenting for this function is a few levels too deep and can be
simplified a fair bit. This patch is in preparation for functional
changes that fix update type determination to occur less frequently
and more accurately.

[How]
Place checks early and exit/continue when possible. This isn't
a functional change.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:22 -05:00
Nicholas Kazlauskas
c7af5f77ae drm/amd/display: Use the right surface for flip and FreeSync
[Why]
We were always passing the first surface on the stream status for
flip updates when we should be using the surface associated with
the plane.

[How]
Use the dc_plane_state from the plane that's being updated.

FreeSync should also only keep track of updates from the primary
plane, so the check needed to be updated.

The acrtc->stream state doesn't need to be checked for NULL before
updating FreeSync either since there needs to be a stream to be
inside this function as a prerequisite.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: David Francis <David.Francis@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:22 -05:00
Nicholas Kazlauskas
f3e3698d05 drm/amd/display: Apply all surface updates onto surfaces
[Why]
Most surface updates weren't propagated onto the surface during
dc_commit_updates_for_stream. This makes it more difficult for DC to
determine the actual surface update type required.

[How]
Use copy_surface_update_to_plane to propagate the changes. The FreeSync
surface timing information update for BTR has been moved out of
amdgpu_dm.c into this function as well.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:22 -05:00
John Barberiz
9ca089925f drm/amd/display: Use udelay when waiting between aux retries
[Why]
"IRQ_HPD Pulse Length Test" DP compliance test
fails. Test complains that certain DPCD registers
are not read within 100 ms.

[How]
msleep is inaccurate for small values. Used udelay
instead for accuracy.

Signed-off-by: John Barberiz <John.Barberiz@amd.com>
Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:22 -05:00
Christian König
1b52f2d567 drm/amdgpu: cleanup VM dw estimation a bit
No functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:22 -05:00
Christian König
90d647222a drm/amdgpu: fix waiting for BO moves with CPU based PD/PT updates
Otherwise we open up the possibility to use uninitialized memory.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:22 -05:00
Shirish S
12a8bd8862 drm/amd/display: Use context parameters to enable FBC
[What]
FBC fails to get enabled when switched between LINEAR(console/VT)
and non-LINEAR(GUI) based rendering due to default value of
tiling info stored in the current_state which is used for deciding
whether or not to turn FBC on or off.

[How]
Use context structure's tiling information which is coherant with
the screen updates.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:16:22 -05:00
Nicholas Kazlauskas
cc7e422d3d drm/amd/display: Don't re-enable CRC when CONFIG_DEBUG_FS isn't defined
[Why]
When CONFIG_DEBUG_FS isn't defined then amdgpu_dm_crtc_set_crc_source
is NULL. This causes a compilation error since it's being called
unconditionally.

[How]
Guard the call based on CONFIG_DEBUG_FS - CRC capture isn't supported
without this.

Cc: Leo Li <sunpeng.li@amd.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Fixes: 43a6a02eb3 ("drm/amd/display: Re-enable CRC capture following modeset")
Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:15:46 -05:00
Marek Olšák
41cca166cc drm/amdgpu: add a workaround for GDS ordered append hangs with compute queues
I'm not increasing the DRM version because GDS isn't totally without bugs yet.

v2: update emit_ib_size

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:15:46 -05:00
Andrey Grodzovsky
67dd1a3633 drm/amdgpu: Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
New chunk for dependency on start of job's execution instead on
the end. This is used for GPU deadlock prevention when
userspace uses mid-IB fences to wait for mid-IB work on other rings.

v2: Fix typo in AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES
v3: Bump KMS version
v4: put old fence AFTER acquiring the scheduled fence.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Suggested-by: Christian Koenig <Christian.Koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:15:46 -05:00
Kenneth Feng
373e87fc91 drm/amd/powerplay: update soc boot and max level on vega10
update soc boot and max level,then uclk isn't stuck
at minimum.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109462
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:15:32 -05:00
Nathan Chancellor
8daa12182a drm/amd/display: Use memset to initialize variables in fill_plane_dcc_attributes
Clang warns:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:2314:38:
warning: suggest braces around initialization of subobject
[-Wmissing-braces]
        struct dc_surface_dcc_cap output = {0};
                                            ^
                                            {}

Previous efforts to fix this type of warning by adding or removing
braces have been met with some pushback in favor of using memset [1][2].
Do that here, mirroring commit 05794eff1a ("drm/amdgpu/gmc: fix
compiler errors [-Werror,-Wmissing-braces] (V2)") in this tree.

[1]: https://lore.kernel.org/lkml/022e41c0-8465-dc7a-a45c-64187ecd9684@amd.com/
[2]: https://lore.kernel.org/lkml/20181128.215241.702406654469517539.davem@davemloft.net/

Fixes: 7df7e505e8 ("drm/amd/display: Set requested plane state DCC params for GFX9")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:15:32 -05:00
Nathan Chancellor
19afd79951 drm/amd/display: Use memset to initialize variables in amdgpu_dm_atomic_commit_tail
Clang warns:

drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5089:60:
warning: suggest braces around initialization of subobject
[-Wmissing-braces]
                struct dc_surface_update dummy_updates[MAX_SURFACES] = { 0 };
                                                                         ^
                                                                         {}

Previous efforts to fix this type of warning by adding or removing
braces have been met with some pushback in favor of using memset [1][2].
Do that here, mirroring commit 05794eff1a ("drm/amdgpu/gmc: fix
compiler errors [-Werror,-Wmissing-braces] (V2)") in this tree.

[1]: https://lore.kernel.org/lkml/022e41c0-8465-dc7a-a45c-64187ecd9684@amd.com/
[2]: https://lore.kernel.org/lkml/20181128.215241.702406654469517539.davem@davemloft.net/

Fixes: 02d6a6fcdf ("drm/amd/display: Simplify underscan and ABM commit")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:15:32 -05:00
Nathan Chancellor
d6d36b55a0 drm/amd/display: Use memset to initialize variable in wait_for_training_aux_rd_interval
Clang warns:

drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dp.c:50:57:
warning: suggest braces around initialization of subobject
[-Wmissing-braces]
        union training_aux_rd_interval training_rd_interval = {0};
                                                               ^
                                                               {}
1 warning generated.

Previous efforts to fix this type of warning by adding or removing
braces have been met with some pushback in favor of using memset [1][2].
Do that here, mirroring commit 05794eff1a ("drm/amdgpu/gmc: fix
compiler errors [-Werror,-Wmissing-braces] (V2)") in this tree.

[1]: https://lore.kernel.org/lkml/022e41c0-8465-dc7a-a45c-64187ecd9684@amd.com/
[2]: https://lore.kernel.org/lkml/20181128.215241.702406654469517539.davem@davemloft.net/

Fixes: 3cec41769d ("drm/amd/display: Fix use of uninitialized union")
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:15:32 -05:00
Colin Ian King
c1219b941c drm/amd/amdgpu: fix spelling mistake "matech" -> "match"
There is a spelling mistake in a dev_err message. Fix it.

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-05 21:15:32 -05:00
Marek Olšák
fe57085a36 drm/amdgpu: clean up memory/GDS/GWS/OA alignment code
- move all adjustments into one place
- specify GDS/GWS/OA alignment in basic units of the heaps
- it looks like GDS alignment was 1 instead of 4

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-02-01 00:33:00 -05:00
Christian König
a5c8e0524d drm/amdgpu: cleanup amdgpu_pte_update_params
kptr is not used any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-29 15:16:18 -05:00
shaoyunl
47dd8048a1 drm/amdgpu: Show XGMI node and hive message per device only once
Reduce the repeated node and hive information during XGMI initialization

Signed-off-by: shaoyunl <shaoyun.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-29 15:16:18 -05:00
Alex Deucher
193392ed9f Revert "drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to undefined SW FP routines"
This reverts commit 1011745073.

Causes a crash.

Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109487
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 4.19
2019-01-29 15:16:18 -05:00
wentalou
cdba61daf5 drm/amdgpu: sriov restrict max_pfn below AMDGPU_GMC_HOLE
sriov need to restrict max_pfn below AMDGPU_GMC_HOLE.
access the hole results in a range fault interrupt IIRC.

Signed-off-by: Wentao Lou <Wentao.Lou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-29 15:16:18 -05:00
wentalou
06ea4c3499 drm/amdgpu: csa_vaddr should not larger than AMDGPU_GMC_HOLE_START
After removing unnecessary VM size calculations,
vm_manager.max_pfn would reach 0x10,0000,0000
max_pfn << AMDGPU_GPU_PAGE_SHIFT exceeding AMDGPU_GMC_HOLE_START
would cause GPU reset.

Signed-off-by: wentalou <Wentao.Lou@amd.com>
Reviewed-by: Monk Liu <monk.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-29 15:16:18 -05:00
Eric Huang
a97c084aad drm/amd/powerplay: add override pcie parameters for Vega20
It is to solve RDMA performance issue.

Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-28 11:46:23 -05:00
Nicholas Kazlauskas
4b5105036a drm/amd/display: Don't leak memory when updating streams
[Why]
The flip and full structures were allocated but never freed.

[How]
Free them at the end of the function. There's a small behavioral
change here with the function returning early if the allocation fails
but we wouldn't should be doing anything in that case anyway.

Fixes: c00e0cc0fdc0 ("drm/amd/display: Call into DC once per multiplane flip")
Fixes: ea39594e0855 ("drm/amd/display: Perform plane updates only when needed")

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Leo Li <sunpeng.li@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-28 11:45:24 -05:00
Fatemeh Darbehani
8fde60b7f3 drm/amd/display: Add Vline1 interrupt source to InterruptManager
[Why]
Enhanced sync need to use vertical_interrupt1.

[How]
Add vertical_interrupt1 source to irq manger,
Implment setup vline interrupt interface.

Signed-off-by: Fatemeh Darbehani <fatemeh.darbehani@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-28 11:44:10 -05:00
Nicholas Kazlauskas
43a6a02eb3 drm/amd/display: Re-enable CRC capture following modeset
[Why]
During any modeset the CRTC stream is removed and a new stream is added.
This new stream doesn't carry over CRC capture state if it was
previously set.

[How]
Re-program the stream for CRC capture. The existing DRM callback can
be re-used here for the most part - the only modification needed is
additional locking now that it's called from within commit tail.

Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-01-28 11:44:03 -05:00