This patch adds missing definitions of mux clocks required for using
EPLL as the audio subsystem root clock on exynos5420/exynos5422 SoCs.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds missing clock IDs for CMU_CDREX (DRAM Express Controller)
which generates clocks for DRAM and NoC (Network on Chip) busses.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds the clock id for ACLK clock of Exynos542x SoC.
ACLK clock means the source clock of AMBA AXI bus. This clock
id should be used for Bus frequency scaling.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Markus Reichl <m.reichl@fivetechno.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
This patch adds clocks, which are required for preserving parent clock
configuration on GSCL power domain on/off.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.
So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:
ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)
Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.
Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
drivers and fixes/enhancements to existing clock drivers. There are also
some non-critical fixes and improvements to the framework core.
Changes to the clock framework core include:
* improvements to printks on errors
* flattening the previously hierarchal structure of per-clock entries
in debugfs
* allow per-clock debugfs entries that are specific to a particular
clock driver
* configure initial clock parent and/or initial clock rate from Device
Tree
* several feature enhancements to the composite clock type
* misc fixes
New clock drivers added include:
* TI Palmas PMIC
* Allwinner A23 SoC
* Qualcomm APQ8084 and IPQ8064 SoCs
* Rockchip rk3188, rk3066 and rk3288 SoCs
* STMicroelectronics STiH407 SoC
* Cirrus Logic CLPS711X SoC
Many fixes, feature enhancements and further clock tree support for
existing clock drivers also were merged, such as Samsung's "ARMCLK down"
power saving feature for their Exynos4 & Exynos5 SoCs.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJT38lmAAoJEDqPOy9afJhJh9YQAKROq+lrKaf+YAk22E0GCF30
Q+KZ9EcePdxWvcDPKsMIf/wAIYdtGDoI6wgyw1tcSWeLKwwyHMfVdOCExWig2gwl
/4LU2tACKe+Xa0HJnsbNwQGj2n4qMGOUsDeRRmK4rcbuHZhTP15IscmFCbL+sUia
z3uaYf7ty3a1tSXBl3NY4EpYAXGiE+MMVBoU08ATYOOjvGcxNNfu50JSltGXarqv
BFBjpv0oikN3RvbVyuUUvEF8m6AeNYhbqxI0IuNmoE+mAkgB2n221CK4Qv6a3oDb
QJebzRdeprcak8HrK76Ik6Dd9itcs03u6G1qwLc30JH5wUHYcgqA5bvqDIx+2W0J
Z7NPi3tFTry1aeXnZPk7DbWruzXLQkXkgRM4xHXsmezRnO7zDvuoDgUT0pIrS9+v
+BRIyfPiBL9Lp1J17R0I1K76O7YnvyQhX+0CdZx0SOJNGPl+SIwTI4q+gQoDIZqP
0ubpuaH4v6gZiEol2HXKYN9ASWyRtX7PfiexQgmts1aewlPopWfuc7LdxhHQIv3B
3O/7jbhdhXsf7VaTvx7xkFEMxjY7IwEF4pN0F+ulwWj/rLK3vLCnTwxgv8IrNHit
Dkzt4kVzLW/GSWa3irTnISvsg+bHkRc7aPuW/i0km7RYUuL2dcaJLEBPYuka/AdH
1xIMaGNpkA3HrS+8CQYf
=48y9
-----END PGP SIGNATURE-----
Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux
Pull clock framework updates from Mike Turquette:
"The clock framework changes for 3.17 are mostly additions of new clock
drivers and fixes/enhancements to existing clock drivers. There are
also some non-critical fixes and improvements to the framework core.
Changes to the clock framework core include:
- improvements to printks on errors
- flattening the previously hierarchal structure of per-clock entries
in debugfs
- allow per-clock debugfs entries that are specific to a particular
clock driver
- configure initial clock parent and/or initial clock rate from
Device Tree
- several feature enhancements to the composite clock type
- misc fixes
New clock drivers added include:
- TI Palmas PMIC
- Allwinner A23 SoC
- Qualcomm APQ8084 and IPQ8064 SoCs
- Rockchip rk3188, rk3066 and rk3288 SoCs
- STMicroelectronics STiH407 SoC
- Cirrus Logic CLPS711X SoC
Many fixes, feature enhancements and further clock tree support for
existing clock drivers also were merged, such as Samsung's "ARMCLK
down" power saving feature for their Exynos4 & Exynos5 SoCs"
* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
clk: Add missing of_clk_set_defaults export
clk: checking wrong variable in __set_clk_parents()
clk: Propagate any error return from debug_init()
clk: clps711x: Add DT bindings documentation
clk: Add CLPS711X clk driver
clk: st: Use round to closest divider flag
clk: st: Update frequency tables for fs660c32 and fs432c65
clk: st: STiH407: Support for clockgenA9
clk: st: STiH407: Support for clockgenD0/D2/D3
clk: st: STiH407: Support for clockgenC0
clk: st: Add quadfs reset handling
clk: st: Add polarity bit indication
clk: st: STiH407: Support for clockgenA0
clk: st: STiH407: Support for A9 MUX Clocks
clk: st: STiH407: Support for Flexgen Clocks
clk: st: Adds Flexgen clock binding
clk: st: Remove uncessary (void *) cast
clk: st: use static const for clkgen_pll_data tables
clk: st: use static const for stm_fs tables
clk: st: Update ST clock binding documentation
...
This patch corrects mistyped author's name in four header files. While
at it, a copy/paste error in author's e-mail in one of the headers is
also fixed.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Samsung, ST & TI. Most of them are of the "this hardware won't work
without this fix" variety, including patches that fix platforms that did
not boot under certain configurations. Other fixes are the result of
changes to the clock core introduced in 3.15 that had subtle impacts on
the clock drivers.
There are no fixes to the clock framework core in this pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJTwrM0AAoJEDqPOy9afJhJGtgP/j99sWo/P/Q+wkybYfvlAvYF
UC69GdYIV4PpHXq7JDrs9n48cf8Cte6QsYTVxFipmcBKiZrxoH1Ft6AZk0XuzHPb
bONgwlxPH03Xy/pm1aWO3AX7zMiOzTlxAqPuisJa4rbBty3XOQqEFyuJnHEW2m59
L754YWvT6dAzYyU1LQE4iSGPD8Dmh/oVvjg17+hM6//yM3fspYA3gzui/Lj4L1sx
QL0FFo6SJ4vvn9MMen+/UgZZ2G25fR4e0AONvz+rzBA2fmCGoQbNs26Iyi+MpEtg
DlXGcMTwl3Cj+mulalAIxBJ441KDtqm6TZ7iIEuaBUDCxFxNIuvup8FuMIAjDlt4
+V6OTFA7tlYr8UGQ/KRiTTgd6TKKUu9FpKmYOq/K1VZZls6m2hVTWvcwZ/217VYq
cimnVrHGs22vXhYKL2S3/TWfioiVP3vN08+NQOI5IRhYfXm+oPMuWwahHU/VnY2C
AaAUaHgqSlLmIbGqgvsjDQglRyGajs8oz/SfDuxXTBClc/6lu4ENNL9UQffdBTV4
IfrU+ALRR+CjPtLOHUTrLIHldGbn40Ff0fdKyJ/iGtdE+iiNJcnoU2G0uuhMP4eP
JpAMY2XrzZWGVJegjvg1m1Qfv85FBJhUB6+T5wIFYwKwBPzSf/yx0YTt+R0mp7Lg
g0CWTO3SoDeKDSK2Yzr2
=6n8W
-----END PGP SIGNATURE-----
Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux
Pull clock driver fixes from Mike Turquette:
"This batch of fixes is for a handful of clock drivers from Allwinner,
Samsung, ST & TI. Most of them are of the "this hardware won't work
without this fix" variety, including patches that fix platforms that
did not boot under certain configurations. Other fixes are the result
of changes to the clock core introduced in 3.15 that had subtle
impacts on the clock drivers.
There are no fixes to the clock framework core in this pull request"
* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
clk: spear3xx: Set proper clock parent of uart1/2
clk: spear3xx: Use proper control register offset
clk: qcom: HDMI source sel is 3 not 2
clk: sunxi: fix devm_ioremap_resource error detection code
clk: s2mps11: Fix double free corruption during driver unbind
clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
clk: exynos5420: Remove aclk66_peric from the clock tree description
clk/exynos5250: fix bit number for tv sysmmu clock
clk: s3c64xx: Hookup SPI clocks correctly
clk: samsung: exynos4: Remove SRC_MASK_ISP gates
clk: samsung: add more aliases for s3c24xx
clk: samsung: fix several typos to fix boot on s3c2410
clk: ti: set CLK_SET_RATE_NO_REPARENT for ti,mux-clock
clk: ti: am43x: Fix boot with CONFIG_SOC_AM33XX disabled
clk: ti: dra7: return error code in failure case
clk: ti: apll: not allocating enough data
Adds IDs for MUX clocks to be used by power domain for MFC
for doing re-parenting while pd on/off.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The "aclk66_peric" clock is a gate clock with a whole bunch of gates
underneath it. This big gate isn't very useful to include in our
clock tree. If any of the children need to be turned on then the big
gate will need to be on anyway. ...and there are plenty of other "big
gates" that aren't described in our clock tree, some of which shut off
collections of clocks that have no relationship in the hierarchy so
are hard to model.
"aclk66_peric" is causing earlyprintk problems since it gets disabled
as part of the boot process, so let's just remove it.
Strangely (and for no good reason) this clock is exported as part of
the common clock bindings. Remove it since there are no in-kernel
device trees using it and no reason anyone out of tree should refer to
it either.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Exynos5800 clock structure is mostly similar to 5420 with only
a small delta changes. So the 5420 clock file is re-used for
5800 also. The common clocks for both are seggreagated and few
clocks which are different for both are separately initialized.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds some missing miscellaneous clocks specific
to exynos5420.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds the missing MAU block specific clocks.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch fixes some parent-child relationships according
to the latest datasheet and adds more clocks related to
PERIS and GEN blocks.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch includes,
1] renaming of the HSI2C clocks
2] renaming of spi clocks according to the datasheet
3] fixes for child-parent relationships
4] adding of more clocks related to PERIC block
5] use GATE_IP_* offsets instead of GATE_BUS_*
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch corrects some child-parent clock relationships,
and updates the clocks according to the latest datasheet.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds missing clocks of G2D block. It also removes
the aclkg3d alias from G3D block clocks.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds the missing GSCL and MSCL block clocks
and corrects some wrong parent-child relationships.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
This patch adds minimum set of clocks to gate ISP block for
power saving.
Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Adds IDs for the clocks needed by the ARM Mali GPU
in exynos5420.
Signed-off-by: Arun Kumar K <arun.kk@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
The patch adds header file defining clock IDs.
This allows to use macros instead of magic numbers in DT bindings.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
