3 Commits

Author	SHA1	Message	Date
Andy Yan	150696e2e3	include: dt-bindings: Add GPIO pin index definition for rockchip pinctrl ... Add gpio pin index definition to make it easier to describe GPIO in dts. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2016-10-21 18:21:09 +02:00
Doug Anderson	f3ababa8ba	pinctrl: Add mux options 3 and 4 for rockchip pinctrl ... Newer Rockchip SoCs have more muxing slots. Add slots 3 and 4 since the rk3288 table goes all the way up to 4. Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>	2014-08-28 15:18:03 +02:00
Heiko Stübner	d3e5116119	pinctrl: add pinctrl driver for Rockchip SoCs ... This driver adds support the Cortex-A9 based SoCs from Rockchip, so at least the RK2928, RK3066 (a and b) and RK3188. Earlier Rockchip SoCs seem to use similar mechanics for gpio handling so should be supportable with relative small changes. Pull handling on the rk3188 is currently a stub, due to it being a bit different to the earlier SoCs. Pinmuxing as well as gpio (and interrupt-) handling tested on a rk3066a based machine. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>	2013-06-16 11:57:32 +02:00