Commit Graph

6 Commits

Author SHA1 Message Date
Zhou Wang
9f5ce88de8 arm64: dts: hisi: add PCIe host controller node for hip07 SoC
Add one PCIe host controller node for HiSilicon Hip07 SoC and enable it in
D05 board.

Signed-off-by: Zhou Wang <wangzhou1@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-08-14 15:25:39 +01:00
Wei Xu
86d67897f9 arm64: dts: hisi: add SAS nodes for the hip07 SoC
Add 3 SAS host controller nodes and the dependent subctrl node
to enable the SAS and SATA function for the hip07 SoC.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-08 13:43:45 +08:00
Wei Xu
0f57c6c9cd arm64: dts: hisi: add RoCE nodes for the hip07 SoC
Add the infiniband node to support the RoCE function
on the hip07 SoC.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-08 11:07:26 +08:00
Wei Xu
38de5b56ef arm64: dts: hisi: add network related nodes for the hip07 SoC
Add MDIO, SerDes, Port and realted HNS nodes to support the
network on the hip07 SoC.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-08 11:07:25 +08:00
Wei Xu
bbeca45f41 arm64: dts: hisi: add mbigen nodes for the hip07 SoC
Add mbigen nodes for the hip07 SoC those will be used
for the SAS, XGE and PCIe host controllers.

Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2017-04-08 11:07:25 +08:00
Kefeng Wang
4f357f94e1 arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
Adding initial dt file for Hip07 D05 board, it is with dual socket
and each socket has two SCCLs(supper cpu cluster), one SCCL contains
four clusters and each cluster has quard Cortex-A72.

Since each SCCL has their own DDR controller, it could be treated as
a separate numa node. Thus, there are four numa nodes(one node with
sixteen core) on Hip07 SoC.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-11-15 10:36:17 +00:00