Commit Graph

2 Commits

Author SHA1 Message Date
Alexandru Ardelean
519808425e iio: imu: adis16460: fix variable signedness
Caught via static-analysis checker:
```
drivers/iio/imu/adis16460.c
   152  static int adis16460_set_freq(struct iio_dev *indio_dev, int val, int val2)
   153  {
   154          struct adis16460 *st = iio_priv(indio_dev);
   155          unsigned int t;
                ^^^^^^^^^^^^^^

   156
   157          t =  val * 1000 + val2 / 1000;
   158          if (t <= 0)
                    ^^^^^^
Unsigned is not less than zero.
```

The types of `val` && `val2` are obtained from the IIO `write_raw` hook, so
userspace can provide negative values, which can cause weird behavior after
conversion to unsigned.

This patch changes the sign of variable `t` so that -EINVAL will be
returned for negative values as well.

Fixes: db6ed4d23d ("iio: imu: Add support for the ADIS16460 IMU")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2019-08-18 18:53:15 +01:00
Alexandru Ardelean
db6ed4d23d iio: imu: Add support for the ADIS16460 IMU
The ADIS16460 device is a complete inertial system that includes a triaxial
gyroscope and a triaxial accelerometer. It's more simplified design than
that of the ADIS16480, and does not offer the triaxial magnetometers &
pressure sensors. It does also have a temperature sensor (like the
ADIS16480).
Since it is part of the ADIS16XXX family, it re-uses parts of the ADIS
library.

Naturally, the register map is different and much more simplified than the
ADIS16480 subfamily, so it cannot be integrated into that driver. A major
difference is that the registers are not paged.

One thing that is particularly special about it, is that it requires a
higher delay between CS changes (i.e. when CS goes up, the spec recommends
that it be brought down after a minimum of 16 uS).
Other ADIS chips require (via spec) a minimum of 2 uS between CS changes.
The kernel's 10 uS default should be fine for those other chips; they
haven't been tested with lower CS change delays yet.

Datasheet:
  https://www.analog.com/media/en/technical-documentation/data-sheets/adis16460.pdf

Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2019-07-27 22:52:06 +01:00