AuxXxilium/linux_dsm_epyc7002
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b3fddd5b10
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3 Commits

Author SHA1 Message Date
Peng Fan
b3fddd5b10 clk: imx: imx8mm: fix int pll clk gate 
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.

Cc: <stable@vger.kernel.org>
Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-05-21 11:42:44 -07:00
Stephen Boyd
341fdf2602 clk: imx: imx8mm: Mark init function __init 
It calls another __init marked function and thus causes a section
mismatch if we don't mark it this way.

Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-02-21 15:29:10 -08:00
Bai Ping
ba5625c3e2 clk: imx: Add clock driver support for imx8mm 
Add clock driver support for i.MX8MM SOC.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-02-21 12:41:16 -08:00