Add sm1 support the axg audio clock controllers. This new version is
indeed derived from the previous generation, as always, adding a few
new clocks to the mix.
The number of gates now exceeds 32 and do not fit in a single register.
Unfortunately, designers chose to introduce the new gate register
immediately after the original one, at the beginning of the register
space, shifting all the master clock register offsets.
The sm1 also introduce a few mux and divider on the top clock path,
possibly to lower the peripheral clocks of the audio blocks if
necessary.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The peripheral clock on the sm1 goes through some muxes
and dividers before reaching the audio gates. To model that,
without repeating our self too much, the "top" clock signal
is introduced and will serve as a the parent of the gates.
On the axg and g12a, the top clock is just a pass-through to
the audio peripheral clock provided by the main controller.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
On the g12a, the register space dedicated to the audio clock also
provides some resets. Let the clock controller register a reset
provider as well for this SoC family.
the axg SoC family does not appear to provide this feature.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
The g12a audio clock controller is largely similar to the existing axg
controller, with the addition of the spdif output B and TDM pad clocks.
This commit extends the existing axg audio clock controller driver
to work with multiple compatibles and add the g12a specific clocks
Signed-off-by: Maxime Jourdan <mjourdan@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190329160649.31603-5-jbrunet@baylibre.com
Clock inputs should not be exported outside the controller. It is a hack
to have a stable global clock name within the clock controller, even for
clocks external to the controller.
There is an ongoing effort to replace this hack with something better.
The first step is to not register those clocks in the provider anymore,
so we can completely remove them later on.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190329160649.31603-4-jbrunet@baylibre.com
Remove the bindings ID of the clock input of the controller. These
clocks are purely internal to the controller, exposing them was a
mistake. Actually, these should not even be in the provider and have
IDs to begin with.
Unexpose these IDs before:
* someone starts using them (even if there no valid reason to do so)
* the actual clocks are removed. The fact that they exist is just the
result of an ugly hack. This will be resolved in CCF when we can
reference DT directly in parent table.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Maxime Jourdan <mjourdan@baylibre.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lkml.kernel.org/r/20190213095835.17448-1-jbrunet@baylibre.com
The axg audio clock controller is the clock generation unit for the
amlogic audio subsystem of A113 based SoCs. It may be clocked by 8
different plls provided by the primary clock controller and also by
10 slave bit clocks and 10 slave sample clocks which may be provided
by external components, such as audio codecs, through the SoC pads.
It contains several muxes, dividers and gates which are fed into the
the different devices of the audio subsystem.
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
