Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
the refdiv == 6, it will increase the lock time, and it is not an optimal
configuration.
Let's fix them for the lock time and jitter are lower:
800 MHz:
- FVCO == 2.4 GHz, revdiv == 1.
1 GHz:
- FVCO == 3 GHz, revdiv == 1.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We need to get the accurate 533.25MHz for the DP display.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
control. While reading that clock is done the normal way from the
registers, setting it always requires some sort of special handling
to let the system survive this addition.
As the commit message explains, there are currently 3 handling-types
known. General SRAM-based code on rk3288 and before (which is waiting
essentially for the PIE support that is currently being worked on),
SCPI-based clk setting on the rk3368 through a coprocessor, which we
might support once the support for legacy scpi-variants has matured
and now on the rk3399 (and probably later) using a dcf controller that
is controlled from the arm-trusted-firmware and gets accessed through
firmware calls from the kernel. This is the variant we currently
support, but the clock type is made to support the other variants in
the future as well.
Apart from that slightly bigger chunk, we have a mix of PLL rates,
clock-ids and flags mainly for the rk3399.
And interestingly an iomap fix for the legacy gate driver, where I
hopefully could deter the submitter from actually using that in any
new works.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJXzrz5AAoJEPOmecmc0R2B0NMH/0SGrQnrUsaq0cvjZPaq8jTD
nJDVIRw099HNM3QZCfy+FZbSsnmex93clX+Fn4UdehplrCZ8ExX1wpPkMwvFcPJF
M34YyFXx5MU9OmDsJXd1UlGRD/mH0L6hKnmfBQiPbK33ObXbr7LCC1L3go+oYABN
eHaOzO1KIcdoCQd6RlVAQHCsiDy8akUJ68P2uACHZ7VVgvGw2f3NdJhOKTD5lCuf
WH/MRo9X9bPDGHpFJIX+mZzZgYsMqUjyF/mYU/VMoH70w+YZTnfcbrYpJ0VkgBYd
aQF2B9VXhed9EQG3Gfu+jgsWoWLed9AJf83UP6eMsPTPLNQBqgzoDZwylbY1Szk=
=LjDG
-----END PGP SIGNATURE-----
Merge tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
The biggest addition is probably the special clock-type for ddr clock
control. While reading that clock is done the normal way from the
registers, setting it always requires some sort of special handling
to let the system survive this addition.
As the commit message explains, there are currently 3 handling-types
known. General SRAM-based code on rk3288 and before (which is waiting
essentially for the PIE support that is currently being worked on),
SCPI-based clk setting on the rk3368 through a coprocessor, which we
might support once the support for legacy scpi-variants has matured
and now on the rk3399 (and probably later) using a dcf controller that
is controlled from the arm-trusted-firmware and gets accessed through
firmware calls from the kernel. This is the variant we currently
support, but the clock type is made to support the other variants in
the future as well.
Apart from that slightly bigger chunk, we have a mix of PLL rates,
clock-ids and flags mainly for the rk3399.
And interestingly an iomap fix for the legacy gate driver, where I
hopefully could deter the submitter from actually using that in any
new works.
* tag 'v4.9-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: use the dclk_vop_frac clock ids on rk3399
clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers
clk: rockchip: add 2016M to big cpu clk rate table on rk3399
clk: rockchip: add rk3399 ddr clock support
clk: rockchip: add dclk_vop_frac ids for rk3399 vop
clk: rockchip: add new clock-type for the ddrclk
soc: rockchip: add header for ddr rate SIP interface
clk: rockchip: add SCLK_DDRC id for rk3399 ddrc
clk: rockchip: handle of_iomap failures in legacy clock driver
clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical
clk: rockchip: use general clock flag when registering pll
clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399
clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI
Export the dclk_vop_frac out, so we can set the dclk_vop as the
child of dclk_vop_frac, and then we can start to take use of
the fractional dividers.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Currently the fractional divider clock time can't handle the
CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers,
there is no clk_divider_bestdiv() function to try speeding up the parent
to see if it helps things.
Eventually someone could try to figure out how to make fractional
dividers able to use CLK_SET_RATE_PARENT, but until they do let's not
confuse the common clock framework (and anyone using it) by setting the
flag.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We would prefer the 2016M as 2.0G than 1992M which seems odd, adding
it to big cpu clk rate table then we can set 2016M in dts.
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Reviewed-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
add ddrc clock setting, so we can do ddr frequency
scaling on rk3399 platform in future.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We don't have code to handle any of the noc clocks in rk3399 and they're
all just listed as critical clocks. Let's do the same for
aclk_emmc_noc.
Without this clock being marked as critical we have problems around
suspend/resume after commit 20c389e656 ("clk: rockchip: fix incorrect
aclk_emmc source gate bits on rk3399"). Before that change we were
presumably not actually gating any of these clocks because we were
setting the wrong gate.
Fixes: 20c389e656 ("clk: rockchip: fix incorrect aclk_emmc source gate bits on rk3399")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Sorry to refer incorrect clock diagram, we double check it that the bits
configuration of the Xpll_aclk_perihp_src need to be fixed:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Through the testing that plug/unplug the USB ethernet cable on the RK3399 kevin board.
1. the hclk_host0 and hclk_host1 are endpoint clocks:
cpll --> G5[1] --> aclk_perihp_cpll_src --\ |--> hclk_host0
| --> ... ---> |
gpll --> G5[0] --> aclk_perihp_gpll_src --/ |--> hclk_host1
2. there is no clock below the cpll_aclk_perihp_src,
and the hclk_hostX are below the gpll_aclk_perihp_src:
pll_cpll 1 1 800000000 0 0
cpll 7 19 800000000 0 0
cpll_aclk_perihp_src 0 0 800000000 0 0
...
pll_gpll 1 1 594000000 0 0
gpll 10 10 594000000 0 0
gpll_aclk_perihp_src 2 2 594000000 0 0
hclk_perihp 5 5 74250000 0 0
hclk_host1_arb 2 2 74250000 0 0
hclk_host1 2 2 74250000 0 0
hclk_host0_arb 2 2 74250000 0 0
hclk_host0 2 2 74250000 0 0
3. by default, G5[0] and G5[1] are enabled:
localhost ~ # mem r 0xff760314
0x000003e0
4. close the G5[1] (aclk_perihp_cpll_src), and plug/unplug USB ethernet cable,
the DUT still works well:
localhost ~ # mem w 0xff760314 0xffff03e2
localhost ~ # mem r 0xff760314
0x000003e2
plug/unplug, the work statue is ok
5. close the G5[0] (aclk_perihp_gpll_src), , and plug/unplug USB ethernet cable,
the DUT will be crashed:
localhost ~ # mem w 0xff760314 0xffff03e1
localhost ~ # mem r 0xff760314
0x000003e1
plug/unplug, the DUT is crashed
Summary:
bit 1 - shows aclk_perihp_cpll_src_en
bit 0 - shows aclk_perihp_gpll_src_en
Fixes: 3bd14ae9da ("clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp_src")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
[here the clock-documentation in the manual was actually stating the wrong
bits and thus only Xing's testing above revealed the issue]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Dues to incorrect diagram, we need to fix incorrect bits for
(c/g)pll_aclk_emmc_src:
cpll_aclk_emmc_src --> G6[13]
gpll_aclk_emmc_src --> G6[12]
Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The aclk_vio_noc should be put into critical list, as the interconnect
is not handled right now, but is required by VOP.
And the Type-C DP need these clocks: aclk_hdcp_noc, hclk_hdcp_noc,
pclk_hdcp_noc. Mark them as critical to avoid someone close them.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Guenter Roeck <groeck@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We need to add more clocks for supporting more display resolution
for HDMI.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
rk3228 clockids and a small fix for the not yet used spdif to
displayport clock on the rk3399.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABCAAGBQJXdbFVAAoJEPOmecmc0R2B2fEH/1Gm80XZsrXPrr0kZ2cO8Zcg
qUpOPJgZvEWJdG1EGzU34VAEAZP0y8sth46iypL+TP3UVf6Z9acZF2eeAbEvzdVY
pM6qb0eNLdrcV+aaKhAScxjEwg5kdLxc/kuwOr9XsZwE4Wqvsbmldw5O8qEU8DAP
fxdhi854hlanCVmTCfdjEpeRqv9JCejU27KttldqBC/0CwGaQwp0cUcp6Ggpv9pF
deHR5BGj2cwnPR2JmNsZ9U85kgf9/7jd4PD4UXNRG/ApuwpIb0/1ulr4YquqAcDW
OpdO6at9QmZItYS6byKNoAPKWoGXjmHYnjlENODQsCXoa6K8HkmDnxBtli6Iczw=
=6ikd
-----END PGP SIGNATURE-----
Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next
Pull rockchip clk driver updates from Heiko Stuebner:
Placeholder for the rk3399 watchdog pclk, some newly exported
rk3228 clockids and a small fix for the not yet used spdif to
displayport clock on the rk3399.
* tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits
clk: rockchip: export rk3228 MAC clocks
clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk
clk: rockchip: export rk3228 audio clocks
clk: rockchip: include rk3228 downstream muxes into fractional dividers
clk: rockchip: fix incorrect rk3228 clock registers
clk: rockchip: add clock-ids for rk3228 MAC clocks
clk: rockchip: add clock-ids for rk3228 audio clocks
clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
The CLKSEL_CON32 bit_0 is controlled for spdif_8ch, not spdif_rec_dptx,
it should be bit_8, let's fix it.
Fixes: 115510053e ("clk: rockchip: add clock controller for the RK3399")
Reported-by: Chris Zhong <zyw@rock-chips.com>
Tested-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Cc: stable@vger.kernel.org
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We should call iounmap to relase reg_base since it's not going
to be used any more if failing to init clk.
This was missing on the newly added rk3399 clock tree.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Like rk3288, the pclk supplying the watchdog is controlled via the
SGRF register area. Additionally the SGRF isn't even writable in
every boot mode.
But still the clock control is available and in the future someone
might want to use it. Therefore define a simple clock for the time
being so that the watchdog driver can read its rate.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Reviewed-by: Stephen Barber <smbarber@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
There was a typo, swapping 'c' <--> 'g'.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We never want to kill the GIC.
Noticed when making other clock fixups, and seeing the newly-constructed
clock tree try to disable cpll, where we had this parent structure:
aclk_gic <------\
|--- aclk_gic_pre <-- cpll <-- pll_cpll
aclk_gic_noc <--/
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The rk3399 clock table had a simple typo in it, calling the SDMMC sample
and drive clocks by the wrong name. Fix this minor typo.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Brian Norris <briannorris@chromium.org>
Acked-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The cifout clock is incorrect due to the manual error, we need to
fix it.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We don't need to many clocks enable after startup, to reduce some
power consumption.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch add some necessary frequencies for the RK3399 clock.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The gate bits of the i2c4 and i2c8 are incorrect due to the manual
error, we need to fix them.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We allow overlong lines in the array portitions describing the clock
trees to ease readability by having each element always at the same
position. But the rest of the code should honor the 80 char limit.
Fix the newly added rk3399 clock code to respect that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the clock tree definition for the new RK3399 SoC.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
