Commit Graph

92 Commits

Author SHA1 Message Date
Ben Skeggs
6189f1b093 drm/nouveau/fifo: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:11 +10:00
Ben Skeggs
6052dc5775 drm/nouveau/volt: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:10 +10:00
Ben Skeggs
cb8bb9cedb drm/nouveau/tmr: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:09 +10:00
Ben Skeggs
da06b46b72 drm/nouveau/therm: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:09 +10:00
Ben Skeggs
5a7d1e22fe drm/nouveau/pmu: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:09 +10:00
Ben Skeggs
2d9d5889e8 drm/nouveau/mxm: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:09 +10:00
Ben Skeggs
1f5bffca22 drm/nouveau/mmu: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:09 +10:00
Ben Skeggs
2ca0ddbc03 drm/nouveau/mc: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:09 +10:00
Ben Skeggs
c7750cfbc1 drm/nouveau/ltc: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:09 +10:00
Ben Skeggs
c44c06aeeb drm/nouveau/imem: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:08 +10:00
Ben Skeggs
ac51596f27 drm/nouveau/ibus: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:08 +10:00
Ben Skeggs
5b920d9264 drm/nouveau/i2c: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:08 +10:00
Ben Skeggs
e7d6518104 drm/nouveau/gpio: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:08 +10:00
Ben Skeggs
ce7b4f60a8 drm/nouveau/fuse: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:08 +10:00
Ben Skeggs
b1e4553cb1 drm/nouveau/fb: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:08 +10:00
Ben Skeggs
266f8b5ee6 drm/nouveau/devinit: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:07 +10:00
Ben Skeggs
3eca809b3c drm/nouveau/clk: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:07 +10:00
Ben Skeggs
01d6b95605 drm/nouveau/bus: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:07 +10:00
Ben Skeggs
a00014e396 drm/nouveau/bios: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:07 +10:00
Ben Skeggs
5b0c189fcb drm/nouveau/bar: cosmetic changes
This is purely preparation for upcoming commits, there should be no
code changes here.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:07 +10:00
Ben Skeggs
9ace404b10 drm/nouveau/device: include core/device.h automatically for subdevs/engines
Pretty much every subdev/engine is going to need access to nvkm_device
shortly to touch registers and/or output messages.

The odd placement of the includes is necessary to work around some
inter-dependencies that currently exist.  This will be fixed later.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:07 +10:00
Ben Skeggs
d351b8569e drm/nouveau/subdev: add direct pointer to nvkm_device
Will be utilised in upcoming commits to remove the need for heuristics
to lookup the device a subdev belongs to.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:06 +10:00
Ben Skeggs
205877f915 drm/nouveau/pmu/gk104: implement a hackish workaround for a hw bug
Only a handful of machines have this enabled by default, where it's been
proven to work.  The workaround can be explicitly enabled with a module
option also.

Still waiting on feedback from NVIDIA for a proper idea of exactly what
this fix is doing, and how to implement it properly.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:05 +10:00
Ben Skeggs
fe0f5d0880 drm/nouveau/disp/dp: fix some tx_pu mishandling
We only need to mask 0x0f on GM2xx, and want to keep the higher bits on
earlier cards.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:05 +10:00
Ben Skeggs
f10956d445 drm/nouveau/bios/dp: use alternate set of drvctl values where necessary
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:05 +10:00
Ben Skeggs
7c11c99b3c drm/nouveau/bios/dcb: accept "maxwell" lane count values for dcb 4.0
We previously assumed that the values "2" and "4" were new in DCB 4.1,
however, there's at least one GM107 DCB 4.0 board (Quadro K620) that
uses the newer values.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:04 +10:00
Ilia Mirkin
895fb8e6f7 drm/nouveau/fb/sddr3: add WR/CWL values seen on a GK208
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:04 +10:00
Ilia Mirkin
bacbad17fb drm/nouveau/bios: add opcodes 0x73 and 0x77
No known VBIOSes use these, but they are present in the actual VBIOS
table parsing logic. No harm in adding these too.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:03 +10:00
Wei Ni
85fa319d8a drm/nouveau/drm/nouveau/clk: fix tstate to pstate calculation
According to the tstate calculation in nvkm_clk_tstate(),
the range of tstate is from -(clk->state_nr - 1) to 0,
it mean the tstate is negative value. But in nvkm_pstate_work(),
it use (clk->state_nr - 1 - clk->tstate) to limit pstate,
it's not correct.
This patch fix it to use (clk->state_nr - 1 + clk->tstate) to
limit pstate.

Signed-off-by: Wei Ni <wni@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:40:01 +10:00
Roy Spliet
087cd0db87 drm/nouveau/clk/nv50: Enable user reclocking for NVA0
Tested on a few cards. Probably works quite well for most, given they should
all be GDDR3.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:39:57 +10:00
Roy Spliet
852c619b6e drm/nouveau/fb/gddr3: Add a few CL and WR entries observed on GTX260
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:39:57 +10:00
Roy Spliet
82a74fd293 drm/nouveau/fb/ramnv50: GDDR3 script for NVA0
This looks surprisingly similar to scripts on earlier cards as well
but they don't seem to work just yet. That... and I don't have any, which
makes it a tough job to reverse engineer.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:39:56 +10:00
Roy Spliet
c25bf7b615 drm/nouveau/bios/ramcfg: Separate out RON pull value
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:39:56 +10:00
Roy Spliet
2813e19f13 drm/nouveau/bios/rammap: Parse perf mode as if it's a rammap entry
Some of the bits in there are similar to the bits in the gt215 rammap.

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:39:56 +10:00
Roy Spliet
35fe024acf drm/nouveau/fb/ramnv50: Ressurect timing code, use proper timing/rammap handlers
Might need some generalisation to < GT200. For those: use at your own risk!

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:39:56 +10:00
Roy Spliet
3b582bed90 drm/nouveau/fb/ramgt215: No need to cuss like that
Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:39:56 +10:00
Roy Spliet
d4cc5f0c2a drm/nouveau/fb/ramnv50: Make 0x100da0 per-partition
Like on GT215

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:39:56 +10:00
Roy Spliet
7164f4c5b2 drm/nouveau/bios/rammap: Pull DLLoff bit out of version 0x10 struct
In preparation of NV50 reclocking, where there is no version

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-08-28 12:39:55 +10:00
Ilia Mirkin
d31b11d858 drm/nouveau/bios: add proper support for opcode 0x59
More analysis shows that this is identical to 0x79 except that it loads
the frequency indirectly from elsewhere in the VBIOS.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91025
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-07-27 18:56:09 +10:00
Ilia Mirkin
360ccb8436 drm/nouveau/bios: add 0x59 and 0x5a opcodes
Opcode 0x5a is a register write for data looked up from another part of
the VBIOS image. 0x59 is a more complex opcode, but we may as well
recognize it. These occur on a single known instance of Riva TNT2
hardware.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91025
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-07-27 18:56:09 +10:00
Alexandre Courbot
9c56be4cf3 drm/nouveau/ibus/gk20a: increase SM wait timeout
Increase clock timeout for SYS, FPB and GPC in order to avoid operation
failure at high gpcclk rate.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-07-27 18:56:08 +10:00
Roy Spliet
9694554691 drm/nouveau/clk/gt215: u32->s32 for difference in req. and set clock
This difference can of course be negative too...

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-07-27 18:56:07 +10:00
Kamil Dudka
7512223b1e drm/nouveau/drm/nv04-nv40/instmem: protect access to priv->heap by mutex
This fixes the list_del corruption reported
at <https://bugzilla.redhat.com/1205985>.

Signed-off-by: Kamil Dudka <kdudka@redhat.com>
2015-07-27 18:56:07 +10:00
Ben Skeggs
4d4d6f7520 drm/nouveau/devinit/gm100-: force devinit table execution on boards without PDISP
Should fix fdo#89558

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-05-29 10:59:32 +10:00
Ben Skeggs
c9ab50d210 drm/nouveau/devinit/gf100: make the force-post condition more obvious
And also more generic, so it can be used on newer chipsets.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-05-29 10:59:32 +10:00
Jan Vesely
4195f40685 drm/nouveau/bios: fix fetching from acpi on certain systems
nvbios_extend() returns 1 to indicate "extended the array" and 0 to
indicate the array is already big enough.  This is used by the core
shadowing code to prevent re-fetching chunks of the image that have
already been shadowed.

The ACPI fetching code may possibly need to extend this further due
to requiring fetches to happen in 4KiB chunks.

Under certain circumstances (that happen if the total image size is
a multiple of 4KiB), the memory allocated to store the shadow will
already be big enough, causing the ACPI code's nvbios_extend() call
to return 0, which is misinterpreted as a failure.

The fix is simple, accept >= 0 as a successful condition here.  The
core will have already made sure that we're not re-fetching data we
already have.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89047

v2 (Ben Skeggs):
- dropped hunk which would cause unnecessary re-fetching
- more descriptive explanation

Signed-off-by: Jan Vesely <jano.vesely@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-04-14 17:00:59 +10:00
Alexandre Courbot
7120908d12 drm/nouveau/pmu/gk20a: add some missing statics
Make static a few functions and structures that should be.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-04-14 17:00:52 +10:00
Ben Skeggs
f02a0e849d drm/nouveau/pmu/gk208: implement gr power-up magic with gk110_pmu_pgob()
Before we moved gk110's implementation of this to pmu, the functions were
identical.  This commit just switches GK208 to use the new (more complete)
implementation of the power-up sequence.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-04-14 17:00:50 +10:00
Ben Skeggs
e1fc44fb9d drm/nouveau/pmu/gk110: implement gr power-up magic like PGOB on earlier chips
Turns out the PTHERM part of this dance is bracketed by the same PMU
fiddling that occurs on GK104/6, let's assume it's also PGOB.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-04-14 17:00:50 +10:00
Roy Spliet
d9da545e10 drm/nouveau/pbus/hwsq: Make code size u16
So we can actually use the full 512 byte code space

Signed-off-by: Roy Spliet <rspliet@eclipso.eu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2015-04-14 17:00:49 +10:00