Commit Graph

17 Commits

Author SHA1 Message Date
Simon Goldschmidt
e793b284d7 arm: dts: socfpga*.dts*: use SPDX-License-Identifier
Follow the recent trend for the license description.

This is also in an effort to fully sync the devicetrees with U-Boot.

Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-11-28 09:24:52 -06:00
Dinh Nguyen
ef8216d28a ARM: dts: socfpga: disable over-current for Arria10 USB devkit
The USB host functionality on the Arria10 needs the disable-over-current
property.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2018-01-23 09:36:46 -06:00
Dinh Nguyen
3c56909ec2 ARM: dts: socfpga: set the i2c frequency
Use 'clock-frequency' binding for the i2c node that will put the I2C driver
into the standard operating mode. 'speed-mode' was not a valid binding for
the I2C driver, remove it.

Signed-off-by: Alan Tull <atull@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-06-23 09:29:13 -05:00
Thor Thayer
7fed0cbffe ARM: dts: socfpga: Add Devkit A10-SR Reset Controller
Add the Altera Arria10 System Resource Reset Controller to the MFD

Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2  change commit header to ARM: dts: socfpga.
2017-03-16 07:57:16 -05:00
Florian Vaussard
332ddfab42 ARM: dts: socfpga: Add unit name to memory nodes
Memory nodes in Arria5, Cyclone5 and Arria10 do not have a unit name.
This will trigger several warnings like this one (when compiled with
W=1):

Node /memory has a reg or ranges property, but no unit name

Add the corresponding unit name to each node.

Signed-off-by: Florian Vaussard <florian.vaussard@heig-vd.ch>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-03-06 15:54:58 -06:00
Dinh Nguyen
59d94d2ed4 ARM: dts: watchdog0 cannot reliably trigger reset
On the Arria10, because of hardware bug, watchdog0 cannot reliably trigger
a reset to the CPU. The workaround would be to use watchdog1 instead.

Also for watchdog1, there is a dependency on the bootloader to enable the
boot_clk source to be from the cb_intosc_hs_clk/2, versus from EOSC1. This
corresponds to the (SWCTRLBTCLKEN & SWCTRLBTCLKSEL) bits enabled in the
control register in the clock manager module of Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-25 10:01:28 -06:00
Dinh Nguyen
3e2c972ca3 ARM: dts: socfpga: add the LTC2977 power monitor on Arria10 devkit
Add the I2C LTC 2977 power monitor that is on the Arria10 devkit.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-04 18:12:10 -06:00
Dinh Nguyen
a0c7807c3e ARM: dts: socfpga: enable watchdog timer on Arria5 and Arria10
Enable the watchdog for Arria5 and Arria10.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
2017-01-04 18:12:10 -06:00
Thor Thayer
acf3b20c23 ARM: dts: socfpga: Add LED framework to A10-SR GPIO
Add the LED framework to the Arria10 System Resource chip GPIO hooks.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18 22:18:12 -05:00
Thor Thayer
07e75f4393 ARM: dts: socfpga: Enable GPIO parent for Arria10 SR chip
Enable the Altera Arria10 GPIO parent for MFD operation.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18 22:18:12 -05:00
Thor Thayer
5984be047d ARM: dts: socfpga: Add Devkit A10-SR fields for Arria10
Add the Altera Arria10 System Resource node. This is a Multi-Function
device with GPIO expander support.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-10-18 22:18:11 -05:00
Matthew Gerlach
b65c0efa35 ARM: dts: socfpga: fix definitions of serial console
The notion of which uart instance is serial0 or serial1
is board specific rather than generic to the chip. This
patch removes the serial aliases from generic chip dtsi
and adds an appropriate alias to the board specific dtsi.
By making the alias for serial0 point to uart1 for the arria10_socdk,
the linux boot command line supports specifying console=ttyS0,115200
for backwards compatibility, and it supports not specifying
the console at all.

Signed-off-by: Matthew Gerlach <mgerlach@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-08 14:09:11 -05:00
Dinh Nguyen
efb6672935 ARM: dts: socfpga: add ethernet alias on Arria10
Without having an ethernet alias, ethernet will have a random MAC address,
versus take an address that was provided from the bootloader.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2016-06-08 14:09:00 -05:00
Dinh Nguyen
19c2138827 ARM: socfpga: dts: enable USB and I2C on Arria10 SoCDK
On the Arria10 Devkit, the I2C bus has a serial EEPROM and an RTC
hanging off it. Also, enable the USB node.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-10-06 04:42:34 -05:00
Dinh Nguyen
efc1985c8f ARM: dts: socfpga: use stdout-path for chosen node
Use stdout-path dts property for kernel console.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-07-20 10:07:50 -05:00
Dinh Nguyen
112cadfd43 ARM: socfpga: dts: enable ethernet for Arria10 devkit
Update the arria10 gmac nodes with all the necessary properties for ethernet
to function on the Arria10 devkit.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
2015-06-10 15:45:12 -07:00
Dinh Nguyen
88c8e4c264 ARM: socfpga: dts: rename socdk board file to socdk_sdmmc
Rename the socfpga_arria10_socdk board file to socfpga_arria10_socdk_sdmmc
as Arria 10 devkit cannot support SDMMC and QSPI at the same time. Thus
we will need to have 2 separate board files, one for SDMMC and one for
QSPI. We also add a new base board dtsi file, socfpga_arria10_socdk.dtsi
so that we use common peripherals for each flavor of the devkits.

Add the sdmmc node to the socfpga_arria10_socdk_sdmmc.dts board file.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
2015-05-11 13:14:59 -05:00