5067 Commits

Author	SHA1	Message	Date
Linus Torvalds	9e259f9352	ARM: 32-bit SoC platform updates ... Most of the SoC updates in this cycle are cleanups and moves to more modern infrastructure: - Davinci was moved to common clock framework - OMAP1-based Amstrad E3 "Superphone" saw a bunch of cleanups to the keyboard interface (bitbanged AT keyboard via GPIO). - Removal of some stale code for Renesas platforms - Power management improvements for i.MX6LL -----BEGIN PGP SIGNATURE----- iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAlt+Lh0PHG9sb2ZAbGl4 b20ubmV0AAoJEIwa5zzehBx3Y+YP/2QVT1T1/Fz3WsuLg7BYa6r51BDxvr/pSQKh eqLhZCcI5RpOlW4noWgJXWqnX2AlR1vX6xe0W0ebj177ttUHmidUQUJCpwP39AGE LrVC2+mlFb3uPx0HlpHsx3zFZdNFfrhl5mN3JbZfnLv0fUibVEhR+K8ii7MV1/Fk Lbo9sVPT8GIJuU6uyTTUnsCufwCkARMhrYbO6cbtS0FCO77a5aHp7btvHZ2ykxwh hG9CI3FhfAP3Tkpm+IbHkC5jYQNRewQoqthzJ4WJbRrcdA/vaArBTOUoZG4NFMOM M3B4jd1x26llmQhUqH4kGeOZiQ714GPrKcGS+8w7Twj5sIRGDxpif2Ac0kKL2B8X Ps6UTM0cb63W9I+TphjLysKSarNjR2lVVhNVoJ8P47MSyDGIRpSR7+IWvlJ7U8vz 1yMWCguwrwZH3DnQb8UINTfI1Y1RstmtO5v8paSqfJyFX5r64x6VfYso1fRzxyFE 4r2TS0HRv117aKkHwY8smjielZ0CpGnyEDQgq9Z72V4FueIqsJQrA3oGYXgTArFl mLL+fJUdwPv00nWuAZ8q0wIj1NvJvksJy+cObZXL6HK9m3cSdYwOHipdG86k20S5 6/KMPmgrMbV9YO3lVtfJZjdu2QTBiYVBPGfsiSo5lVL5Q5rDYV9QBijnE+9W9/yT tJ038MhK =ACVk -----END PGP SIGNATURE----- Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM 32-bit SoC platform updates from Olof Johansson: "Most of the SoC updates in this cycle are cleanups and moves to more modern infrastructure: - Davinci was moved to common clock framework - OMAP1-based Amstrad E3 "Superphone" saw a bunch of cleanups to the keyboard interface (bitbanged AT keyboard via GPIO). - Removal of some stale code for Renesas platforms - Power management improvements for i.MX6LL" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (112 commits) ARM: uniphier: select RESET_CONTROLLER arm64: uniphier: select RESET_CONTROLLER ARM: uniphier: remove empty Makefile ARM: exynos: Clear global variable on init error path ARM: exynos: Remove outdated maintainer information ARM: shmobile: Always enable ARCH_TIMER on SoCs with A7 and/or A15 ARM: shmobile: r8a7779: hide unused r8a7779_platform_cpu_kill soc: r9a06g032: don't build SMP files for non-SMP config ARM: shmobile: Add the R9A06G032 SMP enabler driver ARM: at91: pm: configure wakeup sources for ULP1 mode ARM: at91: pm: add PMC fast startup registers defines ARM: at91: pm: Add ULP1 mode support ARM: at91: pm: Use ULP0 naming instead of slow clock ARM: hisi: handle of_iomap and fix missing of_node_put ARM: hisi: check of_iomap and fix missing of_node_put ARM: hisi: fix error handling and missing of_node_put ARM: mx5: Set the DBGEN bit in ARM_GPC register ARM: imx51: Configure M4IF to avoid visual artifacts ARM: imx: call imx6sx_cpuidle_init() conditionally for 6sll ARM: imx: fix i.MX6SLL build ...	2018-08-23 13:44:43 -07:00
Linus Torvalds	db06f826ec	The new and exciting feature this time around is in the clk core. ... We've added duty cycle support to the clk API so that clk signal duty cycle ratios can be adjusted while taking into account things like clk dividers and clk tree hierarchy. So far only one SoC has implemented support for this, but I expect there will be more to come in the future. Outside of the core, we have the usual pile of clk driver updates and additions. The Amlogic meson driver got the most lines in the diffstat this time around because it added support for a whole bunch of hardware and duty cycle configuration. After that the Rockchip PX30, Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the diff. We're left with the collection of non-critical fixes after that. Overall it looks pretty quiet this time. Core: - Clk duty cycle support - Proper CLK_SET_RATE_GATE support throughout the tree New Drivers: - Actions Semi Owl series S700 SoC clk driver - Qualcomm SDM845 display clock controller - i.MX6SX ocram_s clk support - Uniphier NAND, USB3 PHY, and SPI clk support - Qualcomm RPMh clk driver - i.MX7D mailbox clk support - Maxim 9485 Programmable Clock Generator - Expose 32 kHz PLL on PXA SoCs - imx6sll GPIO clk gate support - Atmel at91 I2S audio clk support - SI544/SI514 clk on/off support - i.MX6UL GPIO clock gates in CCM CCGR - Renesas Crypto Engine clocks on R-Car H3 - Renesas clk support for the new RZ/N1D SoC - Allwinner A64 display engine clock support - Support for Rockchip's PX30 SoC - Amlogic Meson axg PCIe and audio clocks - Amlogic Meson GEN CLK on gxbb, gxl and axg Updates: - Remove an unused variable from Exynos4412 ISP driver - Fix a thinko bug in SCMI clk division logic - Add missing of_node_put()s in some i.MX clk drivers - Tegra SDMMC clk jitter improvements with high speed signaling modes - SPDX tagging for qcom and cs2000-cp drivers - Stop leaking con ids in __clk_put() - Fix a corner case in fixed factor clk probing where node is in DT but parent clk is registered much later - Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return value - i.MX clk init arrays removed in place of CLK_IS_CRITICAL - Convert to CLK_IS_CRITICAL for i.MX51/53 driver - Fix Tegra BPMP driver oops when xlating a NULL clk - Proper default configuration for vic03 and vde clks on Tegra124 - Mark Tegra memory controller clks as critical - Fix array bounds clamp in Tegra's emc determine_rate() op - Ingenic i2s bit update and allow UDC clk to gate - Fix name of aspeed SDC clk define to have only one 'CLK' - Fix i.MX6QDL video clk parent - Critical clk markings for qcom SDM845 - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents - Mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it supplying the pwm used to drive the logic supply of the rk3399 core. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEE9L57QeeUxqYDyoaDrQKIl8bklSUFAlt0WD0RHHNib3lkQGtl cm5lbC5vcmcACgkQrQKIl8bklSX5jBAAlMLb0fqnuAGNJeXZDk5rsCa496LMyGWx ku7uLA2H68SlbSQqq8FUPoCjDZkmsu2CbOX1U2/H4HFDS0pqpPiV3mZNtSeacedp 4Wf8yUB5G3xdq9QUCSX5LxMmEQoGeJ+gaTspBvM6sNvEMBR2kEMGBqUy768tnDTR qCQ8Q1jOU6l8IdFV0SZGssmZ+oFqOyQoJVquPWPkw1+p/2f1KyYIyG5J5FXGxgcR 1XQITY/I/dShQ2wd+ZeDdt+GjZqIXQ06Pt3ruRG7HVP79Zt1XCRJd5dZ2lf+Wj8T 1ul3TWCAMYZ8gCPebLMbBGzKvQJQJcDU6DpIZsrUDN+C6z7KCS9vqeCxP9cF+3jJ LOmA6cWE7z9Vkk9s0I0KJJ2Sw7wRoXzE5OJcwa/yousSz3s9cX+F8SAkdZs77oUF 0XnzPsvwdHI/egQ4UrsStPHM/gOFhsQqo8vvm5xaaTR2AxLKBHuPa9oUv9YpO/P5 J6FCst3qeY3Wp69fJ5/Z058OFOAt81dKXij2fZJBOO4KJy7Kse8Sz5ApybXVAbY5 lfvx+KGMITFqLYrcRIQZmlCuoHcMwI0FtHr9Ens5GXdbrJ+W+FlvP43eLCA0ZmRx 9DidemChj3k3PC3H6tbax/jzV4IIxZdyUoBJ1imL4uyhhaXp/qr45A/aGwNp8Q8a WvkIGm3epK4= =Mcn+ -----END PGP SIGNATURE----- Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The new and exciting feature this time around is in the clk core. We've added duty cycle support to the clk API so that clk signal duty cycle ratios can be adjusted while taking into account things like clk dividers and clk tree hierarchy. So far only one SoC has implemented support for this, but I expect there will be more to come in the future. Outside of the core, we have the usual pile of clk driver updates and additions. The Amlogic meson driver got the most lines in the diffstat this time around because it added support for a whole bunch of hardware and duty cycle configuration. After that the Rockchip PX30, Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the diff. We're left with the collection of non-critical fixes after that. Overall it looks pretty quiet this time. Core: - Clk duty cycle support - Proper CLK_SET_RATE_GATE support throughout the tree New Drivers: - Actions Semi Owl series S700 SoC clk driver - Qualcomm SDM845 display clock controller - i.MX6SX ocram_s clk support - Uniphier NAND, USB3 PHY, and SPI clk support - Qualcomm RPMh clk driver - i.MX7D mailbox clk support - Maxim 9485 Programmable Clock Generator - expose 32 kHz PLL on PXA SoCs - imx6sll GPIO clk gate support - Atmel at91 I2S audio clk support - SI544/SI514 clk on/off support - i.MX6UL GPIO clock gates in CCM CCGR - Renesas Crypto Engine clocks on R-Car H3 - Renesas clk support for the new RZ/N1D SoC - Allwinner A64 display engine clock support - support for Rockchip's PX30 SoC - Amlogic Meson axg PCIe and audio clocks - Amlogic Meson GEN CLK on gxbb, gxl and axg Updates: - remove an unused variable from Exynos4412 ISP driver - fix a thinko bug in SCMI clk division logic - add missing of_node_put()s in some i.MX clk drivers - Tegra SDMMC clk jitter improvements with high speed signaling modes - SPDX tagging for qcom and cs2000-cp drivers - stop leaking con ids in __clk_put() - fix a corner case in fixed factor clk probing where node is in DT but parent clk is registered much later - Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return value - i.MX clk init arrays removed in place of CLK_IS_CRITICAL - convert to CLK_IS_CRITICAL for i.MX51/53 driver - fix Tegra BPMP driver oops when xlating a NULL clk - proper default configuration for vic03 and vde clks on Tegra124 - mark Tegra memory controller clks as critical - fix array bounds clamp in Tegra's emc determine_rate() op - Ingenic i2s bit update and allow UDC clk to gate - fix name of aspeed SDC clk define to have only one 'CLK' - fix i.MX6QDL video clk parent - critical clk markings for qcom SDM845 - fix Stratix10 mpu_free_clk and sdmmc_free_clk parents - mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it supplying the pwm used to drive the logic supply of the rk3399 core" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (85 commits) clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 clk: cs2000-cp: convert to SPDX identifiers clk: scmi: Fix the rounding of clock rate clk: qcom: Add display clock controller driver for SDM845 clk: mvebu: armada-37xx-periph: Remove unused var num_parents clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable clk: actions: Add S700 SoC clock support dt-bindings: clock: Add S700 support for Actions Semi Soc's clk: actions: Add missing REGMAP_MMIO dependency clk: uniphier: add clock frequency support for SPI clk: uniphier: add more USB3 PHY clocks clk: uniphier: add NAND 200MHz clock clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks clk: tegra: Add sdmmc mux divider clock clk: tegra: Refactor fractional divider calculation clk: tegra: Fix includes required by fence_udelay() clk: imx6sll: fix missing of_node_put() clk: imx6ul: fix missing of_node_put() clk: imx: add ocram_s clock for i.mx6sx clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent ...	2018-08-15 21:41:21 -07:00
Stephen Boyd	ac7da1b787	Merge branches 'clk-actions-s700', 'clk-exynos-unused', 'clk-qcom-dispcc-845', 'clk-scmi-round' and 'clk-cs2000-spdx' into clk-next ... * clk-actions-s700: : - Actions Semi Owl series S700 SoC clk driver clk: actions: Add S700 SoC clock support dt-bindings: clock: Add S700 support for Actions Semi Soc's clk: actions: Add missing REGMAP_MMIO dependency * clk-exynos-unused: : - Remove an unused variable from Exynos4412 ISP driver clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable * clk-qcom-dispcc-845: : - Qualcomm SDM845 display clock controller clk: qcom: Add display clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Display clock bindings clk: qcom: Move frequency table macro to common file * clk-scmi-round: : - Fix a thinko bug in SCMI clk division logic clk: scmi: Fix the rounding of clock rate * clk-cs2000-spdx: clk: cs2000-cp: convert to SPDX identifiers	2018-08-14 23:00:15 -07:00
Stephen Boyd	032405a754	Merge branches 'clk-imx6-ocram', 'clk-missing-put', 'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next ... * clk-imx6-ocram: : - i.MX6SX ocram_s clk support clk: imx: add ocram_s clock for i.mx6sx * clk-missing-put: : - Add missing of_node_put()s in some i.MX clk drivers clk: imx6sll: fix missing of_node_put() clk: imx6ul: fix missing of_node_put() * clk-tegra-sdmmc-jitter: : - Tegra SDMMC clk jitter improvements with high speed signaling modes clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks clk: tegra: Add sdmmc mux divider clock clk: tegra: Refactor fractional divider calculation clk: tegra: Fix includes required by fence_udelay() * clk-allwinner: clk: sunxi-ng: add A64 compatible string dt-bindings: add compatible string for the A64 DE2 CCU clk: sunxi-ng: r40: Export video PLLs clk: sunxi-ng: r40: Allow setting parent rate to display related clocks clk: sunxi-ng: r40: Add minimal rate for video PLLs * clk-uniphier: : - Uniphier NAND, USB3 PHY, and SPI clk support clk: uniphier: add clock frequency support for SPI clk: uniphier: add more USB3 PHY clocks clk: uniphier: add NAND 200MHz clock	2018-08-14 22:58:53 -07:00
Stephen Boyd	4a18ef5bab	Merge branches 'clk-qcom-rpmh', 'clk-qcom-spdx', 'clk-con-id-leak', 'clk-fixed-factor-populated' and 'clk-mvebu-periph-parent' into clk-next ... * clk-qcom-rpmh: : - Qualcomm RPMh clk driver clk: qcom: clk-rpmh: Add QCOM RPMh clock driver * clk-qcom-spdx: : - SPDX tagging for qcom clk: qcom: Update SPDX headers for common files * clk-con-id-leak: : - Stop leaking con ids in __clk_put() clk: core: Potentially free connection id * clk-fixed-factor-populated: : - Fix a corner case in fixed factor clk probing where node is in DT but : parent clk is registered much later clk: clk-fixed-factor: Clear OF_POPULATED flag in case of failure * clk-mvebu-periph-parent: : - Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return value clk: mvebu: armada-37xx-periph: Remove unused var num_parents clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent	2018-08-14 22:58:49 -07:00
Stephen Boyd	d16adaf0b9	Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu', 'clk-imx-init-array-cleanup' and 'clk-rockchip' into clk-next ... * clk-mvebu-spdx: clk: mvebu: armada-37xx-periph: switch to SPDX license identifier * clk-meson: clk: meson: add gen_clk clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition clk: meson-axg: add clocks required by pcie driver clk: meson: remove unused clk-audio-divider driver clk: meson: stop rate propagation for audio clocks clk: meson: axg: add the audio clock controller driver clk: meson: add axg audio sclk divider driver clk: meson: add triple phase clock driver clk: meson: add clk-phase clock driver clk: meson: clean-up meson clock configuration clk: meson: remove obsolete register access clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindings clk: meson: audio-divider is one based clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL * clk-imx7d-mu: : - i.MX7D mailbox clk support clk: imx7d: add IMX7D_MU_ROOT_CLK * clk-imx-init-array-cleanup: : - i.MX clk init arrays removed in place of CLK_IS_CRITICAL clk: imx6sx: remove clks_init_on array clk: imx6sl: remove clks_init_on array clk: imx6q: remove clks_init_on array * clk-rockchip: clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 clk: rockchip: fix clk_i2sout parent selection bits on rk3399 clk: rockchip: add clock controller for px30 clk: rockchip: add support for half divider dt-bindings: add bindings for px30 clock controller clk: rockchip: add dt-binding header for px30	2018-08-14 22:58:45 -07:00
Stephen Boyd	139054634b	Merge branches 'clk-imx-critical', 'clk-tegra-bpmp', 'clk-tegra-124', 'clk-tegra-critical' and 'clk-tegra-emc-oob' into clk-next ... * clk-imx-critical: : - Convert to CLK_IS_CRITICAL for i.MX51/53 driver clk: imx51-imx53: Include sizes.h to silence compile errors clk: imx51-imx53: Annotate critical clocks as CLK_IS_CRITICAL * clk-tegra-bpmp: : - Fix Tegra BPMP driver oops when some xlating a NULL clk clk: tegra: bpmp: Don't crash when a clock fails to register * clk-tegra-124: : - Proper default configuration for vic03 and vde clks on Tegra124 clk: tegra: Make vde a child of pll_c3 clk: tegra: Make vic03 a child of pll_c3 * clk-tegra-critical: : - Mark Tegra memory controller clks as critical clk: tegra: Mark Memory Controller clock as critical * clk-tegra-emc-oob: : - Fix array bounds clamp in Tegra's emc determine_rate() op clk: tegra: emc: Avoid out-of-bounds bug	2018-08-14 22:58:42 -07:00
Stephen Boyd	ea4f7872c7	Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', 'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next ... * clk-ingenic-fixes: : - Ingenic i2s bit update and allow UDC clk to gate clk: ingenic: Add missing flag for UDC clock clk: ingenic: Fix incorrect data for the i2s clock * clk-max9485: : - Maxim 9485 Programmable Clock Generator clk: Add driver for MAX9485 dts: clk: add devicetree bindings for MAX9485 * clk-pxa-32k-pll: : - Expose 32 kHz PLL on PXA SoCs clk: pxa: export 32kHz PLL * clk-aspeed: : - Fix name of aspeed SDC clk define to have only one 'CLK' clk: aspeed: Fix SDCLK name * clk-imx6sll-gpio: : - imx6sll GPIO clk gate support clk: imx6sll: add GPIO LPCGs	2018-08-14 22:58:39 -07:00
Stephen Boyd	b183c6887a	Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', 'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next ... * clk-imx6-video-parent: : - Fix i.MX6QDL video clk parent clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL * clk-qcom-sdm845-criticals: : - critical clk markings for qcom SDM845 clk: qcom: Enable clocks which needs to be always on for SDM845 * clk-renesas: clk: renesas: Renesas R9A06G032 clock driver dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation dt-bindings: clock: Add the r9a06g032-sysctrl.h file clk: renesas: r8a7795: Add CCREE clock clk: renesas: r8a7795: Add CR clock * clk-stratix10-fixes: : - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents clk: socfpga: stratix10: fix the sdmmc_free_clk mux clk: socfpga: stratix10: fix the parents of mpu_free_clk * clk-atmel-i2s: : - Atmel at91 I2S audio clk support clk: at91: add I2S clock mux driver dt-bindings: clk: at91: add an I2S mux clock	2018-08-14 22:58:35 -07:00
Stephen Boyd	5ef7748ba3	Merge branches 'clk-qcom-set-rate-gate', 'clk-core-set-rate-gate', 'clk-core-duty-cycle', 'clk-si-prepare' and 'clk-imx-gpio-gates' into clk-next ... * clk-qcom-set-rate-gate: clk: qcom: drop CLK_SET_RATE_GATE from sdc clocks * clk-core-set-rate-gate: clk: fix CLK_SET_RATE_GATE with clock rate protection * clk-core-duty-cycle: clk: add duty cycle support * clk-si-prepare: : - SI544/SI514 clk on/off support clk-si514, clk-si544: Implement prepare/unprepare/is_prepared operations * clk-imx-gpio-gates: : - i.MX6UL GPIO clock gates in CCM CCGR clk: imx6ul: remove clks_init_on array clk: imx6ul: add GPIO clock gates dt-bindings: clock: imx6ul: Do not change the clock definition order	2018-08-14 22:58:30 -07:00
Linus Torvalds	747f62305d	sound updates for 4.19 ... It's been busy summer weeks and hence lots of changes, partly for a few new drivers and partly for a wide range of fixes. Here are highlights: ALSA Core: - Fix rawmidi buffer management, code cleanup / refactoring - Fix the SG-buffer page handling with incorrect fallback size - Fix the stall at virmidi trigger callback with a large buffer; also offloading and code-refactoring along with it - Various ALSA sequencer code cleanups ASoC: - Deploy the standard snd_pcm_stop_xrun() helper in several drivers - Support for providing name prefixes to generic component nodes - Quite a few fixes for DPCM as it gains a bit wider use and more robust testing - Generalization of the DIO2125 support to a simple amplifier driver - Accessory detection support for the audio graph card - DT support for PXA AC'97 devices - Quirks for a number of new x86 systems - Support for AM Logic Meson, Everest ES7154, Intel systems with RT5682, Qualcomm QDSP6 and WCD9335, Realtek RT5682 and TI TAS5707 HD-audio: - Code refactoring in HD-audio ext codec codes to drop own classes; preliminary works for the upcoming legacy codec support - Generalized DRM audio component for the upcoming radeon / amdgpu support - Unification of mic mute-LED and GPIO support for various codecs - Further improvement of CA0132 codec support including Recon3D - Proper vga_switcheroo handling for AMD i-GPU - Update of model list in documentation - Fixups for another HP Spectre x360, Conexant codecs, power-save blacklist update USB-audio: - Fix the invalid sample rate setup with external clock - Support of UAC3 selector units and processing units - Basic UAC3 power-domain support - Support for Encore mDSD and Thesycon-based DSD devices - Preparation for future complete callback changes Firewire: - Add support for MOTU Traveler Misc: - The endianess notation fixes in various drivers - Add fall-through comment in lots of drivers - Various sparse warning fixes, e.g. about PCM format types -----BEGIN PGP SIGNATURE----- iQJCBAABCAAsFiEEIXTw5fNLNI7mMiVaLtJE4w1nLE8FAltxhXUOHHRpd2FpQHN1 c2UuZGUACgkQLtJE4w1nLE9BPxAAnJyKM2IcfVKanjFZQmM4w1gEM3nt+EBvbOF5 155Mq5ELNLxwwCav0eyoeTVD+mB4UO1y9+64SK73dUzBvj7llILs8s5VNMg7KYn6 MnYMo0UIDlvQ/ZwJzzpU04QZVOIHa5HK9XG+u+Fycr8YOCdhGD6m/zGiBStd/xGd Bvgw2eHF10l+zqN+Vf+1P2/ENRyNxLYpJYYC02zl0nfXP29ZY+CjicDoRvD8/97X Pe5Jcfj/4oJZlN0MMXfLLP0vaWbUyogG3a4mzVRC+wHG2FZ5hGfFb92mfT8Yce3H dq9eaih6zMMiDuP4ipClMv/0t64cA8HD+Du/Enq9Jc/g41QAU1JFzj4qi1Ga7S2w F80uWCedwZ5FLXYAAK2kIunIaaD5phD+8DegzchiVzL6eg7BLmi/Rsfg9VkuC1Ir ZZERtT07XCzwXke0IAQQ1yhTE/uMxqntCJlZ0FoohvIABgH0jvrpp/cdDYFdC3it TaNk9REAuCVjr2ket1Jrw6pKNgtry7cDkKFK5d8S5HTNFEL+sWwz2NcSdPNRIIFT aqeUWt/H1P5G25if/636UJtf+EtlRPqC2Eng8OpY8hitb2vB3trjY25T4a5x5FW5 S4oTyVWmxa4Xxj4QMMhpo7jxxwsux8J1fghDCpEqekiwt72CyVP2UN/cU8HJL7kN IWqnZgg= =eTIC -----END PGP SIGNATURE----- Merge tag 'sound-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound Pull sound updates from Takashi Iwai: "It's been busy summer weeks and hence lots of changes, partly for a few new drivers and partly for a wide range of fixes. Here are highlights: ALSA Core: - Fix rawmidi buffer management, code cleanup / refactoring - Fix the SG-buffer page handling with incorrect fallback size - Fix the stall at virmidi trigger callback with a large buffer; also offloading and code-refactoring along with it - Various ALSA sequencer code cleanups ASoC: - Deploy the standard snd_pcm_stop_xrun() helper in several drivers - Support for providing name prefixes to generic component nodes - Quite a few fixes for DPCM as it gains a bit wider use and more robust testing - Generalization of the DIO2125 support to a simple amplifier driver - Accessory detection support for the audio graph card - DT support for PXA AC'97 devices - Quirks for a number of new x86 systems - Support for AM Logic Meson, Everest ES7154, Intel systems with RT5682, Qualcomm QDSP6 and WCD9335, Realtek RT5682 and TI TAS5707 HD-audio: - Code refactoring in HD-audio ext codec codes to drop own classes; preliminary works for the upcoming legacy codec support - Generalized DRM audio component for the upcoming radeon / amdgpu support - Unification of mic mute-LED and GPIO support for various codecs - Further improvement of CA0132 codec support including Recon3D - Proper vga_switcheroo handling for AMD i-GPU - Update of model list in documentation - Fixups for another HP Spectre x360, Conexant codecs, power-save blacklist update USB-audio: - Fix the invalid sample rate setup with external clock - Support of UAC3 selector units and processing units - Basic UAC3 power-domain support - Support for Encore mDSD and Thesycon-based DSD devices - Preparation for future complete callback changes Firewire: - Add support for MOTU Traveler Misc: - The endianess notation fixes in various drivers - Add fall-through comment in lots of drivers - Various sparse warning fixes, e.g. about PCM format types" * tag 'sound-4.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (529 commits) ASoC: adav80x: mark expected switch fall-through ASoC: da7219: Add delays to capture path to remove DC offset noise ALSA: usb-audio: Mark expected switch fall-through ALSA: mixart: Mark expected switch fall-through ALSA: opl3: Mark expected switch fall-through ALSA: hda/ca0132 - Add exit commands for Recon3D ALSA: hda/ca0132 - Change mixer controls for Recon3D ALSA: hda/ca0132 - Add Recon3D input and output select commands ALSA: hda/ca0132 - Add DSP setup defaults for Recon3D ALSA: hda/ca0132 - Add Recon3D startup functions and setup ALSA: hda/ca0132 - Add bool variable to enable/disable pci region2 mmio ALSA: hda/ca0132 - Add Recon3D pincfg ALSA: hda/ca0132 - Add quirk ID and enum for Recon3D ALSA: hda/ca0132 - Add alt_functions unsolicited response ALSA: hda/ca0132 - Clean up ca0132_init function. ALSA: hda/ca0132 - Create mmio gpio function to make code clearer ASoC: wm_adsp: Make DSP name configurable by codec driver ASoC: wm_adsp: Declare firmware controls from codec driver ASoC: max98373: Added software reset register to readable registers ASoC: wm_adsp: Correct DSP pointer for preloader control ...	2018-08-14 14:10:30 -07:00
Linus Torvalds	c2d9f5bc2d	Merge branch 'clkdev' of git://git.armlinux.org.uk/~rmk/linux-arm ... Pull ARM clkdev updates from Russell King: "A couple of cleanups for clkdev" * 'clkdev' of git://git.armlinux.org.uk/~rmk/linux-arm: ARM: 8778/1: clkdev: don't call __of_clk_get_by_name() unnecessarily from clk_get() ARM: 8776/1: clkdev: Remove duplicated negative index check from __of_clk_get()	2018-08-13 19:15:48 -07:00
Bartosz Golaszewski	53ccb22b8d	ARM: 8778/1: clkdev: don't call __of_clk_get_by_name() unnecessarily from clk_get() ... The way this function is implemented caused some confusion when converting the TI DaVinci platform to using the common clock framework. Current kernel supports booting DaVinci boards both in device tree as well as legacy, board-file mode. In the latter, we always end up calling clk_get_sys() as of_node is NULL and __of_clk_get_by_name() returns -ENOENT. It was not obvious at first glance how clk_get(dev, NULL) will work in board-file mode since we always call __of_clk_get_by_name(). Let's make it clearer by checking if of_node is NULL and skipping right to clk_get_sys(). Cc: Sekhar Nori <nsekhar@ti.com> Cc: Kevin Hilman <khilman@baylibre.com> Cc: David Lechner <david@lechnology.com> Reviewed-by: David Lechner <david@lechnology.com> Reviewed-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>	2018-08-13 16:27:52 +01:00
Mark Brown	4aa5db22d3	Merge branch 'asoc-4.19' into asoc-next	2018-08-09 14:47:05 +01:00
Levin Du	640332d1a0	clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 ... PWM2 is commonly used to control voltage of PWM regulator of VDD_LOG in RK3399. On the Firefly-RK3399 board, PWM2 outputs 40 KHz square wave from power on and the VDD_LOG is about 0.9V. When the kernel boots normally into the system, the PWM2 keeps outputing PWM signal. But the kernel hangs randomly after "Starting kernel ..." line on that board. When it happens, PWM2 outputs high level which causes VDD_LOG drops to 0.4V below the normal operating voltage. By adding "pclk_rkpwm_pmu" to the rk3399_pmucru_critical_clocks array, PWM clock is ensured to be prepared at startup and the PWM2 output is normal. After repeated tests, the early boot hang is gone. This patch works on both Firefly-RK3399 and ROC-RK3399-PC boards. Signed-off-by: Levin Du <djw@t-chip.com.cn> Signed-off-by: Heiko Stuebner <heiko@sntech.de>	2018-08-06 23:46:52 +02:00
Kuninori Morimoto	67075b3cb8	clk: cs2000-cp: convert to SPDX identifiers ... Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-08-02 13:55:00 -07:00
Amit Daniel Kachhap	7a8655e19b	clk: scmi: Fix the rounding of clock rate ... This fix rounds the clock rate properly by using quotient and not remainder in the calculation. This issue was found while testing HDMI in the Juno platform. Fixes: 6d6a1d82ea ("clk: add support for clocks provided by SCMI") Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-08-02 13:43:48 -07:00
Taniya Das	81351776c9	clk: qcom: Add display clock controller driver for SDM845 ... Add support for the display clock controller found on SDM845 based devices. This would allow display drivers to probe and control their clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Remove CLK_GET_RATE_NOCACHE everywhere] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-08-01 08:08:12 -07:00
Anders Roxell	8927c27b32	clk: mvebu: armada-37xx-periph: Remove unused var num_parents ... When building armada-37xx-periph, num_parents isn't used in function clk_pm_cpu_get_parent: drivers/clk/mvebu/armada-37xx-periph.c: In function ‘clk_pm_cpu_get_parent’: drivers/clk/mvebu/armada-37xx-periph.c:419:6: warning: unused variable ‘num_parents’ [-Wunused-variable] int num_parents = clk_hw_get_num_parents(hw); ^~~~~~~~~~~ Remove the declaration of num_parents to dispose the warning. Fixes: 616bf80d38 ("clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent") Signed-off-by: Anders Roxell <anders.roxell@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-27 09:55:43 -07:00
Krzysztof Kozlowski	96455f734b	clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable ... Remove unused 'mout_user_aclk400_mcuisp_p4x12' variable to fix GCC warning: drivers/clk/samsung/clk-exynos4412-isp.c:40:27: warning: 'mout_user_aclk400_mcuisp_p4x12' defined but not used [-Wunused-const-variable=] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-26 00:38:51 -07:00
Saravanan Sekar	d47317ca4a	clk: actions: Add S700 SoC clock support ... Add Actions Semi S700 SoC clock support Signed-off-by: Parthiban Nallathambi <pn@denx.de> Signed-off-by: Saravanan Sekar <sravanhome@gmail.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 16:40:54 -07:00
Saravanan Sekar	d017c1f16a	clk: actions: Add missing REGMAP_MMIO dependency ... Add REGMAP_MMIO as dependency to avoid undefined reference to regmap symbols. Fixes: d85d20053e ("clk: actions: Add S900 SoC clock support") Signed-off-by: Saravanan Sekar <sravanhome@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 16:40:52 -07:00
Kunihiko Hayashi	ff388ee365	clk: uniphier: add clock frequency support for SPI ... Add clock control for SPI controller on UniPhier SoCs. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 16:26:18 -07:00
Masahiro Yamada	9d222574ef	clk: uniphier: add more USB3 PHY clocks ... Add USB3 PHY clocks where missing. Use fixed-factor clocks for those without gating. For clarification, prefix clock names with 'ss' or 'hs'. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 15:45:32 -07:00
Masahiro Yamada	0316c018c5	clk: uniphier: add NAND 200MHz clock ... The Denali NAND controller IP needs three clocks: - clk: controller core clock - clk_x: bus interface clock - ecc_clk: clock at which ECC circuitry is run Currently, only the first one (50MHz) is provided. The rest of the two clock ports must be connected to the 200MHz clock line. Add this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 15:45:25 -07:00
Peter De-Schrijver	c76a69e477	clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks ... These clocks have low jitter paths to certain parents. To model these correctly, use the sdmmc mux divider clock type. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 14:26:22 -07:00
Peter De-Schrijver	633e79650b	clk: tegra: Add sdmmc mux divider clock ... Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 13:45:09 -07:00
Peter De Schrijver	cb3ac5947a	clk: tegra: Refactor fractional divider calculation ... Move this to a separate file so it can be used to calculate the sdmmc clock dividers. Signed-off-by: Peter De-Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 13:43:34 -07:00
Aapo Vienamo	0cbb61a313	clk: tegra: Fix includes required by fence_udelay() ... Add the missing linux/delay.h include statement for udelay() used by fence_udelay() macro. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 13:43:13 -07:00
Nicholas Mc Guire	7f5eac5934	clk: imx6sll: fix missing of_node_put() ... of_find_compatible_node() is returning a device node with refcount incremented and must be explicitly decremented after the last use which is right after the us in of_iomap() here. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Fixes: 4a5f720b65 ("clk: imx: add clock driver for imx6sll") Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 13:35:00 -07:00
Nicholas Mc Guire	11177e7a7a	clk: imx6ul: fix missing of_node_put() ... of_find_compatible_node() is returning a device node with refcount incremented and must be explicitly decremented after the last use which is right after the us in of_iomap() here. Signed-off-by: Nicholas Mc Guire <hofrat@osadl.org> Fixes: 787b4271a6 ("clk: imx: add imx6ul clk tree support") Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 13:34:57 -07:00
Anson Huang	d7b7c00dad	clk: imx: add ocram_s clock for i.mx6sx ... i.MX6SX has a 16KB always-on ocram bank called ocram_s, and its clock gate in CCM CCGR1 CG14 needs to be enabled before access, add it to clock tree. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 09:44:58 -07:00
Gregory CLEMENT	616bf80d38	clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent ... The return value of the get_parent operation is a u8, whereas a -EINVAL was returned. This wrong value was return if the value was bigger that the number of parent but this case was already handled by the core. So we can just remove this chunk of code to fix the issue. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Fixes: 9818a7a4fd ("clk: mvebu: armada-37xx-periph: prepare cpu clk to be used with DVFS") Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 09:42:50 -07:00
Rajan Vaja	f6dab4233d	clk: clk-fixed-factor: Clear OF_POPULATED flag in case of failure ... Fixed factor clock has two initializations at of_clk_init() time and during platform driver probe. Before of_clk_init() call, node is marked as populated and so its probe never gets called. During of_clk_init() fixed factor clock registration may fail if any of its parent clock is not registered. In this case, it doesn't get chance to retry registration from probe. Clear OF_POPULATED flag if fixed factor clock registration fails so that clock registration is attempted again from probe. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 09:36:46 -07:00
Mikko Perttunen	365f7a89c8	clk: core: Potentially free connection id ... Patch "clk: core: Copy connection id" made it so that the connector id 'con_id' is kstrdup_const()ed to cater to drivers that pass non-constant connection ids. The patch added the corresponding kfree_const to __clk_free_clk(), but struct clk's can be freed also via __clk_put(). Add the kfree_const call to __clk_put() and add comments to both functions to remind that the logic in them should be kept in sync. Fixes: 253160a8ad ("clk: core: Copy connection id") Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 09:29:12 -07:00
Taniya Das	f9419783a6	clk: qcom: Update SPDX headers for common files ... SPDX headers updated for common/branch/pll/regmap files. Signed-off-by: Taniya Das <tdas@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-25 09:23:33 -07:00
Taniya Das	9c7e47025a	clk: qcom: clk-rpmh: Add QCOM RPMh clock driver ... Add the RPMh clock driver to control the RPMh managed clock resources on some of the Qualcomm Technologies, Inc. SoCs. Signed-off-by: Taniya Das <tdas@codeaurora.org> [sboyd@kernel.org: Clean up whitespace, indentation, remove cmd_db_ready check] Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-16 10:25:04 -07:00
Joel Stanley	565b9937f4	clk: aspeed: Support HPLL strapping on ast2400 ... The HPLL can be configured through a register (SCU24), however some platforms chose to configure it through the strapping settings and do not use the register. This was not noticed as the logic for bit 18 in SCU24 was confused: set means programmed, but the driver read it as set means strapped. This gives us the correct HPLL value on Palmetto systems, from which most of the peripheral clocks are generated. Fixes: 5eda5d79e4 ("clk: Add clock driver for ASPEED BMC SoCs") Cc: stable@vger.kernel.org # v4.15 Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-11 09:34:25 -07:00
Geert Uytterhoeven	76672e2e5b	ARM: 8776/1: clkdev: Remove duplicated negative index check from __of_clk_get() ... __of_clk_get() calls of_parse_phandle_with_args(), which rejects negative indices since commit bd69f73f2c ("of: Create function for counting number of phandles in a property"). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>	2018-07-11 11:02:48 +01:00
Oleksij Rempel	30343897d8	clk: imx7d: add IMX7D_MU_ROOT_CLK ... This clock is needed for iMX mailbox driver Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-09 09:55:19 -07:00
Gregory CLEMENT	66c7bb7c41	clk: mvebu: armada-37xx-periph: switch to SPDX license identifier ... Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-09 09:44:49 -07:00
Gregory CLEMENT	61c40f35f5	clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz ... Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz respectively) to L0 frequency (1.2 Ghz) requires a significant amount of time to let VDD stabilize to the appropriate voltage. This amount of time is large enough that it cannot be covered by the hardware countdown register. Due to this, the CPU might start operating at L0 before the voltage is stabilized, leading to CPU stalls. To work around this problem, we prevent switching directly from the L2/L3 frequencies to the L0 frequency, and instead switch to the L1 frequency in-between. The sequence therefore becomes: 1. First switch from L2/L3(200/300MHz) to L1(600MHZ) 2. Sleep 20ms for stabling VDD voltage 3. Then switch from L1(600MHZ) to L0(1200Mhz). It is based on the work done by Ken Ma <make@marvell.com> Cc: stable@vger.kernel.org Fixes: 2089dc33ea ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks") Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>	2018-07-09 09:44:06 -07:00
Jerome Brunet	7df533a7e3	clk: meson: add gen_clk ... GEN_CLK is able to route several internal clocks to one of the SoC pads. In the future, even more clocks could be made accessible using cts_msr_clk - the clock measure block. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>	2018-07-09 13:49:31 +02:00
Jerome Brunet	80d396b511	clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition ... HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition Fixes: 738f66d321 ("clk: gxbb: add AmLogic GXBB clk controller driver") Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>	2018-07-09 13:49:22 +02:00
Yixun Lan	cddcb20b2b	clk: meson-axg: add clocks required by pcie driver ... Adding clocks for the pcie driver. Due to the ASIC design, the pcie controller re-use part of the mipi clock logic, so the mipi clock is also added. Tested-by: Jianxin Qin <jianxin.qin@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> [amended to remove unnecessary locales] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>	2018-07-09 13:49:11 +02:00
Jerome Brunet	85ddc1a32c	clk: meson: remove unused clk-audio-divider driver ... clk-audio-divider is no longer used, we can remove it. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>	2018-07-09 13:48:59 +02:00
Jerome Brunet	9799d5ae00	clk: meson: stop rate propagation for audio clocks ... It is actually a lot easier to setup the PLL with carefully chosen rates than relying on CCF clock propagation for this audio use case. This way, we can make sure we will always be able to provide the common audio clock rates, while having the PLL in the optimal operating range. For this, we stop the rate propagation at the mux picking the PLL and let it round to the closest matching PLL. Doing so, we can use the generic divider for the i2s clock. clk-audio-divider is no longer required. It was a (poor) attempt to use CCF rate propagation while making sure the PLL rate would be high enough to work with audio use cases. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>	2018-07-09 13:48:59 +02:00
Jerome Brunet	1cd5018175	clk: meson: axg: add the audio clock controller driver ... The axg audio clock controller is the clock generation unit for the amlogic audio subsystem of A113 based SoCs. It may be clocked by 8 different plls provided by the primary clock controller and also by 10 slave bit clocks and 10 slave sample clocks which may be provided by external components, such as audio codecs, through the SoC pads. It contains several muxes, dividers and gates which are fed into the the different devices of the audio subsystem. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>	2018-07-09 13:48:26 +02:00
Jerome Brunet	3054a55c5d	clk: meson: add axg audio sclk divider driver ... Add a driver to control the clock divider found in the sample clock generator of the axg audio clock controller. The sclk divider accumulates specific features which make the generic divider unsuitable to control it: - zero based divider (div = val + 1), but zero value gates the clock, so minimum divider value is 2. - lrclk variant may adjust the duty cycle depending the divider value and the 'hi' value. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>	2018-07-09 13:48:25 +02:00
Jerome Brunet	2eb2a01b64	Merge remote-tracking branch 'clk/clk-core-duty-cycle' into next/drivers	2018-07-09 13:47:38 +02:00