This adds support for the Marvell switch and names the network
ports according to the labels, that can be found next to the
connectors ("ID", "IX", "ePort 1", "ePort 2"). The switch is
connected to the host system using a PCI based network card.
The PCI bus configuration has been written using the following
information:
root@b850v3# lspci -tv
-[0000:00]---00.0-[01]----00.0-[02-05]--+-01.0-[03]----00.0 Intel Corporation I210 Gigabit Network Connection
+-02.0-[04]----00.0 Intel Corporation I210 Gigabit Network Connection
\-03.0-[05]--
root@b850v3# lspci -nn
00:00.0 PCI bridge [0604]: Synopsys, Inc. Device [16c3:abcd] (rev 01)
01:00.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
02:01.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
02:02.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
02:03.0 PCI bridge [0604]: PLX Technology, Inc. PEX 8605 PCI Express 4-port Gen2 Switch [10b5:8605] (rev ab)
03:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)
04:00.0 Ethernet controller [0200]: Intel Corporation I210 Gigabit Network Connection [8086:1533] (rev 03)
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
The IPU that drives HDMI must have its pre_sel set to pll2_pfd_396m
to avoid stepping on the LVDS output's toes, as the PLL can't be clocked
to the pixel clock and to the LVDS serial clock (3.5*pixel clock) at the
same time.
As we are using ipu1_di0 and ipu2_di0, ensure both are switched to
to pll2_pfd2_396m to avoid issues. The LDB driver will switch the
required IPU to ldb_di1 when it uses it to drive LVDS.
Signed-off-by: Martyn Welch <martyn.welch@collabora.co.uk>
Signed-off-by: Romain Perier <romain.perier@collabora.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The license text has been mangled at some point then copy pasted across
multiple files. Restore it to what it should be.
Note that this is not intended as a license change.
Reviewed-by: Heiko Schocher <hs@denx.de>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Afzal Mohammed <afzal.mohd.ma@gmail.com>
Acked-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The default monitor that ships with B850v3 requires a 65MHz pixel clock.
65MHz can not be achieved using PLL3 (480MHz/7=68.5MHz). Hence set the
LDB_DIx clock source to PLL5. Since PLL5 is already in use by IPU1_DIx,
set the clock source for IPU1_DIx to PLL2_PFD2 to allow simultaneous
display on both LVDS and HDMI interface.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Remove ldb panel entry for the following reasons:
- The b850v3 has an onboard LVDS to DisplayPort converter (STDP4028). So
we should not limit the monitors that can be connected by hardcoding the
auo,b133htn01 1080p panel.
- The default resolution on the LVDS interface needs to be WXGA or less.
Otherwise when a 1080p monitor is connected to the HDMI port there is no
output on both the LVDS and HDMI ports since a single IPU on i.MX6 can
not handle two 1080p displays. With the panel entry removed from the
devicetree, drm driver defaults the resolution on LVDS interface to XGA.
Once in userspace, applications can set the desired resolution on LVDS
interface over IPU2 CRTC.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
