AuxXxilium/linux_dsm_epyc7002
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2 Commits

Author SHA1 Message Date
Chunyan Zhang
5e75ea9c67 clk: sprd: add missing kfree 
The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.

Fixes: 3e37b00558 ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2019-09-17 22:01:02 -07:00
Chunyan Zhang
3e37b00558 clk: sprd: add adjustable pll support 
Introduced a common adjustable pll clock driver for Spreadtrum SoCs.

Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
 2017-12-21 15:00:53 -08:00