Fixes gcc '-Wunused-but-set-variable' warning:
sound/soc/codecs/tlv320aic32x4.c: In function 'aic32x4_setup_clocks':
sound/soc/codecs/tlv320aic32x4.c:669:16: warning: variable 'mclk_rate' set but not used [-Wunused-but-set-variable]
It is not used since introduction in
commit 96c3bb0023 ("ASoC: tlv320aic32x4: Dynamically Determine Clocking")
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
PowerTune controls the power level of the chip. On playback this
indirectly controls things like the gain of the various output
amplifiers. This can allow for the decrease of output levels
from the codec. This adds controls for those power levels to
the driver.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add a switch for setting common mode voltage. This can allow
for higher drive levels on the amplifier outputs.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The common pins were mistakenly not added to the DAPM graph.
Adding these pins will allow valid graphs to be created.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The clocking and processing blocks are now properly set up to
support 192000 sample rates. Allow drivers to ask for that.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
mclk is not used by anything anymore. Remove support for it.
All that information now comes from the clock tree.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The sysclk is now managed by the CCF. Change this function
to merely find the system clock and set it using
clk_set_rate.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The existing code uses a static lookup table to determine the
settings of the various clock devices on board the chip. This is
limiting in a couple of ways. First, this doesn't allow for any
master clock rates other than the three that have been
precalculated. Additionally, new sample rates are difficult to
add to the table. Witness that the chip is capable of 192000 Hz
sampling, but it is not provided by this driver. Last, if the
driver is clocked by something that isn't a crystal, the
upstream clock may not be able to achieve exactly the rate
requested in the driver. This will mean that clocking will be
slightly off for the sampling clock or that it won't work at all.
This patch determines the settings for all of the clocks at
runtime considering the real conditions of the clocks in the
system. The rules for the clocks are in TI's SLAA557 application
guide on pages 37, 51 and 77.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Move these to separate helper functions. This looks cleaner and fits
better with the new clock setting in CCF.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Control the clock gating to the various clock components to use
the CCF. This allows us to prepare_enalbe only 3 clocks and the
relationships assigned to them will cause upstream clockss to
enable automatically. Additionally we can do this in a single
call to the CCF.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Model and manage BDIV divider as components in the Core
Clock Framework. This should allow us to do some more complex
clock management and power control. Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Model and manage DAC/ADC dividers as components in the Core
Clock Framework. This should allow us to do some more complex
clock management and power control. Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Model and manage codec clock input as a component in the Core
Clock Framework. This should allow us to do some more complex
clock management and power control. Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Model and manage the on-board PLL as a component in the Core
Clock Framework. This should allow us to do some more complex
clock management and power control. Also, some of the
on-board chip clocks can be exposed to the outside, and this
change will make those clocks easier to consume by other
parts of the kernel.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Different processing blocks are required for different sampling
rates and power parameters. Set the processing blocks based
on this information.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Break the clock setting logic out from the main hw_params. It's
rather large and unweildy and makes for a large function. This
also better enables some of the following changes to the clock
tree access in the driver.
Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
As stated in 'TLV320AIC3254 Application Reference Guide' ([1]):
3.2 Device Startup Lockout Times
After the TLV320AIC3254 initializes through hardware reset at power-up
or software reset, the internal registers initialize to default values.
This initialization takes place within 1ms after pulling the RESET
signal high. During this initialization phase, no register-read or
register-write operation should be performed on ADC or DAC coefficient
buffers. Also, no block within the codec should be powered up during
the initialization phase.
[1] http://www.ti.com/lit/an/slaa408a/slaa408a.pdf
Signed-off-by: Peter Seiderer <ps.report@gmx.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
Quite a big batch of fixes here. There's a couple of things going on,
the main one is that we found some issues with not deferring probe when
we should, causing us to skip some driver initialization. The fixes for
this then in turn exposed some issues with how we were searching for
components which had previously gone unnoticed due to the original
issue.
There's also been the normal driver specific stuff and there's been what
looks like several batches of automated scanning for issues which have
generated quite a large set of smaller fixes for potential crashes and
missed error handling.
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Merge tag 'asoc-fix-v5.0-rc2' into asoc-5.1
ASoC: Fixes for v5.0
Quite a big batch of fixes here. There's a couple of things going on,
the main one is that we found some issues with not deferring probe when
we should, causing us to skip some driver initialization. The fixes for
this then in turn exposed some issues with how we were searching for
components which had previously gone unnoticed due to the original
issue.
There's also been the normal driver specific stuff and there's been what
looks like several batches of automated scanning for issues which have
generated quite a large set of smaller fixes for potential crashes and
missed error handling.
SND_SOC_DAPM_MICBIAS is deprecated, replace it with SND_SOC_DAPM_SUPPLY.
MICBIAS voltage wasn't supplied to the microphone with the older
SND_SOC_DAPM_MICBIAS widget, hence the microphone wouldn't work.
This patch fixes the problem.
Signed-off-by: b-ak <anur.bhargav@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
During the bootup of the kernel, the DAPM bias level is in the OFF
state. As soon as the DAPM framework kicks in it pushes the codec
into STANDBY state.
The probe function doesn't prepare the clock, and STANDBY state
does a clk_disable_unprepare() without checking the previous state.
This leads to an OOPS.
Not transitioning from an OFF state to the STANDBY state fixes the
problem.
Signed-off-by: b-ak <anur.bhargav@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
Make the code easier to read by using snd_soc_update_bits() over
read/modify/write sequences.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Make the code easier to read by using snd_soc_update_bits() over
read/modify/write sequences. Also use separate per-register
variables instead of re-using "data". This can prevent accidental
over-writing and makes it clear for which register each bit value is
intended.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Simplify mute function by using snd_soc_update_bits() over
read/modify/write style code.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Inter-register definitions should use BIT and GENMASK definitions
and also be grouped by what register they belong to. This makes it
easy to cross-check with the datasheet and is consistent with other
drivers.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Setting the DATALEN bit field requires shifting our value by 4. Setting
the OSR value of the PLL divider also requires a shift by 4. Currently
the code abuses this fact and uses the shift for the divider register to
set the data-length register. Fix this here by using the definition meant
for this register.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Setting the DATATYPE bit field requires shifting our value by 6. Setting
the J value of the PLL also requires a shift by 6. Currently the code
abuses this fact and uses the shift for the PLL register to set the
data-type register. Fix this here by using the definition meant for
this register.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Drop definition of frequencies that only map from one number to
the same number. This is not needed and if misused can hide
bugs.
Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Declare snd_soc_codec_driver structures as const as they are only passed
as an argument to the function snd_soc_register_codec. This argument is
of type const, so declare the structures with this property as const.
In file codecs/sn95031.c, snd_soc_codec_driver structure is also used in
a copy operation along with getting passed to snd_soc_register_codec.
So, it can be made const too.
Done using Coccinelle:
@match disable optional_qualifier@
identifier s;
position p;
@@
static struct snd_soc_codec_driver s@p={...};
@good1@
identifier match.s;
position p;
@@
snd_soc_register_codec(...,&s@p,...)
@bad@
identifier match.s;
position p!={match.p,good1.p};
@@
s@p
@depends on !bad disable optional_qualifier@
identifier match.s;
@@
static
+const
struct snd_soc_codec_driver s={...};
Signed-off-by: Bhumika Goyal <bhumirks@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Add the ability to configure the MFP1->MFP5 registers
as GPIOs. In addition adding ALSA controls to get and set
the GPIO state.
Per the data sheet each MFP can be configured as a GPIO
input only, output only or either an input or output.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
codec driver and component driver has duplicated callback functions,
and codec side functions are just copied to component side when
register timing. This was quick-hack, but no longer needed.
This patch moves these functions from codec driver to component driver.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
The TLV320AIC32x4 has a very flexible mixer on the inputs to the ADCs. Each
mixer has an available set of available pins that can be connected to the
ADC positive and negative pins via three different resistor values. This
allows for configuration of differential inputs as well as doing level
manipulation between sources going into the mixers.
The current code only provides positive pins and I implemented the resistors
in an earlier patch. It turns out that it appears to more accurately model
what's happening to implement each of the pins as a MUX rather than on/off
switches and a mixer. This way each pin can be set to its desired resistor
value. Since there are no switches, the mixer is no longer necessary in the
DAPM path. I set the DAPM paths such that the "off" position of any of the
MUXes turns the path off.
This should allow for any input confiuration available on the codec.
Signed-off-by: Jeremy McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The input mixers support routing the IN1_R pin to the Left PGA and the
IN2_L pin to the Right PGA. This patch allows for those routings.
Signed-off-by: Jeremy McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The input pins of the aic3204 have resistors inline with them. The
current code assumes that you want a 10k resistor inline with your
inputs and implements it as a simple switch. This patch creates an enum
for each pin and allows you to switch between not connected, 10k, 20k
and 40k ohm values. This more closely models the acutal aic3204 part.
These pin settings are documented in TI's SLAA557 pages 135 and 136
(http://www.ti.com/lit/ml/slaa557/slaa557.pdf).
Signed-off-by: Jeremy McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The TLV320AIC32x4 series supports 96ksps rates in hardware. This patch
adds the necessary PLL divider values and clock settings to the table to
make 96ksps work.
Signed-off-by: Jeremy McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
To prepare for abstracting adding SPI support, the I2C pieces needs to
be in its own moudle. This patch moves common probe code into aic32x4_probe
and common removal code into aic32x4_remove. It also creates a static
regmap config structure to be copied in the I2C specific driver.
Signed-off-by: Jeremy McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
The codec's probe function is named aic32x4_probe. This is going to
conflict with later work to implement SPI support and separate out I2S
into its own file. In line with other drivers in the tree, this function
is renamed to aic32x4_codec_probe instead.
Signed-off-by: Jeremy McDermond <nh6z@nh6z.net>
Signed-off-by: Mark Brown <broonie@kernel.org>
i2c_driver does not need to set an owner because i2c_register_driver()
will set it.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
All drivers have the same line at the end of the set_bias_level callback to
update the bias_level state. Move this update into
snd_soc_dapm_force_bias_level() and remove them from the drivers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Set the CODEC driver's suspend_bias_off flag rather than manually going to
SND_SOC_BIAS_OFF in suspend and SND_SOC_BIAS_STANDBY in resume. This makes
the code a bit shorter and cleaner.
Since the ASoC core now takes care of setting the bias level to
SND_SOC_BIAS_OFF when removing the CODEC there is no need to do it manually
anymore either.
The manual transition to SND_SOC_BIAS_STANDBY at the end of CODEC probe()
can also be removed as the core will automatically do this after the CODEC
has been probed.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Fixed Coding style issues of lines over 80 characters.
Signed-off-by: Shahina Shaik <sharab.shaik@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Fixed a brace coding style issue in the tlv320aic32x4.c
Signed-off-by: Shahina Shaik <sharab.shaik@gmail.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
For some CODEC drivers like who act as the MFDs children are ignored
by this patch.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
Rearrange clock tree shutdown to disable them in the reversed order of
startup. First disable all dividers, then PLL followed by master clock.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
Support regulators to power up the codec. This patch also enables the
AVDD LDO if no AV regulator was found.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
Add support for a master clock passed through DT. The master clock of
the codec is only active when the codec is in use.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
