Commit Graph

853 Commits

Author SHA1 Message Date
Dan Carpenter
a5ea8e9995 pinctrl: sh-pfc: Unlock on error in sh_pfc_func_set_mux()
We need to unlock and enable IRQs before we return on this error path.

Fixes: 8a0cc47ccc ("pinctrl: sh-pfc: Rollback to mux if required when the gpio is freed")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/20190827093927.GB8443@mwanda
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2019-09-12 12:59:43 +01:00
Linus Walleij
df62267dde pinctrl: sh-pfc: Include the right header
This is a GPIO driver, use the appropriate header
<linux/gpio/driver.h> rather than the legacy <linux/gpio.h>
header.

Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-23 09:08:10 +02:00
Yoshihiro Shimoda
8a0cc47ccc pinctrl: sh-pfc: Rollback to mux if required when the gpio is freed
Some drivers require switching between function and gpio at run-time.
Allow to roll back from gpio to mux when the gpio is freed.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-23 09:08:10 +02:00
Yoshihiro Shimoda
b13431ed6e pinctrl: sh-pfc: Remove incomplete flag "cfg->type"
The old commit c58d9c1b26 ("sh-pfc: Implement generic pinconf
support") broke the cfg->type flag to PINMUX_TYPE_FUNCTION because
sh_pfc_pinconf_set() didn't call sh_pfc_reconfig_pin().
Now if we fix the cfg->type condition, it gets worse because:
 - Some drivers might be deferred so that .set_mux() will be called
   multiple times.
 - In such the case, the sh-pfc driver returns -EBUSY even if
   the group is the same, and then that driver fails to probe.

Since the pinctrl subsystem already has such conditions according
to @set_mux and @gpio_request_enable, this patch just remove
the incomplete flag from sh-pfc/pinctrl.c.

Fixes: c58d9c1b26 ("sh-pfc: Implement generic pinconf support")
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-12 15:55:26 +02:00
Yoshihiro Shimoda
1d4ba593d0 pinctrl: sh-pfc: Add new flags into struct sh_pfc_pin_config
To clean/modify the code up later, this patch just adds new flags
"mux_set" and "gpio_enabled" into the struct sh_pfc_pin_config.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-08-12 15:55:15 +02:00
Geert Uytterhoeven
6da53cfa0f pinctrl: sh-pfc: Use dev_notice_once() instead of open-coding
At the time of commit 9a643c9a11 ("sh-pfc: Convert message
printing from pr_* to dev_*"), the dev_*_once() variants didn't exist
yet, so the once behavior was open-coded.

Since commit e135303bd5 ("device: Add dev_<level>_once variants")
they do, so "revert" to the good practice of using a helper.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-08-08 10:18:57 +02:00
Linus Torvalds
43c95d3694 This is the bulk of pin control changes for the v5.3 kernel
cycle:
 
 Core changes:
 
 - Device links can optionally be added between a pin control
   producer and its consumers. This will affect how the system
   power management is handled: a pin controller will not suspend
   before all of its consumers have been suspended. This was
   necessary for the ST Microelectronics STMFX expander and
   need to be tested on other systems as well: it makes sense
   to make this default in the long run. Right now it is
   opt-in per driver.
 
 - Drive strength can be specified in microamps. With decreases
   in silicon technology, milliamps isn't granular enough, let's
   make it possible to select drive strengths in microamps. Right
   now the Meson (AMlogic) driver needs this.
 
 New drivers:
 
 - New subdriver for the Tegra 194 SoC.
 
 - New subdriver for the Qualcomm SDM845.
 
 - New subdriver for the Qualcomm SM8150.
 
 - New subdriver for the Freescale i.MX8MN (Freescale is now a
   product line of NXP).
 
 - New subdriver for Marvell MV98DX1135.
 
 Driver improvements:
 
 - The Bitmain BM1880 driver now supports pin config in
   addition to muxing.
 
 - The Qualcomm drivers can now reserve some GPIOs as taken
   aside and not usable for users. This is used in ACPI systems
   to take out some GPIO lines used by the BIOS so that
   noone else (neither kernel nor userspace) will play with them
   by mistake and crash the machine.
 
 - A slew of refurbishing around the Aspeed drivers (board
   management controllers for servers) in preparation for the
   new Aspeed AST2600 SoC.
 
 - A slew of improvements over the SH PFC drivers as usual.
 
 - Misc cleanups and fixes.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEElDRnuGcz/wPCXQWMQRCzN7AZXXMFAl0oTPcACgkQQRCzN7AZ
 XXNTsw//aNPfkJS8gRszv58G56lyuO8h6Cq4m5eDpzhlpjx5qjELgi9h2UNGINqD
 7CWxo35ufbKe0fDIcqpXmtuDMtSu6MuKT3SMepuw9uf9wxyndK4RIuyb0lpAJrx2
 +NMPxzS+ARlrMmcfvXPRyPWHqAkXsQk6zcCgiuNCPtROkOZgs1YZ3+pemZw2/FMq
 gSLTO/95p0TPWr6YAlpByqfsA1A/onEm9HOiU2INV7DrAfUj7mnkuC1nZ4IJDFcv
 Gn6qQVQPah+MBzkwt4WXy5kDRozCIbg7x+FQBw3KAO23TrLDTFuNsYIWGFcP2CN2
 eT8iSP3cWrXNUuEgcPD59aO07rhFooT+QBQFt2ih1dJCV1u/795wb57nxSh1YDcO
 M2tG+AW2EZky65FXwhLW2rq3LvmTM4kiEz3mA/DrcOAKvvQllK+6FKEhNy0StstP
 yvvlqoXdgH3sfOnWTAyHr35qA/pMuGEXSryWTJPqpflCvZ3wxNk+IV5nyPAtfaFz
 CK7U0Ya7NaEp/5ZlpE720apJ4uSqmRrLwk5Y1eKQvT46mGOk3rC9ZPIMXc8mB10/
 mJ9mTubi1t4uIPnBl/T1T7f8QhNtr9hOY6wjLf1LoMeJ1XVNBqA+2uydOlBJ1iop
 RQ7y/Jl1SZ/gBzKCmvjPHT2+0Oui9oXGd9bQi0xQKO5Lus/nAIg=
 =Wdw1
 -----END PGP SIGNATURE-----

Merge tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.3 kernel cycle:

  Core changes:

   - Device links can optionally be added between a pin control producer
     and its consumers. This will affect how the system power management
     is handled: a pin controller will not suspend before all of its
     consumers have been suspended.

     This was necessary for the ST Microelectronics STMFX expander and
     need to be tested on other systems as well: it makes sense to make
     this default in the long run.

     Right now it is opt-in per driver.

   - Drive strength can be specified in microamps. With decreases in
     silicon technology, milliamps isn't granular enough, let's make it
     possible to select drive strengths in microamps.

     Right now the Meson (AMlogic) driver needs this.

  New drivers:

   - New subdriver for the Tegra 194 SoC.

   - New subdriver for the Qualcomm SDM845.

   - New subdriver for the Qualcomm SM8150.

   - New subdriver for the Freescale i.MX8MN (Freescale is now a product
     line of NXP).

   - New subdriver for Marvell MV98DX1135.

  Driver improvements:

   - The Bitmain BM1880 driver now supports pin config in addition to
     muxing.

   - The Qualcomm drivers can now reserve some GPIOs as taken aside and
     not usable for users. This is used in ACPI systems to take out some
     GPIO lines used by the BIOS so that noone else (neither kernel nor
     userspace) will play with them by mistake and crash the machine.

   - A slew of refurbishing around the Aspeed drivers (board management
     controllers for servers) in preparation for the new Aspeed AST2600
     SoC.

   - A slew of improvements over the SH PFC drivers as usual.

   - Misc cleanups and fixes"

* tag 'pinctrl-v5.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (106 commits)
  pinctrl: aspeed: Strip moved macros and structs from private header
  pinctrl: aspeed: Fix missed include
  pinctrl: baytrail: Use GENMASK() consistently
  pinctrl: baytrail: Re-use data structures from pinctrl-intel.h
  pinctrl: baytrail: Use defined macro instead of magic in byt_get_gpio_mux()
  pinctrl: qcom: Add SM8150 pinctrl driver
  dt-bindings: pinctrl: qcom: Add SM8150 pinctrl binding
  dt-bindings: pinctrl: qcom: Document missing gpio nodes
  pinctrl: aspeed: Add implementation-related documentation
  pinctrl: aspeed: Split out pinmux from general pinctrl
  pinctrl: aspeed: Clarify comment about strapping W1C
  pinctrl: aspeed: Correct comment that is no longer true
  MAINTAINERS: Add entry for ASPEED pinctrl drivers
  dt-bindings: pinctrl: aspeed: Convert AST2500 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Convert AST2400 bindings to json-schema
  dt-bindings: pinctrl: aspeed: Split bindings document in two
  pinctrl: qcom: Add irq_enable callback for msm gpio
  pinctrl: madera: Fixup SPDX headers
  pinctrl: qcom: sdm845: Fix CONFIG preprocessor guard
  pinctrl: tegra: Add bitmask support for parked bits
  ...
2019-07-13 15:02:27 -07:00
Geert Uytterhoeven
992968d786 pinctrl: sh-pfc: Remove obsolete SH_PFC_PIN_NAMED*() macros
Now all Renesas pin control drivers have been converted to use the new
non-GPIO helper macros, SH_PFC_PIN_NAMED() and SH_PFC_PIN_NAMED_CFG()
are no longer used.  Remove them.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:25 +02:00
Geert Uytterhoeven
2549155932 pinctrl: sh-pfc: sh73a0: Use new macros for non-GPIO pins
Update the SH-Mobile AG5 pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the SH-Mobile AG5 SoC (in 34x34 BGA package) by
symbolic enum values, referring to signal names.

Note that the user-visible names of these pins are still based on pin
numbers instead of signal names, to preserve DT backwards compatibility.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:22 +02:00
Geert Uytterhoeven
7ad549ffcb pinctrl: sh-pfc: r8a77990: Use new macros for non-GPIO pins
Update the R-Car E3 pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the R-Car E3 SoC (in 25x25 FCBGA package) by
symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:20 +02:00
Geert Uytterhoeven
5da89cedce pinctrl: sh-pfc: r8a77965: Use new macros for non-GPIO pins
Update the R-Car M3-N pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the R-Car M3-N SiP (in 39x39 BGA package) by
symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:17 +02:00
Geert Uytterhoeven
168e18fd6c pinctrl: sh-pfc: r8a7796: Use new macros for non-GPIO pins
Update the R-Car M3-W pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the R-Car M3-W SiP (in 39x39 BGA package) by
symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:15 +02:00
Geert Uytterhoeven
42ee6c3395 pinctrl: sh-pfc: r8a7795: Use new macros for non-GPIO pins
Update the R-Car H3 ES2.0 and later pin control driver to use the new
macros for describing pins without GPIO functionality.  This replaces
the use of physical pin numbers on the R-Car H3 ES2.0 SiP (in 39x39
BGA package) by symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:13 +02:00
Geert Uytterhoeven
4f062bcb58 pinctrl: sh-pfc: r8a7795-es1: Use new macros for non-GPIO pins
Update the R-Car H3 ES1.x pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the R-Car H3 ES1.x SiP (in 39x39 BGA package) by
symbolic enum values, referring to signal names.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:10 +02:00
Geert Uytterhoeven
2404187c84 pinctrl: sh-pfc: r8a7790: Use new macros for non-GPIO pins
Update the R-Car H2 pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the R-Car H2 SoC (in 31x31 FCBGA package) by
symbolic enum values, referring to signal names.

Note that the user-visible names of these pins are still based on pin
numbers instead of signal names, to preserve DT backwards compatibility.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:08 +02:00
Geert Uytterhoeven
8eba07d3d9 pinctrl: sh-pfc: r8a7778: Use new macros for non-GPIO pins
Update the R-Car M1A pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the R-Car M1A SoC (in 25x25 FCBGA package) by
symbolic enum values, referring to signal names.

Note that the user-visible names of these pins are still based on pin
numbers instead of signal names, to preserve DT backwards compatibility.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:06 +02:00
Geert Uytterhoeven
587a9b5dad pinctrl: sh-pfc: emev2: Use new macros for non-GPIO pins
Update the EMMA Mobile EV2 pin control driver to use the new macros for
describing pins without GPIO functionality.  This replaces the use of
physical pin numbers on the EMMA Mobile EV2 SoC (in 23x23 BGA package)
by symbolic enum values, referring to signal names.

Note that the user-visible names of these pins are still based on pin
numbers instead of signal names, to preserve DT backwards compatibility.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:04 +02:00
Geert Uytterhoeven
4818f44898 pinctrl: sh-pfc: Add new non-GPIO helper macros
Add new macros for describing pins without GPIO functionality:
  - NOGP_ALL() expands to a list of PIN_id values, to be used for
    generating symbolic enum values,
  - PINMUX_NOGP_ALL() expands to a list of sh_pfc_pin entries, to
    list all pins and their capabilities.
Both macros depend on an SoC-specific CPU_ALL_NOGP() macro, to be
provided by each individual SoC pin control driver.

The new macros offer two advantages over the existing SH_PFC_PIN_NAMED()
and SH_PFC_PIN_NAMED_CFG() macros:
  1. They do not rely on PIN_NUMBER() macros and physical pin numbering,
     hence do not suffer from pin numbering confusion among different
     SoC/SiP packages.
  2. They are similar in spirit to the existing scheme for handling pins
     with GPIO functionality.

Note that internal to the driver, non-GPIO pins use a sequential
numbering scheme which starts after the highest GPIO pin number in use.
This value is calculated automatically, using two new helper macros, for
systems with either 32-port bank (GP port style) or linear (PORT style)
pin space.  Sample expansion:

    GP_LAST = sizeof(union {
	char dummy[0] __attribute__((deprecated, deprecated));
	char GP_0_0[(0 * 32) + 0] __attribute__((deprecated, deprecated));
	char GP_0_1[(0 * 32) + 1] __attribute__((deprecated, deprecated));
	...
	char GP_7_3[(7 * 32) + 3] __attribute__((deprecated, deprecated));
    })

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-06-04 11:19:00 +02:00
Masahiro Yamada
8e82fe2ab6 treewide: fix typos of SPDX-License-Identifier
Prior to the adoption of SPDX, it was difficult for tools to determine
the correct license due to incomplete or badly formatted license text.
The SPDX solves this issue, assuming people can correctly spell
"SPDX-License-Identifier" although this assumption is broken in some
places.

Since scripts/spdxcheck.py parses only lines that exactly matches to
the correct tag, it cannot (should not) detect this kind of error.

If the correct tag is missing, scripts/checkpatch.pl warns like this:

 WARNING: Missing or malformed SPDX-License-Identifier tag in line *

So, people should notice it before the patch submission, but in reality
broken tags sometimes slip in. The checkpatch warning is not useful for
checking the committed files globally since large number of files still
have no SPDX tag.

Also, I am not sure about the legal effect when the SPDX tag is broken.

Anyway, these typos are absolutely worth fixing. It is pretty easy to
find suspicious lines by grep.

  $ git grep --not -e SPDX-License-Identifier --and -e SPDX- -- \
    :^LICENSES :^scripts/spdxcheck.py :^*/license-rules.rst
  arch/arm/kernel/bugs.c:// SPDX-Identifier: GPL-2.0
  drivers/phy/st/phy-stm32-usbphyc.c:// SPDX-Licence-Identifier: GPL-2.0
  drivers/pinctrl/sh-pfc/pfc-r8a77980.c:// SPDX-Lincense-Identifier: GPL 2.0
  lib/test_stackinit.c:// SPDX-Licenses: GPLv2
  sound/soc/codecs/max9759.c:// SPDX-Licence-Identifier: GPL-2.0

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-01 18:29:58 +02:00
Geert Uytterhoeven
dd1f760bff pinctrl: sh-pfc: r8a7778: Use common PORT_GP_CFG_27() macro
Get rid of the custom PORT_GP_PUP_27() macro by using the common
PORT_GP_CFG_27() macro instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
fbc5108d93 pinctrl: sh-pfc: Add PORT_GP_27 helper macro
This follows the style of the existing PORT_GP_X macros, and will be
used by a follow-up patch for the r8a7778 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
be1c072d66 pinctrl: sh-pfc: r8a77965: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car M3-N SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
32ba9f222e pinctrl: sh-pfc: r8a7796: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car M3-W and RZ/G2M SoCs.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
9141d4558f pinctrl: sh-pfc: r8a7795: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on revisions ES2.x and later of the R-Car H3 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
0cbdf1b876 pinctrl: sh-pfc: r8a7795-es1: Add TPU pins, groups and functions
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on revision ES1.x of the R-Car H3 SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
e7ad751628 pinctrl: sh-pfc: r8a77970: Remove MMC_{CD,WP}
Hardware Manual Errata for rev. 1.50 of March 26, 2019 removed the bit
definitions for MMC_CD and MMC_WP in the documentation for the IPSR6 and
IPSR7 registers, as these pin functionalities do not exist on R-Car
V3M.

Remove the definitions, and the corrresponding pins and groups.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
4d1816cd67 pinctrl: sh-pfc: Move PIN_NONE to shared header file
Several drivers have identical definitions for PIN_NONE.
Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h,
and convert all drivers over to use it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
f1074e7281 pinctrl: sh-pfc: Add SH_PFC_PIN_CFG_PULL_UP_DOWN shorthand
It is very common for a pin to support both pull-up and pull-down
functionality.  Hence add a shorthand SH_PFC_PIN_CFG_PULL_UP_DOWN.
This not only reduces typing, but also avoids the need for several line
breaks, and makes many overly long lines shorter, improving
readability.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
bd79c92039 pinctrl: sh-pfc: Rename 2-parameter CPU_ALL_PORT() variant
There are two variants of the CPU_ALL_PORT() macro in use:
  1. A three-parameter variant, to be provided for SoCs with a linear
     GPIO pin space ("PORT style"),
  2. A two-parameter variant, to be provided for SoCs with 32-port GPIO
     banks ("GP port style").

Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and
to increase naming consistency.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
542ffc9e02 pinctrl: sh-pfc: Validate pin tables at runtime
Extend the run-time debug code with checks to ensure there are no
conflicting pin names, numbers, or enumeration values.

This helps catching bugs early.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
3dd5fd79f0 pinctrl: sh-pfc: Add check for empty pinmux groups/functions
The pinmux groups and functions arrays may contain two parts, to ease
supporting SoCs that expose pin subsets of other related SoCs.  Both
parts need to be declared with explicit sizes, which thus need to be
updated when adding support for more groups and functions.

If a size is too small, the compiler will detect this at build time
("excess elements in array initializer").
If a size is too large, this may go undetected (for pin groups), lead to
pin controller registration failures (for pin functions: "pinmux ops has
no name for functionN"), or crash the optional run-time debug code (for
pin groups).

Extend the run-time debug code with checks to detect this, to help
catching bugs early.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
80cde64f68 pinctrl: sh-pfc: Mark run-time debug code __init
All run-time debug code is called from sh_pfc_init(), which is __init.

Fixes: 6161b39a14 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Geert Uytterhoeven
5f304f8c87 pinctrl: sh-pfc: Correct printk level of group reference warning
Improve wording while at it.

Fixes: 6161b39a14 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-05-21 11:07:29 +02:00
Takeshi Kihara
0a042b355e pinctrl: sh-pfc: r8a77965: Add I2C{0,3,5} pins, groups and functions
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.

[takeshi.kihara.df: add blank lines after function declarations]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: use standard macros PINMUX_IPSR_PHYS and PINMUX_IPSR_PHYS_MSEL]
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-04 12:02:50 +02:00
Ulrich Hecht
f05603fa6a pinctrl: sh-pfc: r8a7796: Remove placeholder I2C pin data
Pin data for I2C controllers 0, 3 and 5 is properly defined already.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-04 12:02:07 +02:00
Geert Uytterhoeven
baaa2effc6 pinctrl: sh-pfc: r8a77970: Fix spacing
Replace "F_(0,0)" by "F_(0, 0)".

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-04 12:01:18 +02:00
Takeshi Kihara
e551122cdb pinctrl: sh-pfc: rcar-gen3: Rename SEL_NDFC to SEL_NDF
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of Feb
12, 2019, the sel_ndfc MOD_SEL register bit is renamed to sel_ndf.

Update the pin control drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car E3]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:02:58 +02:00
Takeshi Kihara
a040f3dec8 pinctrl: sh-pfc: rcar-gen3: Rename SEL_ADG_{A,B,C} to SEL_ADG{A,B,C}
According to the R-Car Gen3 Hardware Manual Errata for Rev 0.80 of Dec
22, 2017, and the Errata for Rev 1.50 of Dec 25, 2018, MOD_SEL0 register
bits 3, 4, 17, and 18 are renamed from SEL_ADG_{A,B,C} to
SEL_ADG{A,B,C}.  Update the pin control drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:02:49 +02:00
Takeshi Kihara
624a7a12cc pinctrl: sh-pfc: rcar-gen3: Rename RTS{0,1,3,4}# pin function definitions
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50 of
Feb 12, 2019, the RTS{0,1,3,4}_#/TANS pin names defined in the GPSR and
IPSR registers are renamed to RTS{0,1,3,4}_#.
This patch updates the pin control drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car H3 ES1.x, V3M, V3H, and D3]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:02:40 +02:00
Takeshi Kihara
662dc924a0 pinctrl: sh-pfc: rcar-gen3: Remove CC5_OSCOUT pin
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
Jun 4, 2018, the CC5_OSCOUT pin is removed.  Update the pin control
drivers to reflect this.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Update R-Car V3M, V3H]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:02:22 +02:00
Takeshi Kihara
5671f8e027 pinctrl: sh-pfc: rcar-gen3: Remove HDMI CEC pins, groups, and functions
The HDMI CEC function is not supported by the R-Car Gen3 Hardware Manual
Rev 1.00. Therefore, delete the corresponding pin groups and functions,
and rename the HDMI[01]_CEC definitions to match their GPIO
functionality.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Squashed several commits]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:01:51 +02:00
Takeshi Kihara
e87882eb9b pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit30 when using SSI_SCK2 and SSI_WS2
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug
24, 2018, there is no need to configure MOD_SEL1 bit30 when the
SSI_SCK2_{A,B} or SSI_WS2_{A,B} pin functions are selected.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Remove now unused definitions, mark MOD_SEL1 bit30 reserved]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:01:36 +02:00
Takeshi Kihara
e167d723e1 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL1 bit31 when using SIM0_D
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of
Aug 24, 2018, there is no need to configure MOD_SEL1 bit31 when the
SIM0_D_{A,B} pin function is selected.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[geert: Remove now unused definitions, mark MOD_SEL1 bit31 reserved]
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:01:26 +02:00
Takeshi Kihara
943ff71281 pinctrl: sh-pfc: r8a77990: Fix MOD_SEL0 bit16 when using NFALE and NFRB_N
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.00 of Aug
24, 2018, the MOD_SEL0 bit16 must be set to 0 when the NFALE_A and
NFRB_N_A pin functions are selected.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-04-02 10:01:18 +02:00
Geert Uytterhoeven
360328c7dc pinctrl: sh-pfc: Improve PINMUX_IPSR_PHYS() documentation
- The IPSR field is meant for documentation only,
  - The function name refers to the pin function, not to the IPSR
    field.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
2019-04-02 09:57:50 +02:00
Geert Uytterhoeven
fa4d36712f pinctrl: sh-pfc: Validate enum IDs for regs with variable-width fields
Add a run-time check to the PINMUX_CFG_REG_VAR() macro, to ensure the
number of provided enum IDs is correct.  This cannot be done at build
time, as the number of values depends on the variable-width fields in
the config register.

This helps catching bugs early.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02 09:58:07 +02:00
Geert Uytterhoeven
c481c81784 pinctrl: sh-pfc: Validate enum IDs for regs with fixed-width fields
Add build-time checks to the PINMUX_CFG_REG() and PINMUX_DATA_REG()
macros, to ensure the number of provided enum IDs is correct.

This helps catching bugs early.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02 09:58:04 +02:00
Geert Uytterhoeven
19b593a1cf pinctrl: sh-pfc: Absorb enum IDs in PINMUX_DATA_REG() macro
Currently the PINMUX_DATA_REG() macro must be followed by initialization
data, specifying all enum IDs.  Hence the macro itself does not know
anything about the enum IDs, preventing the macro from performing any
validation on it.

Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence the enum IDs are wrapped using the GROUP()
macro.

No functional changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02 09:58:01 +02:00
Geert Uytterhoeven
69f7be1c63 pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG_VAR() macro
Currently the PINMUX_CFG_REG_VAR() macro must be followed by
initialization data, specifying all enum IDs.  Hence the macro itself
does not know anything about the enum IDs, preventing the macro from
performing any validation on it.

Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence both the register field widths and the enum
IDs are wrapped using the GROUP() macro.

No functional changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02 09:57:58 +02:00
Geert Uytterhoeven
efca8da0c5 pinctrl: sh-pfc: Absorb enum IDs in PINMUX_CFG_REG() macro
Currently the PINMUX_CFG_REG() macro must be followed by initialization
data, specifying all enum IDs.  Hence the macro itself does not know
anything about the enum IDs, preventing the macro from performing any
validation on it.

Make the macro accept the enum IDs as a parameter, and update all users.
Note that array data enclosed by curly braces cannot be passed to a
macro as a parameter, hence the enum IDs are wrapped using a new macro
GROUPS().

No functional changes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-04-02 09:57:55 +02:00