clk_out_1, clk_out_2, and clk_out_3 are part of Tegra PMC block but were
previously erroneously provided by the clock and reset controller.
clk_out_1 is dedicated for audio mclk on Tegra30 through Tegra210.
This patch updates device tree sound node to use clk_out_1 from the PMC
provider as mclk and uses assigned-clock properties to specify clock
parents for clk_out_1 and extern1.
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the stmpe-adc DT node as found on Toradex T30 modules
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Support the V1.1 hardware revisions with the following change:
Changed power rail for MMC1 interface to a 3.3V/1.8V switchable rail in
order to be able to run UHS SD cards in ultra high speed 1.8V mode.
[ 207.502011] mmc2: host does not support reading read-only switch,
assuming write-enable
[ 207.517011] mmc2: new ultra high speed SDR104 SDHC card at address
aaaa
[ 207.534190] mmcblk2: mmc2:aaaa SE32G 29.7 GiB
[ 207.545096] mmcblk2: p1
root@apalis-t30:~# cat /sys/kernel/debug/mmc2/ios
clock: 208000000 Hz
actual clock: 204000000 Hz
vdd: 21 (3.3 ~ 3.4 V)
bus mode: 2 (push-pull)
chip select: 0 (don't care)
power mode: 2 (on)
bus width: 2 (4 bits)
timing spec: 6 (sd uhs SDR104)
signal voltage: 1 (1.80 V)
driver type: 0 (driver type B)
root@apalis-t30:~# hdparm -t /dev/mmcblk2
/dev/mmcblk2:
Timing buffered disk reads: 256 MB in 3.02 seconds = 84.71 MB/sec
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
