Commit Graph

6 Commits

Author SHA1 Message Date
Roy Pledge
06cc59386c soc: fsl: qbman: Add 64 bit DMA addressing requirement to QBMan
The QBMan block is memory mapped on SoCs above a 32 bit (4 Gigabyte)
boundary so enabling 64 bit DMA addressing is needed for QBMan to
be usuable.

Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
2018-10-05 14:01:46 -05:00
Li Yang
4625210899 soc: fsl: cleanup Kconfig menu
Put NXP/Freescale QorIQ SoC drivers under a menu and make the item
naming more aligned.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
2018-07-24 16:19:16 -05:00
Madalin Bucur
e868adf21c soc/fsl/qbman: Enable FSL_LAYERSCAPE config on ARM
Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
[Stuart: changed to use ARCH_LAYERSCAPE]
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Li Yang <leoyang.li@nxp.com>
2017-09-22 13:33:07 -05:00
Claudiu Manoil
de77562339 soc/qman: Add self-test for QMan driver
Add self tests for the DPAA 1.x Queue Manager driver. The tests
ensure that the driver can properly enqueue and dequeue to/from
frame queues using the QMan portal infrastructure.

Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-09-25 02:39:00 -05:00
Claudiu Manoil
97e0d385b1 soc/bman: Add self-test for BMan driver
Add a self test for the DPAA 1.x Buffer Manager driver. This
test ensures that the driver can properly acquire and release
buffers using the BMan portal infrastructure.

Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-09-25 02:38:59 -05:00
Claudiu Manoil
1f9c0a7727 soc/fsl: Introduce DPAA 1.x BMan device driver
This driver enables the Freescale DPAA 1.x Buffer Manager block.
BMan is a hardware accelerator that manages buffer pools.  It allows
CPUs and other accelerators connected to the SoC datapath to acquire
and release buffers during data processing.

Signed-off-by: Roy Pledge <roy.pledge@nxp.com>
Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Signed-off-by: Scott Wood <oss@buserror.net>
2016-09-25 02:38:58 -05:00