Commit Graph

7 Commits

Author SHA1 Message Date
Hoan Nguyen An
bc7133cef8 clk: renesas: r8a77965: Add FDP clock
This patch adds FDP1-0 clock to the R8A77965 SoC.

Signed-off-by: Hoan Nguyen An <na-hoan@jinso.co.jp>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-28 11:06:11 +02:00
Takeshi Kihara
e59bb7be47 clk: renesas: r8a77965: Add SATA clock
This patch adds SATA clock to the R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[wsa: rebased to upstream base]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-08-27 17:00:19 +02:00
Geert Uytterhoeven
979a2298a5 clk: renesas: r8a77965: Add OSC EXTAL predivider configuration
R-Car Gen3 Hardware Manual Rev.0.52 documents the relation between the
MD13 and MD14 mode pins, and the OSC EXTAL predivider, as used by the
OSC and RINT RCLK clocks.  Hence augment the configuration structure
with all documented predivider values.

According to R-Car Gen3 Hardware Manual Rev.1.00, R-Car M3-N does not
have the CPG_RCKCR register.  Change the OSC and RINT clock definitions
to use the OSC EXTAL predivider instead, which is supported on all R-Car
M3-N SoC revisions.

Inspired by a patch in the BSP by Takeshi Kihara
<takeshi.kihara.df@renesas.com>.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27 17:00:18 +02:00
Geert Uytterhoeven
fdb78a8c35 clk: renesas: rcar-gen3: Rename rint to .r
All other internal clock names have a period prepended.

Hence rename the internal RCLK from "rint" to ".r", and move it to the
section where all other internal clocks are defined.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-08-27 17:00:18 +02:00
Takeshi Kihara
cdc749e229 clk: renesas: r8a77965: Add MSIOF controller clocks
This patch adds MSIOF{0,1,2,3} clocks to the R8A77965 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2018-04-16 13:39:36 +02:00
Jacopo Mondi
1e04204eff clk: renesas: r8a77965: Replace DU2 clock
R-Car M3-N does not have the DU2 unit but it has DU3 instead.
Fix the module clock definition to reflect that.

Fixes: 7ce36da900 ("clk: renesas: cpg-mssr: Add support for R-Car M3-N")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-03-13 17:10:45 +01:00
Jacopo Mondi
7ce36da900 clk: renesas: cpg-mssr: Add support for R-Car M3-N
Initial support for R-Car M3-N (r8a77965), including core and module
clocks.

Based on Table 8.2d of "R-Car Series, 3rd Generation User's Manual:
Hardware (Rev. 0.80, Oct 31, 2017)".

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2018-02-26 09:13:29 +01:00