Commit Graph

12 Commits

Author SHA1 Message Date
Ulrich Hecht
878f8baa02 clk: renesas: r8a7796: Add I2C clocks
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:21 +02:00
Ulrich Hecht
28aa831949 clk: renesas: r8a7796: Add HSCIF clocks
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:21 +02:00
Ulrich Hecht
951456c37d clk: renesas: r8a7796: Add SCIF clocks
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:20 +02:00
Ulrich Hecht
cf8fe97cad clk: renesas: r8a7796: Add SYS-DMAC clocks
Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-10-17 15:56:20 +02:00
Bui Duc Phuc
5fad71f58f clk: renesas: r8a7796: Add CMT clocks
This patch adds CMT module clocks for r8a7796 SoC.

Signed-off-by: Bui Duc Phuc <bd-phuc@jinso.co.jp>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12 11:08:01 +02:00
Laurent Pinchart
5576df81d2 clk: renesas: r8a7796: Add RAVB clock
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-12 11:08:00 +02:00
Khiem Nguyen
5086b0d6ce clk: renesas: r8a7796: Add THS/TSC clock
Signed-off-by: Khiem Nguyen <khiem.nguyen.xt@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-09-05 14:16:25 +02:00
Simon Horman
0749698133 clk: renesas: r8a7796: Add SDIF clocks
This patch adds SDIF clocks for R8A7796 SoC.

Based on work by Ai Kyuse and Yoshihiro Shimoda for the r8a7795 SoC.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-23 10:30:41 +02:00
Takeshi Kihara
4e09508a89 clk: renesas: r8a7796: Add GPIO clocks
Add GPIO clocks for the R8A7796 SoC.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-19 09:38:40 +02:00
Geert Uytterhoeven
b51d527501 clk: renesas: r8a7796: Add watchdog module clock
Add the module clock for the Watchdog Timer (WDT) controller on the
Renesas R-Car M3-W (r8a7796) SoC.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09 09:53:47 +02:00
Geert Uytterhoeven
2570d4005d clk: renesas: r8a7796: Add watchdog core clocks
Add all core clocks related to the Watchdog Timer (WDT) controller on
the Renesas R-Car M3-W (r8a7796) SoC: OSC, Internal RCLK, and RCLK.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-08-09 09:53:47 +02:00
Geert Uytterhoeven
e4e2d7c388 clk: renesas: cpg-mssr: Add support for R-Car M3-W
Initial support for R-Car M3-W (r8a7796), including basic core clocks,
and SCIF2 (console) and INTC-AP (GIC) module clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
2016-06-06 11:58:35 +02:00