Commit Graph

457236 Commits

Author SHA1 Message Date
Gajanan Bhat
0948c26514 drm/i915: Generalize drain latency computation
Modify drain latency computation to use it for any plane. Same function can be
used for primary, cursor and sprite planes.

v2: Adressed review comments by Imre and Ville.
    - Moved clock round up in separate patch
    - Added WARN check for clock and pixel size
    - Simplified bit masking
    - Use cursor_base instead of reg read

v3: Changed to bitwise shorthand operator for plane_dl assignment.

Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:59 +02:00
Ville Syrjälä
e2fcdaa9c9 drm/i915: Free pending page flip events at .preclose()
If there are pending page flips when the fd gets closed those page
flips may have events associated to them. When the page flip eventually
completes it will queue the event to file_priv->event_list, but that
may be too late and file_priv->event_list has already been cleaned up.
Thus we leak a bit of kernel memory in the form of the event structure.

To avoid such problems clear out such pending events from
intel_crtc->unpin_work at ->preclose(). Any event that already made it
to file_priv->event_list will get cleaned up by the drm_release_events()
a bit later.

We can ignore the file_priv->event_space accounting since file_priv is
going away. This is already how drm core deals with pending vblank
events, which are maintained by the drm core.

What saves us from a total disaster (ie. dereferencing and alrady
freed file_priv) is the fact that the fb descruction triggers a modeset
and there we wait for pending flips.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:58 +02:00
Jesse Barnes
692ef70c01 drm/i915: clean up PPGTT checking logic
sanitize_enable_ppgtt is the function that checks all the conditions,
honoring a forced ppgtt status or doing auto-detect as necessary.  Just
make sure it returns the right value in all cases and use that in the
macros instead of the confusing intel_enable_ppgtt() function.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
[danvet: Don't reenable full ppgtt through the backdoor.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:58 +02:00
Ville Syrjälä
efd814b73c drm/i915: Polish the chv cmnlane resrt macros
Replace the semi-funky cmnlane assert/deassert macros with something a
bit more conventional. Also protect the macro arguments properly (also
for  PHY_POWERGOOD()).

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:57 +02:00
Ville Syrjälä
3dd7b97458 drm/i915: Hack to tie both common lanes together on chv
It looks like frobbing the cmnreset line on pne PHY disturbs the other
PHY on chv. The result is a black screen. On HDMI it's just a flash of
black, but DP usually falls over and can't get back up.

As a workaround set up the power domains so that both common lane
wells power up and down together. I also tried leaving the cmnreset
deasserted even the if the power well goes down but that didn't seem
acceptable to the PHY.

Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:56 +02:00
Ville Syrjälä
3c2777fd2f drm/i915: Add cherryview_update_wm()
CHV has a third pipe so we need to compute the watermarks for its
planes. Add cherryview_update_wm() to do just that.

v2: Rebase on top of Imre's cxsr changes
v3: Pass crtc to vlv_update_drain_latency()

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:56 +02:00
Gajanan Bhat
41aad816d7 drm/i915: Update DDL only for current CRTC
Instead of looping through all CRTCs, update DDL for current CRTC for which
watermark is being updated.
CHV is confirmed to have precision of 32/64 which is same as VLV.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:55 +02:00
Ville Syrjälä
1abc4dc7e2 drm/i915: Parametrize VLV_DDL registers
The VLV/CHV DDL registers are uniform, and neatly enough the register
offsets are sane so we can easily unify them to a single set of defines
and just pass the pipe as the parameter to compute the register offset.

Note that we now fill out the drain latency for pipe C on CHV which we
didn't do before. The rest of the pipe C watermarks are still untouched
but that will be remedied later by adding a proper cherryview_update_wm()
function.

v2: Add a note about CHV pipe C changes (Paulo)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:54 +02:00
Ville Syrjälä
0a56067469 drm/i915: Fill out the FWx watermark register defines
Add defines for all the watermark registers on modernish gmch platforms.

VLV has increased the number of bits available for certain watermaks so
expand the masks appropriately. Also vlv and chv have added some extra
FW registers.

Not sure what happened on chv because a new register called FW9 is now
at the offset where FW7 was on vlv, while FW7 and FW8 (another new
register) have been moved off somewhere else. Oh well, well just need
two defines for FW7 then.

v2: Fix DSPHOWM1 offset (Paulo)

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:54 +02:00
Sonika Jindal
9783de2096 drm: Resetting rotation property
Reset rotation property to 0.

v2: Resetting after disabling the plane

Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:53 +02:00
Ville Syrjälä
7ed6eeeec6 drm/i915: Add rotation property for sprites
Sprite planes support 180 degree rotation. The lower layers are now in
place, so hook in the standard rotation property to expose the feature
to the users.

v2: Moving rotation_property to mode_config

Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:53 +02:00
Sonika Jindal
2a297cce2e drm: Add rotation_property to mode_config
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:52 +02:00
Ville Syrjälä
e57465f351 drm/i915: Make intel_plane_restore() return an error
Propagate the error from intel_update_plane() up through
intel_plane_restore() to the caller. This will be used for
rollback purposes when setting properties fails.

Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:51 +02:00
Ville Syrjälä
76eebda727 drm/i915: Add 180 degree sprite rotation support
The sprite planes (in fact all display planes starting from gen4)
support 180 degree rotation. Add the relevant low level bits to the
sprite code to make use of that feature.

The upper layers are not yet plugged in.

v2: HSW handles the rotated buffer offset automagically

v3: BDW also handles the rotated buffer offset automagically

Testcase: igt/kms_rotation_crc
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:51 +02:00
Damien Lespiau
b2784e1519 drm/i915: Introduce a for_each_intel_encoder() macro
Following the established idom, let's provide a macro to iterate through
the encoders.

spatch helps, once more, for the substitution:

  @@
  iterator name list_for_each_entry;
  iterator name for_each_intel_encoder;
  struct intel_encoder * encoder;
  struct drm_device * dev;
  @@
  -list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
  +for_each_intel_encoder(dev, encoder) {
    ...
  }

I also modified a few call sites by hand where a pointer to mode_config
was directly used (to avoid overflowing 80 chars).

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Wrap paramters correctly in the macro and remove spurious
space checkpatch noticed.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:50 +02:00
Damien Lespiau
4079b8d1c3 drm/i915: Demote the DRRS messages to debug messages
While those messages are interesting, there aren't _that_ interesting.
We don't need them in the kernel logs by default.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:49 +02:00
Paulo Zanoni
7fad3594bf drm/i915: remove duplicate register defines
cat i915_reg.h | sort | uniq -d | grep define

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:49 +02:00
Damien Lespiau
ac921bdde9 drm/i915: Remove now useless comments about the translation values
We used to carry a default HDMI value in entry 9, but this entry got
removed for both HSW and BDW.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:48 +02:00
Damien Lespiau
156ae28c9f drm/i915/bdw: Remove the HDMI/DVI entry from the DP/eDP/FDI tables
We always write entries 0 to 8 from the DDI translation tables and then
entry 9 for HDMI/DVI with the help of the VBT. We then don't need the
failsafe HDMI entry in the DP/eDP/FDI tables.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:48 +02:00
Damien Lespiau
a26aa8baee drm/i915/bdw: Provide the BDW specific HDMI buffer translation table
Among the changes, the tables has only 10 entries instead of 12 on HSW
and the index the the 800mV/0dB entry has changed.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:47 +02:00
Damien Lespiau
ce4dd49e97 drm/i915: Gather the HDMI level shifter logic into one place
The knowledge about the HDMI/DVI DDI translation table was scattered
around.
  - info->hdmi_level_shift was initialized with 6, the index of the 800
    mV, 0dB translation
  - A check on the VBT value was done to ensure it wasn't overflowing
    the translation table (< 0xC)
  - The actual programming was done in intel_ddi.c

As we need to change that knowledge for Broadwell, let's gather
everything into one place.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:46 +02:00
Rodrigo Vivi
da46f936bb drm/i915: Introduce FBC False Color for debug purposes.
With this bit enabled, HW changes the color when compressing frames for
debug purposes.

ALthough the simple way to enable a single bit is over intel_reg_write,
this value is overwriten on next update_fbc so depending on the workload
it is not possible to set this bit with intel-gpu-tools. So this patch
introduces a persistent way to enable false color over debugfs.

v2: Use DEFINE_SIMPLE_ATTRIBUTE as Daniel suggested
v3: (Ville) only do false color for IVB+ since according to spec bit is
    MBZ before IVB.
v4: We don't have FBC on valleyview nor on cherryview (Ben)
v5: s/!HAS_PCH_SPLIT/!HAS_FBC (Ville)

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:46 +02:00
Daniel Vetter
7f3de8336f drm/i915: Align intel_dsi*.c files a bit
I'm not really that insisting on checkpath compliance, but ragged
function paramter alignment does get me. Please adjust your editor to
just do this for you.

Cc: Shobhit Kumar <shobhit.kumar@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:45 +02:00
Shobhit Kumar
7f0c860533 drm/i915: Add support for Video Burst Mode for MIPI DSI
v2: Updated the error log as suggested by Imre

Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:45 +02:00
Ville Syrjälä
1fb44505f6 drm/i915: Clarify CHV swing margin/deemph bits
CHV display PHY registes have two swing margin/deemph settings. Make it
clear which ones we're using.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:44 +02:00
Ville Syrjälä
625695f8c3 drm/i915: Call intel_{dp, hdmi}_prepare for chv
CHV was forgotten the intel_{dp,hdmi}_prepare() were introduced (or the
chv patches were still in flight?). Call these when enabling the ports.

Things tend to work much better when we actually write something
to the port registers :)

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:43 +02:00
Ville Syrjälä
1ae0d1377f drm/i915: Split chv_update_pll() apart
Split chv_update_pll() into two parts ala:
 commit bdd4b6a655
 Author: Daniel Vetter <daniel.vetter@ffwll.ch>
 Date:   Thu Apr 24 23:55:11 2014 +0200

    drm/i915: Extract vlv_prepare_pll

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:43 +02:00
Ville Syrjälä
d17ec4ced6 drm/i915: Leave DPLL ref clocks on
We enable the DPLL refclock already when bringing up the cmnlane power
well, so also leave it on when otherwise disabling the DPLL.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:42 +02:00
Ville Syrjälä
d49a340d6e drm/i915: Disable cdclk changes for chv until Punit is ready
Punit seems a bit WIP still. Disable cdclk changes until we have
hardware where it works.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:41 +02:00
Ville Syrjälä
383c5a6a46 drm/i915: Add cdclk change support for chv
Looks like the Punit is supposed to support the 400MHz cdclk directly on
chv, so we don't need the vlv tricks.

FIXME: Punit doesn't seem ready for this yet on current hw

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:41 +02:00
Paulo Zanoni
06ffc7789e d rm/i915: freeze display before the interrupts and GT
Since we started using intel_runtime_pm_disable_interrupts() at normal
(non-runtime) suspend/resume, we had to remove a WARN from
ironlake_disable_display_irq to avoid a case where we were doing the
correct thing and the WARN was not really needed. The problem is that
the WARN was useful in other cases, and its removal can hide some bugs
that we would catch automatically.

To be able to add back the WARN, we have to call intel_crtc_control()
before interrupts are disabled, which is what this patch currently
does.

Also notice that Ville's patch from the Watermarks series "drm/i915:
Leave interrupts enabled while disabling crtcs during suspend" also
did a change that's equivalent to the one we're doing on this patch,
with the exception that its original patch, when applied to the
current tree, procduces a WARN.

Related commits:

commit daa390e5ee45cc051d6bf37b296901f2f92b002d
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
    drm/i915: don't warn if IRQs are disabled when shutting down display IRQs

commit e11aa36230
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
    drm/i915: use runtime irq suspend/resume in freeze/thaw

Note that the function part of this patch has already been done in

commit 0e32b39cee
Author: Dave Airlie <airlied@redhat.com>
Date:   Fri May 2 14:02:48 2014 +1000

    drm/i915: add DP 1.2 MST support (v0.7)

with the fixup

commit 09b64267c1
Author: Dave Airlie <airlied@redhat.com>
Date:   Wed Jul 23 14:25:24 2014 +1000

    drm/i915: don't suspend gt until after we disable irqs and display (v2)

so all that's left from Paulo's patch is reinstating the WARNING.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Explain conflict resolution with Dave's DP MST patches with a
note in the commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:40 +02:00
Daniel Vetter
3d51278af9 drm/i915: Make ddi_clock_gate() HSW/BDW specific
Turns out we were again way too naive and optimistic, of course things
will change.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:39 +02:00
Damien Lespiau
ad13d6048f drm/i915: Split the CDCLK retrieval per-platform
This is only going to get worse, so split it now to avoid adding more
cases to the if/else ladder.

Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:39 +02:00
Damien Lespiau
d664c0cece drm/i915: Make intel_ddi_calculate_wrpll() HSW/BDW specific
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:38 +02:00
Damien Lespiau
0220ab6e00 drm/i915: Split the BDW/HSW specific shared pll selection
We'll need a different algorithm to select the shared DPLL.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:37 +02:00
Damien Lespiau
bf9584bd0e drm/i915: Fix stale comment for intel_ddi_pll_select()
Since the run-time PM on DPMS series, this function has an outdated
comment. Refresh it a bit.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:37 +02:00
Damien Lespiau
ea155f32ce drm/i915: Restrict hsw_dp_set_ddi_pll_sel() to HSW/BDW
Future platform will use config->ddi_pll_sel in a different way.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:36 +02:00
Damien Lespiau
143b307c43 drm/i915: Extract the HSW/BDW shared dpll init code
So we can easily provide an alternate implementation in the future.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:35 +02:00
Damien Lespiau
7d2c81751c drm/i915: Extract the HSW DDI selection code into its own function
Future platform will slightly change that.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:35 +02:00
Damien Lespiau
74dd69280b drm/i915: Add a space to the shared DPLL debug message
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:34 +02:00
Damien Lespiau
dcfc355213 drm/i915: Specify when the PLL hw state fields are valid
Not all those fields are valid on a given platform. Make it explicit.

Unions could also be used, but were cluttering some code paths with
if/else ladders.

v2: Don't use anonymous unions (Daniel)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:33 +02:00
Ville Syrjälä
aad3d14d25 drm/i915: Add DP training pattern 3 for CHV
CHV supports DP training pattern 3. Add the required stuff.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:33 +02:00
Ville Syrjälä
a5043453aa drm/i915: Split a few long debug prints
Split some WM debug prints to multiple lines. This shouldn't hurt
grappability since the important part is at the start and the rest
is just repeated stuff for each pipe.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:32 +02:00
Rafael Barbalho
026b96e293 drm/i915: Fix read back of plane stride register
According to the specifications bit 6 is actually valid in the stride register.

Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Rafael Barbalho <rafael.barbalho@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:32 +02:00
Ville Syrjälä
2ce147f36d drm/i915: Add chv port D TX wells
Add the TX wells for port D. The Punit subsystem numbers are a total
guess at this time. Also I'm not sure these even exist. Certainly the
Punit in current hardware doesn't deal with these.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:31 +02:00
Ville Syrjälä
8258356537 drm/i915: Add chv port B and C TX wells
Add the TX wells for ports B and C just like on VLV.

Again Punit doesn't seem ready (or the wells don't even exist anymore)
so leave it iffed out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:30 +02:00
Ville Syrjälä
26972b0a80 drm/i915: Add per-pipe power wells for chv
CHV has a power well for each pipe. Add the code to deal with them.

The Punit in current hardware doesn't seem ready for this yet, so
leave it iffed out.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:30 +02:00
Ville Syrjälä
f07057d13c drm/i915: Add disp2d power well for chv
Not sure if it's still there since chv has per-pipe power wells.
At least with current Punit this doesn't work. Also the display
irq handling would need to be adjusted for pipe C. So leave the
code iffed out for now.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:29 +02:00
Ville Syrjälä
a74d782c74 drm/i915: Kill intel_reset_dpio()
Both VLV and CHV handle the cmnreset stuff in the power well code now,
so intel_reset_dpio() is no longer needed.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:28 +02:00
Ville Syrjälä
5d6f7ea752 drm/i915: Add chv cmnlane power wells
CHV has two display PHYs so there are also two cmnlane power wells. Add
the approriate code to power the wells up/down.

Like on VLV we do the cmnreset assert/deassert and the DPLL refclock
enabling at approriate times.

This code actually works on my bsw.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2014-08-08 17:43:28 +02:00