Add xo entry to sdhc clock node on all qcom platforms.
Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Following the Amlogic Linux kernel, it seem the only differences
between the GXL and GXM SoCs are the CPU Clusters.
This commit renames the gxl-s905d-p23x DTSI in a common file for
S905D p23x and S912 q20x boards.
Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards
dts files since the S905D and S912 SoCs shares the same pinout
and the P23x and Q20x boards are identical.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
All conflicts were simple overlapping changes except perhaps
for the Thunder driver.
That driver has a change_mtu method explicitly for sending
a message to the hardware. If that fails it returns an
error.
Normally a driver doesn't need an ndo_change_mtu method becuase those
are usually just range changes, which are now handled generically.
But since this extra operation is needed in the Thunder driver, it has
to stay.
However, if the message send fails we have to restore the original
MTU before the change because the entire call chain expects that if
an error is thrown by ndo_change_mtu then the MTU did not change.
Therefore code is added to nicvf_change_mtu to remember the original
MTU, and to restore it upon nicvf_update_hw_max_frs() failue.
Signed-off-by: David S. Miller <davem@davemloft.net>
-----BEGIN PGP SIGNATURE-----
iQEcBAABAgAGBQJYMhsfAAoJEHm+PkMAQRiGbZMH/AnSgpvWgJQGr/NsovAJsDM9
aJZPNQnjVD+6dBZLudCJOeKoZ8hd0vI/FNPxDrAJxt0L4PCX6Hxnmt+qsLAhodiU
uGOpLK7dwgE5OH3xEKzbEHJBitEZ5nmKBG1oEZNurL9kTFxyL78j7YnlMz/DpjsH
RwDfV4tD5vyVv8vcmHzo6OBWja+78Njo6+OVaMq/fw8+LqS2uq1ajsLWlkUMGo4b
3CDziy6lMLjHy5LlrWkxYvIK2ldB8o+3EDnp/KOwrQ/L9qNaBillUxwDI8qodqHV
NTUjBi51oqG06YwplJa7Qr9SVFD28SlNjVIv/PRgHm6kPfzNUvlp97WnWUn8R/8=
=SoWG
-----END PGP SIGNATURE-----
Merge tag 'v4.9-rc6' into patchwork
Linux 4.9-rc6
* tag 'v4.9-rc6': (305 commits)
Linux 4.9-rc6
ext4: sanity check the block and cluster size at mount time
fscrypto: don't use on-stack buffer for key derivation
fscrypto: don't use on-stack buffer for filename encryption
i2c: i2c-mux-pca954x: fix deselect enabling for device-tree
kvm: x86: merge kvm_arch_set_irq and kvm_arch_set_irq_inatomic
KVM: x86: fix missed SRCU usage in kvm_lapic_set_vapic_addr
KVM: async_pf: avoid recursive flushing of work items
kvm: kvmclock: let KVM_GET_CLOCK return whether the master clock is in use
KVM: Disable irq while unregistering user notifier
KVM: x86: do not go through vcpu in __get_kvmclock_ns
MAINTAINERS: Add LED subsystem co-maintainer
crypto: algif_hash - Fix NULL hash crash with shash
powerpc/mm: Fix missing update of HID register on secondary CPUs
KVM: arm64: Fix the issues when guest PMCCFILTR is configured
arm64: KVM: pmu: Fix AArch32 cycle counter access
powerpc/mm/radix: Invalidate ERAT on tlbiel for POWER9 DD1
i2c: digicolor: use clk_disable_unprepare instead of clk_unprepare
ipmi/bt-bmc: change compatible node to 'aspeed, ast2400-ibt-bmc'
Revert "drm/mediatek: set vblank_disable_allowed to true"
...
other fixes.
In order to get the thermal node that we're adjusting the compatible
string on, we have to merge in the bcm2835-dt-next branch.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCgAGBQJYL0q9AAoJELXWKTbR/J7o+wwQAKaYPlaBJPDTkPkKbvg7C2Xl
1EzOP2oDgHp7r7Ntk5u2NOJD7GVIpKL8LVYQu94pCCUMGz36kiES4kNL+h6VlxPn
dsla8GcasDFDzaXSVM7G68vH3p0WLmnQ2RVO6bD3O71twJeGuHfmLF4kmtj4ba7+
m+jP9AlG9nt3K3LKblGyv0grklTP8Kuxg4CEEwpSw5kNQUdrobItkbTmK1RE/hgm
u8mx6J4mZmTJBhZD+nRLN53YJig/ZYMvVpygxoTZb+hr9T/yb+sOJ144ajyiLDUO
tOAvPutJbNHOFQobNb8FQftLJ1awojJFOlRAF2xpjMOvesICO4YTxB6t1zsxTFI9
qJFXiX/962qpbkLDALQnoOQDuIz7Kkk8JdD/8/54XudcYUvutM/sc1WSR43T9gzu
n1MJUD169p24XzACUs1hEe/kiZ64Z4mD2BSkelxk3EfWd9/vxzIkDw/8084cm+zh
RNHcXpf2vHgIqlPcj5+Kcq8jNhi7c2nwVR1cdDnF+tcJjAuRWn4LR702mIXzdNRR
EG74X9PbNuQ+HzAW7u+1rgQGOqblTGYpviN8We6jwVQO5BICQwEGfqjVbXrByxdq
+gwR0xlSsMqae1J5Bg8X22pSAQicGiAJxsGrGHE+xZ9iJmrSyXebt604idvEvkc8
Nbkh07jgaxneG+nrU2ww
=zVOm
-----END PGP SIGNATURE-----
gpgsig -----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYM9MLAAoJEIfQlpxEBwcEMo0QAKPVSHV/0zsWBg2MDaFG0MWM
tUm9G4U3iVR/isTyLTogTQ1JrxR+lb4psgUsri/DkfvMdlDL3V+640BS/nA2M7Mj
ZclG3vTjUg9sUUelw1zbKv8Ow53y1xaSJFA5XlWL9zMTxoIq0J8B8zjxZp+nYaTe
Yo/OJKbM8NNLTw9tbE3gZhQ371iQ/nxEyu7ZIWvrWtsmgSeaZ2g0BUhiKLkUx3ta
zQPqEHA5yVveSxK/9iTxrsNndnqWEqsN+/qkTGTH0yJDqdQwd3AAjVmlVsDKLllW
eWX10KC2hoHPY438hP1zVa0Pwss2/HRSBKF/UatRf4mVqsdy8q5WMtROT/+Vn4qx
SEazhRnMAPPBI+FpnbZKFycdzvlOf4tFXQdpn7fwk1jhy2gbQFnGRFwdUeoVDrSN
AsPAhtqgSGcRvy8eLtutzOpXwkRfHlkuYOm1hxeD/7tADW17rNjGrXvqUhudcJkl
1cCAHABS7lAV/f22anx9Y+mOSL+Zp7yZ4vZ1FHFLS52XvyWbyibxYn+/goMD/Pv9
pJeYFSopCOHb4Cid94Jbs2qh5/lfdr4EOf+6Qq9ZcPDKXfkinFOC+JCRy20T+iXZ
bQvpNWKk0T8y0vg7kyFjW772od06Yd+OBNKXculdstjRTJY2G8Nd0LJ4iOCF/mFX
e39X2qPoEEQh/M1RiOZv
=GHAx
-----END PGP SIGNATURE-----
Merge tag 'bcm2835-dt-64-next-2016-11-18' into devicetree-arm64/next
This pull request brings thermal support to the BCM2837 DT, and a few
other fixes.
In order to get the thermal node that we're adjusting the compatible
string on, we have to merge in the bcm2835-dt-next branch.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
PCI PHYs are missing from the Northstar2 DT entries for the 2 PCI buses.
Add them so that PCI devices can be discovered.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Enable sdio1 in the Northstar2 SVK device tree file
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Add the mshc_2 node for supporting T-Flash.
Also add the "mshc*" aliases. dwmmc driver should be assigned to
"ctrl_id" after parsing to "mshc". If there are no aliases for mshc,
then it might be set to the wrong capabilities.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
The "arm,no-tick-in-suspend" property was introduced to note
implementations where the system counter does not quite follow the ARM
specification that it "must be implemented in an always-on power
domain".
Particularly, RK3399's counter stops ticking when we switch from the
24MHz clock to the 32KHz clock in low-power suspend, so let's mark it as
such.
Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The NVIDIA P2771 is composed of a P3310 processor module that connects
to the P2597 I/O board. It comes with a 1200x1920 MIPI DSI panel that is
connected via the P2597's display connector and has several connectors
such as HDMI, USB 3.0, PCIe and ethernet.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The P3310 processor module comes ships with a firmware that implements
PSCI 1.0. Enable and use it to bring up all CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
The NVIDIA P3310 is a processor module used in several reference designs
that features a Tegra186 SoC, 8 GiB of LPDDR4 RAM, 32 GiB eMMC and other
essentials such as ethernet, WiFi and a PMIC. It is typically connected
to an I/O board (such as the P2597) that provides the connecters needed
to hook it up to the outside world.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has a total of four SDHCI controllers that each support SD 4.2
(up to UHS-I speed), SDIO 4.1 (up to UHS-I speed), eSD 2.1, eMMC 5.1 and
SDHOST 4.1 (up to UHS-I speed).
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has a total of nine I2C controllers that are compatible with
the I2C controllers introduced in Tegra114. Two of these controllers
share pads with two DPAUX controllers (for AUX transactions).
Signed-off-by: Thierry Reding <treding@nvidia.com>
The initial patch only added UARTA, but there's no reason we shouldn't
be adding all of them. While at it, also specify the missing clocks and
resets for UARTA.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tegra186 has six CPUs: two CPUs are second generation Denver CPUs that
support ARMv8 and four CPUs are Cortex-A57 CPUs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
This adds the initial support of Tegra186 SoC. It provides enough to
enable the serial console and boot from an initial ramdisk.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[treding@nvidia.com: remove leading 0 from unit-addresses]
[treding@nvidia.com: remove unused nvidia,bpmp property]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a device node for the Product Register, which provides SoC product
and revision information.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This changes SDHI0 pin names for H3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports SDHI2 for H3ULCB onboard eMMC
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports SDHI2 for M3ULCB onboard eMMC
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports SDHI0 on M3ULCB board SD card slot
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports watchdog timer for M3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This enables EXTALR clock that can be used for the watchdog.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports GPIO keys on M3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This supports GPIO leds on M3ULCB board
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This enables the external crystal for the SCIF_CLK and its pinctrl, to
be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the initial device tree for the R8A7796 SoC based M3ULCB low cost
board (R-Car Starter Kit Pro)
This commit supports the following peripherals:
- SCIF (console)
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This updates H3ULCB device tree header with official board name
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fix invalid GIC interrupt flags - type IRQ_TYPE_NONE is not allowed for GIC
interrupts. Although this was working but with error messages like:
genirq: Setting trigger mode 0 for irq 16 failed
Use level high interrupt instead of type none. The choice of level high was
rather an arbitrary decision hoping it will work on each platform. Tests shown
no issues so far.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYLvZEAAoJEME3ZuaGi4PXtDoQAIRly22e50cqCTabUukeWjgy
GfOL1aDuH6+iFApTMvUJEsvlMiEQANsGaIREeNsJhHcPbAXFClYIBSG/e24ZSULz
PfiADjpi2EaUdhoyEHjiMnYR4jZ/Oj4lo4iWmgQWIcBRqzlrCr35EvXfQ9deEj9K
TR71X0oawz4krphSaqn7+VWTBlAN24QDZtPyFi6XWgbxtQTpGHddNYZGyF/LWCSp
AOmE3rm556rKF+VZpNtYCKfRmP9SkXwm7q/voAuqjABGf+rKWE6P1B7e+jlN82HY
7fLZzHS7lzM80OK3fExRNCPdmQ13NVBiyNQDIMxyF460/ObPwGfCjOW9bam5dErr
DcIMDq83lTUXEwdhSgMuI/Orm2VFpla2G0AptKfbu1NkAbLaK1PtH212Lcwvti5a
NV2Vu9wF8PIDR/7ctZw2M3HunTaCzQQQMJiwJbSKjCguhhUDye1+ZiYdfMdIXCoG
b3V40gbm0PdKqZwC/J9uygT9lWro4LBSR8HUJWbBtBU3qpmECuGOtX8sHgB3JDbV
Adv7p5DjIPdS/ELkFxhdupx9fZHzl3w95CD8T27jNZLx9PKNHb9r9e7tdnJ8amDd
JCwe78V+vOAfuyM6cwJntHlY6WCkkC0YU5QgOCo5+uuTDm3ulCsoG5b6b6LEdKD1
dRNqOTXx8uHPV4I0jaUR
=j/xt
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Topic branch with DT arm64 changes for v4.10.
Fix invalid GIC interrupt flags - type IRQ_TYPE_NONE is not allowed for GIC
interrupts. Although this was working but with error messages like:
genirq: Setting trigger mode 0 for irq 16 failed
Use level high interrupt instead of type none. The choice of level high was
rather an arbitrary decision hoping it will work on each platform. Tests shown
no issues so far.
* tag 'samsung-dt64-gic-flags-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Use human-friendly symbols for interrupt properties in exynos7
arm64: dts: exynos: Fix invalid GIC interrupt flags in exynos7
Signed-off-by: Olof Johansson <olof@lixom.net>
Adding the new "community" board for Armada 3700
-----BEGIN PGP SIGNATURE-----
iGoEABECACoFAlguJU8jHGdyZWdvcnkuY2xlbWVudEBmcmVlLWVsZWN0cm9ucy5j
b20ACgkQCwYYjhRyO9VNGQCfRB3BbnBCIgpu0n9wWumR7LsDmJYAoIafat62MwuH
gRsYSdrm1VVhMHwQ
=LnOL
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt64-4.10-1' of git://git.infradead.org/linux-mvebu into next/dt64
mvebu dt64 for 4.10 (part 1)
Adding the new "community" board for Armada 3700
* tag 'mvebu-dt64-4.10-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: Add definition for the Globalscale Marvell ESPRESSOBin Board
Signed-off-by: Olof Johansson <olof@lixom.net>
Support for the Allwinner A64, their first armv8 SoC.
-----BEGIN PGP SIGNATURE-----
iQIcBAABCAAGBQJYK3ohAAoJEBx+YmzsjxAgQ0cP/AtC7KSWnQ2afcEeIRxii9X+
QbiyQqPvmRF/mBtZN/49wKwRdh1qtsGk29UxMf06hrk2oA/Kc9KoPed+5Q0qG2ac
2m1KWN6G+qNk8bbd26A4sXRBsWUH7Gp7kCUjIBoRRUup6YQFySxIEjSU7dfmPHzi
Rxbq5fo9JMpar8bjVr1mVeIL/0p4Uz2LYt4miqARlztGJaUEZtBTrWDncLM0TqTV
hzeP1lKwelwkVDcrrSgZ5nBCcdmXFvIK6S3pNHcy11NCt7Qnf4pEn2heFs0Xh0/3
3nTcr7TEEeEc1oVc6UyM6GCgV3SrBlLTXIhvULQoU0sdhjTQxUo1zpDCO81p0UfQ
Qu7KxjhvXOjRYZLBQfXWN4VwOURrP9Bw2VwxN4vACUpQpQX/9eovIT8XVH9Jd8kO
bnbmzWLJq+arnE81CVrL7oqTK0r6O1/D+6kOLbvP9o6+Pt/2oJ8kHrJQCLXzfOnE
nhuZE489fTLeKtgloR5wez/Vu1JwaIhhHsfWkskljmi7Xx4XUJdu6XtBoS67qJE5
xDg/ujD3S9TT0AhZ5XWn1f6fCPI4N+E8HvHUJNLZSi1iPnW4c2wZ9tBBEOu7hh2X
7ZiZ6k+FOg+ZyY/jdChJ0SWvIzcutIbkP/0pKgLLPozEImv6ARqfyJbWauxbt/Hl
JKw9pE7Uo7ztdAz/52DL
=JkJ+
-----END PGP SIGNATURE-----
Merge tag 'sunxi-dt64-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt64
Allwinner arm64 DT changes for 4.10
Support for the Allwinner A64, their first armv8 SoC.
* tag 'sunxi-dt64-for-4.10' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
arm64: dts: add Pine64 support
Documentation: devicetree: add vendor prefix for Pine64
arm64: dts: add Allwinner A64 SoC .dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>
- Correct the hardware pin number of the usb node on the Hip06
- Add the Hisilicon Hip07 D05 board dts binding
- Add the initial dts for the Hip07 D05 board
- Fix the warning for the node without reg propery on the Hip06
- Fix the sas am max transmissions quirk property on the Hip06
- Disable the sas0 and sas2 on D03 board
- Add refclk node for SAS on the Hip06
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYKvD8AAoJEAvIV27ZiWZcIdgP/RXYCWB8yztd3K74qSJ8xydr
SBKY77zXwQBHzmDEbB881pJOaaBKzO9uTHo6nbkWRoE/cMYONohc+cO7WkkY4Lav
gMEJ9Ss7ckwCAjQAkzh4hHV4V8EMA1+aMDNbNR/slw+neQnzBuTMd4EERmve3Wzg
d4exeYgXVWGZLWhfFxp9xwyDt8fn03LoYYgqkM6wFKKpCXFx6dDVvjZw/V7W5vn0
GVBSxgam2BW4ug4/Q6ZlnBrNU1db8DzhGUfqXOd8569v8QUxBq19Gy1DP1eTEtCl
5WvnOIUSDQ+1MEFIaybq9CIWcM792XoQEpV9OI1EouAOYN4JeAiutGPQY0seyEIF
X1jIPBteetqLtXSf3uQdYf8hVmTMNZp+/f/jRWK6K/BPgeVts0N9t1jqhcSMzOaH
cneUkCuXsN4crBzBszhSsSPNMg7vvuprJNJCepESdiA4lBpn/KKFRj3aDNOw+ev3
dpC6Rn0htzeg4wWWez9MptlXnMhRoL01FR+0nNy4R3FB4OEphzzMZuTWEAe7EyKA
wwPG0u2WqR8nqFgk7iphHcoI1/NevSr0HbxRl0dWZ2UDZtESvSseZl0AEQRTU2ES
/rg9S6ShNQvQI9bHhITIXixZ07gpyM/TPbJlAUp6PHtxwiVpLoDsCQEzCYnktFl+
S/4pvu6yetne9bIPz59s
=MVHS
-----END PGP SIGNATURE-----
Merge tag 'hisi-arm64-dt-4.10' of git://github.com/hisilicon/linux-hisi into next/dt64
ARM64: DT: Hisilicon SoC DT updates for 4.10
- Correct the hardware pin number of the usb node on the Hip06
- Add the Hisilicon Hip07 D05 board dts binding
- Add the initial dts for the Hip07 D05 board
- Fix the warning for the node without reg propery on the Hip06
- Fix the sas am max transmissions quirk property on the Hip06
- Disable the sas0 and sas2 on D03 board
- Add refclk node for SAS on the Hip06
* tag 'hisi-arm64-dt-4.10' of git://github.com/hisilicon/linux-hisi:
arm64: dts: hisi: add refclk node to hip06 dts files for SAS
arm64: dts: hisi: disable sas0 and sas2 for d03
arm64: dts: hisi: fix hip06 sas am-max-trans quirk
arm64: dts: hip06: Fix no reg property warning
arm64: dts: hisilicon: Add initial dts for Hip07 D05 board
Documentation: arm64: Add Hisilicon Hip07 D05 dts binding
arm64: dts: hip06: Correct hardware pin number of usb node
Signed-off-by: Olof Johansson <olof@lixom.net>
- Enable Thermal Monitoring Unit (TMU) for thermal management on
LS1043A and LS2080A.
- Add support for LS1046A SoC, which has similar peripherals as
LS1043A but integrates 4 A72 cores.
- Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJYKrk2AAoJEFBXWFqHsHzOQlwH+wQXK2WABTOjRVchLOzup/cD
UtB7mbmXJrBSePa3OTvF8xMk4VFfjm9oljmLnUEnzWEfjsS2aURT2GJBWv/ddhqw
Mg/fYcZ1LgzJq8VOnenLpF1L2jc/I2hivCkBNmmkMK0HQvURKEAsdqNDc7Zg0meY
64qokll9Uz4DM2yeHkrUs9Q13UPs9/88ikYbE+CVDFaI0TCJjZUTImmjYkt8pJyk
poDtW6yE8ibMNk2DK4e4tthPRcYnhkFOtSJF6Qy6jouV/J9+aaKG5+rj4MBeF8Aj
T2+RFSQ4s2BuI5cH3qQq8Fv7lvF0Ay4wNWZl420R7shjbPWQNdIcbAbKL+51De0=
=jiir
-----END PGP SIGNATURE-----
Merge tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64
Freescale arm64 device tree updates for 4.10:
- Enable Thermal Monitoring Unit (TMU) for thermal management on
LS1043A and LS2080A.
- Add support for LS1046A SoC, which has similar peripherals as
LS1043A but integrates 4 A72 cores.
- Add two LS1046A based board support: LS1046A-QDS and LS1046A-RDB.
* tag 'imx-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: dts: ls2080a: Add TMU device tree support for LS2080A
arm64: dts: ls1043a: Add TMU device tree support for LS1043A
arm64: dts: add LS1046A-QDS board support
Documentation: DT: Add entry for QorIQ LS1046A-QDS board
arm64: dts: add LS1046A-RDB board support
Documentation: DT: Add entry for QorIQ LS1046A-RDB board
arm64: dts: add QorIQ LS1046A SoC support
dt-bindings: ahci-fsl-qoriq: updated for SoC ls1046a
dt-bindings: qoriq-clock: add LS1043A/LS1046A/LS2080A compatible for clockgen
dt-bindings: i2c: adds two more nxp devices
dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG
dt-bindings: fsl: Add LS1043A/LS1046A/LS2080A SoC compatible strings
Signed-off-by: Olof Johansson <olof@lixom.net>
us to use generic parser later on. Note that the driver supports
handling the legacy binding also with no #pinctrl-cells so these
changes can be queued separately from the driver changes.
-----BEGIN PGP SIGNATURE-----
iQIuBAABCAAYBQJYKlcwERx0b255QGF0b21pZGUuY29tAAoJEBvUPslcq6Vz/GQP
/2+QScOal19fL4GL2IQRZA7k6BqNIwig2Rn1Kc1y6ONDeXRcVBFLP7Rbe2LFjygJ
y+XcRcZePtspqQXCxESNxM+IClNHqFf/zY3055GAIkXCmWgKjs12CXU+u23ApUwx
uSTzPGCBp7aSakX+U1h4sBB/2vCyQbUyiyxQ3rEijnZAfNgAOvxj+Tk1YaZQzltA
/FJ06Nko9Os3jWHbEFudjTsYiFJyCa9x6MquupQKT9TF+P28Mb/+SFv05OLLITOV
eUEpuca2ml1KBgyRDnBZdhbfzzsHDwcP26JWEsejeOn5FIXMKdK7Ayo/lcZgHYn9
4hsQoarIrTI9F/7DSZIS4W9tOYCM+5cEensRo6yajaKGmeCGHtFveNftcXSloKSN
SrIc47l+XEXC+BFRrcurm9nf61HbmlozVpiURCtuw8vANLLtenWWzew12QFuBsDU
D2yNVg7e9rHg5cJzS3oq3rkb7/XGg2EnwQvV+xUuLorWtp7Eo5YWy4aBu/9UVVQX
kx3lj2PsGrrKofwyP711vUMqO8uEwZbx3SDW+S7WpSC6JoxObCh0kd+3YP1P2+8+
i7ltGDbI4gm+zAzUcB27CUOuLbx720DTUTbfHhi50KLjkWM/FEKTW+9MeJ9VChD4
t/JZSUYPGHR7DS+9a3qVew04Rjl4GsSthHNidahj4izj
=qXyV
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v4.10/pinctrl-cells-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Add #pinctrl-cells for pinctrl-single using dts files. This allows
us to use generic parser later on. Note that the driver supports
handling the legacy binding also with no #pinctrl-cells so these
changes can be queued separately from the driver changes.
* tag 'omap-for-v4.10/pinctrl-cells-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: Add #pinctrl-cells for pinctrl-single instances
Signed-off-by: Olof Johansson <olof@lixom.net>
One big merge this time with a total of 166 non-merge commits.
Most of the work, by far, is on dwc2 this time (68.2%) with dwc3 a far
second (22.5%). The remaining 9.3% are scattered on gadget drivers.
The most important changes for dwc2 are the peripheral side DMA support
implemented by Synopsys folks and support for the new IOT dwc2
compatible core from Synopsys.
In dwc3 land we have support for high-bandwidth, high-speed isochronous
endpoints and some non-critical fixes for large scatter lists.
Apart from these, we have our usual set of cleanups, non-critical fixes,
etc.
-----BEGIN PGP SIGNATURE-----
iQJRBAABCAA7FiEElLzh7wn96CXwjh2IzL64meEamQYFAlgu7+gdHGZlbGlwZS5i
YWxiaUBsaW51eC5pbnRlbC5jb20ACgkQzL64meEamQaDbxAAsgDPAp8QTx8D1d70
hSGyPZ55rmqlzBNbUUOQyk/AeN5xM3XVbjZNOxWn4c386iaDrngcqOrxjCbBRsje
b9yMESMiZsTPVlKXE45yXt//NHg1KUfpHON7rybaiFq0uqjUhnQf95DeYPgJVxit
7F9B+05XcNMyxYRoz6bGkRTU+lcJ6g3/orgKfp4t/hs8WUNXH6+71keMF+IdLYNH
mcPmJ8MXpfLzv8eweRwV0s/3flxCuFx1ksZ8cW6qHR5vX303X2sGTlinBmhfQapr
t0a+OBtLpZdNmjw/yB2odc/1jjLNRHpYU5xGqwouMx9Ca2PocFT2xFbmUWR23xp1
X0rkICRxcLPjZql2Uld5QHO9dPnF/FbX0Njuvxo+2r8ENE5/eG4C/RcYcRDmYPsu
u8k2rKFs0+yCOAU91rD8mayJVBWBJ4trqZFT0TcocCGsMTk8fTYpF1Iskj9Z4FKz
yo+lgyCCtp673ykGZ1ezsL6YWOmdrQv/PurKZqrXAmdhi6+mImLI/nAHtAdOZx0X
zK9MwPnwDxrPiqhrZ46+Bm/EjZI50TM44M1ldmCwKi/6/Nvy54DHMtjPI5/9205R
bjftW3DkVWAC//29RNcGEHtwiJFPEU/kdoRFOPhKGJ7ocCzFVSTFBgo02kDsC6De
Wouv2QTFuZN9s17o29YVD3bGJZM=
=5WN9
-----END PGP SIGNATURE-----
Merge tag 'usb-for-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb into usb-next
Felipe writes:
usb: patches for v4.10 merge window
One big merge this time with a total of 166 non-merge commits.
Most of the work, by far, is on dwc2 this time (68.2%) with dwc3 a far
second (22.5%). The remaining 9.3% are scattered on gadget drivers.
The most important changes for dwc2 are the peripheral side DMA support
implemented by Synopsys folks and support for the new IOT dwc2
compatible core from Synopsys.
In dwc3 land we have support for high-bandwidth, high-speed isochronous
endpoints and some non-critical fixes for large scatter lists.
Apart from these, we have our usual set of cleanups, non-critical fixes,
etc.
This patch adds device nodes for MFC video codec device to Exynos5433 SoC
dtsi and proper initial clock configuration to TM2 dts.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch adds device nodes for JPEG codec device to Exynos5433 SoC dtsi
and proper initial clock configuration to TM2 dts.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch adds device nodes for GScaler devices to Exynos5433 SoC dtsi
and proper initial clock configuration to TM2 dts.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This is not needed as the gadget now fully supports DMA and it can
autodetect it. This was initially added because gadget DMA mode was only
partially implemented so could not be automatically enabled.
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
UART3 device is not really needed for enabling audio block on TM2.
Enabling it made it working by enabling some common parent clocks,
what is now handled by improved exynos5433 clocks driver. Thus the UART3
device node can be safely disabled. The assigned-clocks entries are
however still needed, so move them under the respective CMU node.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Without this patch the clkout clock is orphaned and sound doesn't
work properly.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Move initial FSYS CMU (related to USB 3.0 devices) clocks configuration
from generic exynos5433.dtsi file to exynos5433-tm2.dts, as this is
a board specific item.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Audio PLL and oscillator clocks are proper parent clocks for AUD CMU.
They are not visible as such on first glance on Exynos5433 SoC docs,
but they are needed for this CMU to operate properly.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This patch corrects FSYS CMU parent clocks specified in clock controller
node to let improved Exynos5433 clocks driver to control proper clocks
on FSYS<->TOP CMU boundary.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Interrupt of type IRQ_TYPE_NONE is not allowed for GIC interrupts. The
GIC requires shared interrupts to be edge rising or level high. Platform
declares support for both. Set all interrupts type to level high, as this
works fine - tested on Exynos5433-based TM2 board.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
- Add clocks for auxadc on mt8173-evb
- Add nodes needed by clock controller for mt2701
- Use clocks from the clock controller for the uart of mt2701
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABAgAGBQJYJdcrAAoJELQ5Ylss8dNDoJcP/2q1LuStbojWMWxFKexQBCIk
8VEPzY8fyEckshbmgnz36qqp2MnecTLjb1ETesFIEGZWbEBnoAJC9hyIg6fFVZQi
mFZC8/0I7uvaFZHa+a3fQZb3tCmLMcWbAaGvA0p28kNRKnRhTMVHhLa7Z0WmMrG+
lQLlBBTP/xHErOakFJagkFIWYmmmMReS7x+X/tnVPienxkwODjpLYJQLL1wVmoqV
lpSj/nSRRDg8CeeG8/x+Odtr77L56glDMwwieXVpBe2sd+CpRk3QSTTcuYLkUp46
JBBKrr7TLLD6KEw6FgPjvjWDR3TH7S2wkbZVJN4B+8tmdEhpQhnle2MpJ6TYLKQb
ENwZ9JP70UD8o6mWb5e/g9R82WxUq1KDpdlU71OeBsnqfJRn1sge8bsO6+qs4+6Z
JapDW+Zwsewp9VZS12k4VdsCsYR0MZgX6XXj/NOOseJOMUXBFAoHj7vaC5Gj0UIT
VFKndrzWjIaVbaLHA/2KyVvOpJsEVTwSURyEko6XnTRLg+E85SSx+r6Bp3rlSlCV
Javet8M9YTLhPa1IeFMvf/1V4C4poX5tE4tvCiSZC1Wvxto5FSEgeGarq59Pgyi3
UWnxao8FHBHi3NU8khTI+rnIYtw5WxkEpqU5UUTYMUwsQ3x83VnU0WzpCSKQSNdD
Od24wmc/rrNKeU098abr
=wFjD
-----END PGP SIGNATURE-----
Merge tag 'v4.9-next-dts' of https://github.com/mbgg/linux-mediatek into next/dt
- Add bindings for mtk-scpsys for mt2701
- Add clocks for auxadc on mt8173-evb
- Add nodes needed by clock controller for mt2701
- Use clocks from the clock controller for the uart of mt2701
* tag 'v4.9-next-dts' of https://github.com/mbgg/linux-mediatek:
arm: dts: mt2701: Use real clock for UARTs
arm: dts: mt2701: Add clock controller device nodes
arm64: dts: mt8173: Fix auxadc node
soc: mediatek: Add MT2701 power dt-bindings
Signed-off-by: Olof Johansson <olof@lixom.net>
a fix for wrong i2c registers on rk3368 a new nvmem cell and
power-domain on rk3399 as well as moving mmc frequency
properties to the more generic max-frequency one.
-----BEGIN PGP SIGNATURE-----
iQEtBAABCAAXBQJYJzRqEBxoZWlrb0BzbnRlY2guZGUACgkQ86Z5yZzRHYE8HAgA
hFPUM6OmYsP81xJ8B8NscxZXi0r5ZTp14ouF5cREPF5mwXghrE5ZEGC/+xQJ/X4p
WSSGglNEJV5Ofs869wYDU3yZwNRzwkK7bGY+Mzq8eySYzkfZR2VZUf5ZStsLfUS1
j6Gr7jr2gwFtpjlwLmaUj8O4i/I3FfTiDLobqdpXoeoRcisLXS4/xDxEC1143TDR
ctylpGFEW/LXC1L4kTyLUZ6688654IC5qZBp4yHLIgb+qfd8k+CEjEyxtCzGpAQJ
sLQnsjjer4C3MqgOSDAjyguKpePCz0VIoE8wct136sQh20isbgWuhQjQ9+QzAaE+
/N+j0d87kaHUdPa097wQkg==
=LC5U
-----END PGP SIGNATURE-----
Merge tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64
64bit devicetree changes including the px5 evaluation board
a fix for wrong i2c registers on rk3368 a new nvmem cell and
power-domain on rk3399 as well as moving mmc frequency
properties to the more generic max-frequency one.
* tag 'v4.10-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
arm64: dts: rockchip: replace to "max-frequency" instead of "clock-freq-min-max"
arm64: dts: rockchip: add cpu-id nvmem cell node for rk3399
arm64: dts: rockchip: add sdmmc support for px5-evb
arm64: dts: rockchip: Add more properties for emmc on px5-evb
arm64: dts: rockchip: Add PX5 Evaluation board
arm64: dts: rockchip: add powerdomain for typec on rk3399
arm64: dts: rockchip: fix i2c resource error of rk3368
Signed-off-by: Olof Johansson <olof@lixom.net>
SoC along with two boards. A lot of Samsung people contributed into this
but the final work and commits were done by Chanwoo Choi.
This means that for v4.10 we got:
1. Exynos5433 DTSI.
2. Two boards: TM2 and TM2E. These are (almost fully) working mobile phones.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYIhaFAAoJEME3ZuaGi4PXu+0P/jN29SCAeg/9e/0LR0IB3/Zo
gCW4lRtunv0q3DzC6r5Wai0fZ/HgNi/3FUxAwVhS3D1+NdXYb9Dk5FL4v3Fqzsb1
ozbig+MC+imzIF281E3UFgSA38wn3er8xosFxeqYLqtlPT6UOv+wg6yuv2s6oYxN
4zS1SARsnp2pHCvLjCBM5LxO5+dx10NpUr+jEAw65yQbElq2iHAKgwro4KQPP/Bn
TU4Nx/yOiR7L/6IvgIN8zO/k/v8KyfRO/HM9yw4/ZLMO4AyX+/MhrBngHjELtxP6
CymvAlpJC9+FumWsMh5BiG7Jx7W0rlg1askyohff+fx7rCm8K6A+oLNE+RBex17W
vs+gsOCgHMPSdft/9eNkXd1U3c8fpZU59KW/8WFu6WSa2J0IFWmouYfwTYj80Xgk
NBd05IiY4X+UQ3+Jyl4CC7lttxfcizFNstx3HI/x+vYgZQTFrUONIxjVYm2pYYUk
tITYFev06qTVg21VVJhC0CZydDJzYf6jKhh6oqDz2TK1M2gpaGVbyWgMfNtZDWqR
/2Kb058Tf6q1fLG0O9EipQgQoiMLAVFMlNi8COZxYYFIXHI7WBF8pa6ybO1FbVIO
eDDJ80I6EjkcM3hm92jtNRYg86JQ4RDOq55vVzR9oxiaVmo3ecvWaIRFURR+OIw7
2bITXNAL7h5HNX6mx9Bx
=zbqq
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt64
Finally, I am really pleased to announce adding support for Exynos5433 ARMv8
SoC along with two boards. A lot of Samsung people contributed into this
but the final work and commits were done by Chanwoo Choi.
This means that for v4.10 we got:
1. Exynos5433 DTSI.
2. Two boards: TM2 and TM2E. These are (almost fully) working mobile phones.
* tag 'samsung-dt64-4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board
arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board
arm64: dts: exynos: Add dtsi files for Samsung Exynos5433 64bit SoC
Signed-off-by: Olof Johansson <olof@lixom.net>
- Switch CPU enable-method from spin-table to PSCI
- Add OPP tables to support generic cpufreq driver
- Misc fixes
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQIcBAABAgAGBQJYHfLxAAoJED2LAQed4NsGwnIP/3hE5jd52BkIf+LnM5muoiXd
A8FcqOQgj6zix6lrmAwQEGp+ociUiMYpQXgj8B5K1UwPKVRYjwvc1EuRQriI1btF
Kp8IIQnepLK2nRLliHl3w55bO7pdxx53rqeoF8HXF6FvkTMS1JycXI0pkZp8VkDQ
rDQ1LqCxBWtdTccOQgIUF615YysxpbrHZEbg7fYGtDmeEcu1e1c5VAnj0xgefWiY
C94iPba3HYKPQkn+6ueQR2M2VinNvl6V+m9FgmqcoQG5jDTyCM52DMD2h0RJMI9i
NsqxRfQAZc5B4ReyuFSDEKHwbqRwCx2o6LMWuyqCx2deRcHRS0hy6DiEnnaKheeC
Fqr4jnQwlE9lqXiCAklz1wNfO7bDdbWIfokRfDYxvBAQIQPbi2FUkDTYWqjoEU+8
VT6ZuPGYIjzDaZEMyVqN0PHj5mp4eQ4oBPDhyXrWU3d06Ky3I6yKMoQ43/inj1RC
BlA/OlsDr/uo2oYReqZGTSIGNYEAGoAqalV9paNDZxaIizzUHdRxoO97at7oHTHH
5HOCB3XP62cWFoE3t1yEoJBn6z/IrxCzTa8UkM+j/IMWT1xsoi3389u+5OOVgN7Y
oPi1pgdi82b6aD9QW4BG/RN0Pr+xTywPqU6omd14lKTlCxZfCOjLGrn2p0myg3GC
wbe4n2uoIL9AAnuYSfDg
=K2GC
-----END PGP SIGNATURE-----
Merge tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier into next/dt64
UniPhier ARM64 SoC DT updates for v4.10
- Switch CPU enable-method from spin-table to PSCI
- Add OPP tables to support generic cpufreq driver
- Misc fixes
* tag 'uniphier-dt64-v4.10' of git://git.kernel.org/pub/scm/linux/kernel/git/masahiroy/linux-uniphier:
arm64: dts: uniphier: make compatible of syscon nodes SoC-specific
arm64: dts: uniphier: add CPU clocks and OPP tables for LD20 SoC
arm64: dts: uniphier: add CPU clock and OPP table for LD11 SoC
arm64: dts: uniphier: increase register region size of sysctrl node
arm64: dts: uniphier: switch over to PSCI enable method
Signed-off-by: Olof Johansson <olof@lixom.net>
-----BEGIN PGP SIGNATURE-----
iQEcBAABAgAGBQJYFQwAAAoJEHm+PkMAQRiGr8YH/0urDFZm/RFu752rSawF7iVM
nx9Ck03YkRiMRZfdzPARbHJts7lhLG1rvsT50VQNMK1sVv0BXcrnJnDu49xV+dLj
DqXWvYGtdTCpAd34Am37pX/rrRl11vdJgS2VgprmbytkM8FD0xEe+aDKxnnmuALo
bggYDhMrJik3/UXG0zVfefKZJFLNAJiZv9AgWgkCR+bo861bu3UFn47tN1jGXOOl
QyFl5t7ggesojA5Q1U9hTrk1gS9Ia9it3Elyzfqb66lUdyf001I1nbUA/hNYyDXD
HU9dj3agvVXjvnDjyDR4/k86FA+EEEwSgk5CBTCVe30dLKnojFyb7FWZg72utg4=
=CHER
-----END PGP SIGNATURE-----
Merge tag 'v4.9-rc3' into next/dt64
Linux 4.9-rc3
* tag 'v4.9-rc3': (292 commits)
Linux 4.9-rc3
x86/smpboot: Init apic mapping before usage
ACPICA: Dispatcher: Fix interpreter locking around acpi_ev_initialize_region()
ACPICA: Dispatcher: Fix an unbalanced lock exit path in acpi_ds_auto_serialize_method()
ACPICA: Dispatcher: Fix order issue of method termination
ARC: module: print pretty section names
ARC: module: elide loop to save reference to .eh_frame
ARC: mm: retire ARC_DBG_TLB_MISS_COUNT...
ARC: build: retire old toggles
ARC: boot log: refactor cpu name/release printing
ARC: boot log: remove awkward space comma from MMU line
ARC: boot log: don't assume SWAPE instruction support
ARC: boot log: refactor printing abt features not captured in BCRs
ARCv2: boot log: print IOC exists as well as enabled status
ubifs: Fix regression in ubifs_readdir()
ubi: fastmap: Fix add_vol() return value test in ubi_attach_fastmap()
MAINTAINERS: Add entry for genwqe driver
VMCI: Doorbell create and destroy fixes
GenWQE: Fix bad page access during abort of resource allocation
vme: vme_get_size potentially returning incorrect value on failure
...
All of them are fixes for arm64 device tree
- 2 for the SPI node on the Armada 7K/8K
- 1 for the clock node on the Armada 37xx
-----BEGIN PGP SIGNATURE-----
iGoEABECACoFAlgk6sUjHGdyZWdvcnkuY2xlbWVudEBmcmVlLWVsZWN0cm9ucy5j
b20ACgkQCwYYjhRyO9VwEgCdGuixX9TYgWna2/PdhtVs5JXdW98Amwb054ygu7dw
2ONd6XGynL1PpVhQ
=qm28
-----END PGP SIGNATURE-----
Merge tag 'mvebu-fixes-4.9-1' of git://git.infradead.org/linux-mvebu into fixes
mvebu fixes for 4.9 (part 1)
All of them are fixes for arm64 device tree
- 2 for the SPI node on the Armada 7K/8K
- 1 for the clock node on the Armada 37xx
* tag 'mvebu-fixes-4.9-1' of git://git.infradead.org/linux-mvebu:
arm64: dts: marvell: add unique identifiers for Armada A8k SPI controllers
arm64: dts: marvell: fix clocksource for CP110 slave SPI0
arm64: dts: marvell: Fix typo in label name on Armada 37xx
Signed-off-by: Olof Johansson <olof@lixom.net>
We are incorrectly defining the pwr LED, attaching it to a gpio line
that is wired to the Wi-Fi SDIO module (which fails due to this).
The actual power LED is connected to the GPIO expander, which we don't
expose currently.
Fixes: 9d56c22a78 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.")
Thanks-to: Eric Anholt <eric@anholt.net> [for clarifying we can't control the LED]
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
When the USB PHY driver was introduced the reset framework did not
have support for triggering a reset pulse for shared resets. On GXBB
however there is only one reset line for both PHYs (meaning we have a
shared reset line). With the latest changes to the reset framework and
the corresponding updates to the phy-meson8b-usb2 driver we can now pass
the reset to the second PHY as well.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
All boards from the Tronsmart Vega S95 series are sharing similar MMC
based hardware.
sd_emmc_a is used to connect a Broadcom based SDIO wifi card (supported
by the brcmfmac driver). The 32.768KHz LPO clock for the wifi chip is
generated by PWM_E.
sd_emmc_b is routed to the SD-card. Unlike p20x there is no GPIO
regulator, meaning it only supports 3.3V (which seems to be hard-wired).
The eMMC chip is connected to sd_emmc_c and is implemented similar to
the meson-gxbb-p20x boards (meaning that hard-wired fixed regulators
are used).
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable Ethernet on the p23x board, pinctrl attribute is only added for
the p230 board since the p231 only uses the Internal PHY.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add Ethernet node with Internal PHY selection for the Amlogic GXL SoCs
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
meson-gx.dtsi was directly derived from meson-gxbb.dtsi, so keep the
copyrights in chronological order to not give a wrong impression.
Fixes: c328666d58 ("ARM64: dts: amlogic: Add Meson GX dtsi from GXBB")
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Enable the Infraread Receiver on the p23x board.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add SD/SDIO/MMC nodes and PWM 32768Hz clock configuration to provide
storage and WiFi functionality on the p23x boards.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add clock node for Amlogic Meson GXL.
The GXBB compatible is retained since the GXBB clock tree is used for now.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Add pinctrl nodes and pin definitions for Amlogic Meson GXL.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
[khilman: use GXBB include until GXL pinctrl support merged]
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Move common nodes between GXBB and GXL in to the common GX dtsi.
Leave the clock attributes in the GXBB dtsi for now.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
This patch adds ARM Performance Monitor Unit dt node for exynos7.
PMU provides various statistics on the operation of the CPU and
memory system at runtime, which are very useful when debugging or
profiling code. This enables the same.
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
[krzk: Squashed with "Add level for cpu dt node for exynos7"]
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Add otg-port nodes for both u2phy0 and u2phy1. The otg-port can
be used for USB2.0 part of USB3.0 OTG controller.
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
We will only maintain 1 dts for D03 and there are 50MHz
and 66MHz versions of D03: so we expect UEFI to update
refclk rate in the fdt at boot time.
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The SAS nodes sas0 and sas2 are not available on d03, so
disable them.
Signed-off-by: John Garry <john.garry@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
The string for the am max transmissions quirk property
is not correct -> fix it.
Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Xiang Chen <chenxiang66@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Warning (unit_address_vs_reg): Node /soc/ethernet@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/ethernet@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/ethernet@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/ethernet@1 has a unit name, but no reg property
Fix warning when build with W=1.
Cc: Kejian Yan <yankejian@huawei.com>
Cc: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Adding initial dt file for Hip07 D05 board, it is with dual socket
and each socket has two SCCLs(supper cpu cluster), one SCCL contains
four clusters and each cluster has quard Cortex-A72.
Since each SCCL has their own DDR controller, it could be treated as
a separate numa node. Thus, there are four numa nodes(one node with
sixteen core) on Hip07 SoC.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
Add the sd power-domain, its qos area and assign it to the
sdmmc device node.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Control power domain for eMMC via genpd to reduce power consumption.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Tested-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add backlight node for evb board, perpare for panel device node.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This patch fixes that sometimes hang at start-up time of the system.
As the below log:
...
[ 11.136543] calling pm_genpd_debug_init+0x0/0x60 @ 1
[ 11.141602] initcall pm_genpd_debug_init+0x0/0x60 returned 0 after 11 usecs
[ 11.148558] calling genpd_poweroff_unused+0x0/0x84 @ 1
<hang>
In some cases, the rk3399 should turn off the gmac power domain to save
power if some boards didn't register the gmac device node for rk3399.
Then, rk3399 need to make sure the gmac's pclk enabled if we need
operate the gmac power domain. (Due to the NOC had enabled always)
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Initial device tree support for Qualcomm MSM8994 SoC and
Huawei Angler / Google Nexus 6P support.
The device tree is based on the Google 3.10 kernel tree.
The device can be booted into the initrd with only one CPU running.
Signed-off-by: Bastian Köcher <mail@kchr.de>
[jeremymc@redhat.com: removed Kconfig, defconfig, move from Huawei to qcom dir]
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Tested-by: Michael Scott <michael.scott@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Initial device tree support for Qualcomm MSM8992 SoC and
LG Bullhead / Google Nexus 5X support.
Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
