Commit Graph

227 Commits

Author SHA1 Message Date
Linus Torvalds
40b9672a2f Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
Pull asm/uaccess.h whack-a-mole from Al Viro:
 "It's linux/uaccess.h, damnit... Oh, well - eventually they'll stop
  cropping up..."

* 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs:
  asm-prototypes.h: use linux/uaccess.h, not asm/uaccess.h
  riscv: use linux/uaccess.h, not asm/uaccess.h...
  ppc: for put_user() pull linux/uaccess.h, not asm/uaccess.h
2018-01-31 19:18:12 -08:00
Christoph Hellwig
7549cdf59d
riscv: rename sptbr to satp
satp is the name used by the current privileged spec 1.10, use it
instead of the old name.  The most recent release binutils release
(2.29) doesn't know about the satp name yet, so stick to the name from
the previous privileged ISA release and comment on the fact.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-30 19:16:12 -08:00
Christoph Hellwig
5ec9c4ff04
riscv: add ZONE_DMA32
This patch allows devices that require memory that can be addressed
using 32-bit addresses to work easily on RISC-V systems.  The newly
improved dma-direct ops will tap into this pool automatically for
32-bit addressing.

Based on an earlier patch from Wesley W. Terpstra.

CC: Wesley W. Terpstra <terpstra@sifive.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-30 19:14:27 -08:00
Christoph Hellwig
fe9b842f72
riscv: disable SUM in the exception handler
The SUM bit is enabled at the beginning of the copy_{to,from}_user and
{get,put}_user routines, and cleared before they return.  But these user
copy helper can be interrupted by exceptions, in which case the SUM bit
will remain set, which leads to elevated privileges for the code running
in exception context, as that can now access userspace address space
unconditionally.  This frequently happens when the user copy routines
access freshly allocated user memory that hasn't been faulted in, and a
pagefault needs to be taken before the user copy routines can continue.

Fix this by unconditionally clearing SUM when the exception handler is
called - the restore code will automatically restore it based on the
saved value.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-30 19:12:38 -08:00
Tobias Klauser
509009ccfa
riscv: remove redundant unlikely()
IS_ERR_VALUE() already implies unlikely(), so it can be omitted.

Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-30 19:12:06 -08:00
Alan Kao
10626c32e3
riscv/ftrace: Add basic support
This patch contains basic ftrace support for RV64I platform.
Specifically, function tracer (HAVE_FUNCTION_TRACER), function graph
tracer (HAVE_FUNCTION_GRAPH_TRACER), and a frame pointer test
(HAVE_FUNCTION_GRAPH_FP_TEST) are implemented following the
instructions in Documentation/trace/ftrace-design.txt.

Note that the functions in both ftrace.c and setup.c should not be
hooked with the compiler's -pg option: to prevent infinite self-
referencing for the former, and to ignore early setup stuff for the
latter.

Signed-off-by: Alan Kao <alankao@andestech.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-30 19:10:54 -08:00
Palmer Dabbelt
5d44bf2065
RISC-V: Remove mem_end command line processing
This is just some cruft left over from before the port converted to
device tree.  The right way to handle memory regions is to specify them
in the device tree, which BBL (our simplest bootloader) is already
capable of doing.  This patch simply removes the cruft.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-30 19:09:53 -08:00
Michael Clark
3e076a7e04
RISC-V: Remove duplicate command-line parsing logic
builtin_cmdline handling is present in drivers/of/fdt.c so the
duplicate logic in arch/riscv/setup.c results in duplication of
the builtin command line. e.g. CONFIG_CMDLINE="root=/dev/vda ro"
gets appended twice and gives "root=/dev/vda ro root=/dev/vda ro"

Before this patch:

[    0.000000] Kernel command line: root=/dev/vda ro root=/dev/vda ro

After this patch:

[    0.000000] Kernel command line: root=/dev/vda ro

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-30 19:09:52 -08:00
Christoph Hellwig
1125203c13
riscv: rename SR_* constants to match the spec
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-07 15:14:39 -08:00
Palmer Dabbelt
9e49a4ed07
RISC-V: Make __NR_riscv_flush_icache visible to userspace
We were hoping to avoid making this visible to userspace, but it looks
like we're going to have to because QEMU's user-mode emulation doesn't
want to emulate a vDSO.  Having vDSO-only system calls was a bit
unothodox anyway, so I think in this case it's OK to just make the
actual system call number public.

This patch simply moves the definition of __NR_riscv_flush_icache
availiable to userspace, which results in the deletion of the now empty
vdso-syscalls.h.

Changes since v1:

* I've moved the definition into uapi/asm/syscalls.h rathen than
  uapi/asm/unistd.h.  This allows me to keep asm/unistd.h, so we can
  keep the syscall table macros sane.
* As a side effect of the above, this no longer disables all system
  calls on RISC-V.  Whoops!

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-01-07 15:14:37 -08:00
Palmer Dabbelt
27b0174525
RISC-V: Remove unused CONFIG_HVC_RISCV_SBI code
This is code that probably should never have made it into the kernel in
the first place: it depends on a driver that hadn't been reviewed yet.
During the HVC_SBI_RISCV review process a better way of doing this was
suggested, but that means this code is defunct.  It's compile-time
disabled in 4.15 because the driver isn't in, so I think it's safe to
just remove this for now.

CC: Greg KH <gregkh@linuxfoundation.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-12-11 07:51:09 -08:00
Dan Carpenter
86ad5c97ce
RISC-V: Logical vs Bitwise typo
In the current code, there is a ! logical NOT where a bitwise ~ NOT was
intended.  It means that we never return -EINVAL.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-12-11 07:51:06 -08:00
Al Viro
5e454b5457 riscv: use linux/uaccess.h, not asm/uaccess.h...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2017-12-04 18:01:01 -05:00
Palmer Dabbelt
3b62de26cf
RISC-V: Fixes for clean allmodconfig build
Olaf said: Here's a short series of patches that produces a working
allmodconfig. Would be nice to see them go in so we can add build
coverage.

I've dropped patches 8 and 10 from the original set:

* [PATCH 08/10] (RISC-V: Set __ARCH_WANT_RENAMEAT to pick up generic
  version) has a better fix that I've sent out for review, we don't want
  renameat.
* [PATCH 10/10] (input: joystick: riscv has get_cycles) has already been
  taken into Dmitry Torokhov's tree.
2017-12-01 13:31:31 -08:00
Palmer Dabbelt
0e710ac652 RISC-V: Clean up an unused include
We used to have some cmpxchg syscalls.  They're no longer there, so we
no longer need the include.

CC: Christoph Hellwig <hch@infradead.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 12:58:29 -08:00
Andrew Waterman
921ebd8f2c RISC-V: Allow userspace to flush the instruction cache
Despite RISC-V having a direct 'fence.i' instruction available to
userspace (which we can't trap!), that's not actually viable when
running on Linux because the kernel might schedule a process on another
hart.  There is no way for userspace to handle this without invoking the
kernel (as it doesn't know the thread->hart mappings), so we've defined
a RISC-V specific system call to flush the instruction cache.

This patch adds both a system call and a VDSO entry.  If possible, we'd
like to avoid having the system call be considered part of the
user-facing ABI and instead restrict that to the VDSO entry -- both just
in general to avoid having additional user-visible ABI to maintain, and
because we'd prefer that users just call the VDSO entry because there
might be a better way to do this in the future (ie, one that doesn't
require entering the kernel).

Signed-off-by: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 12:58:29 -08:00
Andrew Waterman
08f051eda3 RISC-V: Flush I$ when making a dirty page executable
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart.  As a result, we need to explicitly flush
the instruction cache whenever marking a dirty page as executable in
order to preserve the correct system behavior.

Local instruction caches aren't that scary (our implementations actually
flush the cache, but RISC-V is defined to allow higher-performance
implementations to exist), but RISC-V defines no way to perform an
instruction cache shootdown.  When explicitly asked to do so we can
shoot down remote instruction caches via an IPI, but this is a bit on
the slow side.

Instead of requiring an IPI to all harts whenever marking a page as
executable, we simply flush the currently running harts.  In order to
maintain correct behavior, we additionally mark every other hart as
needing a deferred instruction cache which will be taken before anything
runs on it.

Signed-off-by: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 12:58:25 -08:00
Olof Johansson
4bde63286a RISC-V: Provide stub of setup_profiling_timer()
Fixes the following on allmodconfig build:

profile.c:(.text+0x3e4): undefined reference to `setup_profiling_timer'

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:12:15 -08:00
Olof Johansson
24948b7ec0 RISC-V: Export some expected symbols for modules
These are the ones needed by current allmodconfig, so add them instead
of everything other architectures are exporting -- the rest can be
added on demand later if needed.

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:01:10 -08:00
Olof Johansson
83e7b8769a RISC-V: move empty_zero_page definition to C and export it
Needed by some modules (exported by other architectures).

Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-30 10:01:10 -08:00
Andrew Waterman
28dfbe6ed4 RISC-V: Add VDSO entries for clock_get/gettimeofday/getcpu
For now these are just placeholders that execute the syscall.  We will
later optimize them to avoid kernel crossings, but we'd like to have the
VDSO entries from the first released kernel version to make the ABI
simpler.

Signed-off-by: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-27 07:51:39 -08:00
Palmer Dabbelt
b7e5a59150 RISC-V: Remove __vdso_cmpxchg{32,64} symbol versions
These were left over from an earlier version of the port.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2017-11-27 07:51:39 -08:00
Palmer Dabbelt
fbe934d69e RISC-V: Build Infrastructure
This patch contains all the build infrastructure that actually enables
the RISC-V port.  This includes Makefiles, linker scripts, and Kconfig
files.  It also contains the only top-level change, which adds RISC-V to
the list of architectures that need a sed run to produce the ARCH
variable when building locally.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:49 -07:00
Palmer Dabbelt
e2c0cdfba7 RISC-V: User-facing API
This patch contains code that is in some way visible to the user:
including via system calls, the VDSO, module loading and signal
handling.  It also contains some generic code that is ABI visible.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:48 -07:00
Palmer Dabbelt
7db91e57a0 RISC-V: Task implementation
This patch contains the implementation of tasks on RISC-V, most of which
is involved in task switching.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:46 -07:00
Palmer Dabbelt
5d8544e2d0 RISC-V: Generic library routines and assembly
This patch contains code that is more specific to the RISC-V ISA than it
is to Linux.  It contains string and math operations, C wrappers for
various assembly instructions, stack walking code, and uaccess.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:45 -07:00
Palmer Dabbelt
76d2a0493a RISC-V: Init and Halt Code
This contains the various __init C functions, the initial assembly
kernel entry point, and the code to reset the system.  When a file was
init-related this patch contains the entire file.

Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2017-09-26 15:26:44 -07:00