Complement the GM20B GPU device tree node on Tegra210 with missing
properties to make it usable.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2
iQIcBAABCAAGBQJXI3yjAAoJEN0jrNd/PrOhmUEQAK73RCf3YtRpEFMWOFIrU6cG
5YsUw5auf65Bc98mFn9a+3lEUMl7QBpLrY3QialllK+CA4pQDs74fwk3rEZ0pSIK
BUQMaKpkoYsfEqbsV3zEYLfVXkoK5oss1Vd6KfjR0qH4dDQJ8cAEPHkm0KGs4Mxo
ud1AsZ/0L/3zQEvSZqdEks7N+g+yBXtSzx7CnQ8y9OEHdLQAvh5f1WD5rKc8ir+z
P/ufsl16J365Sv4JTOzWQhnOaQXgSyzM+CECGZtcCTd0GTel1y6O+SRgIkKv9nD5
jeFcPMuMYvPKD4FeZgedMia1NQd1mkwWA5gEb4KwOfxgGFUKkYft6hy2Zx4wUVm2
I9tvDhzzOJduJUu3F69Zws6ztHUPB5zM3hIrSPptkOVME6k063TBGVItGH0NgJAT
fubvqi0xbVHhZ6jGSY6kwwo1nnIB2DtPcgF8Gm0bHctF4Zveyo3Vq5iyaTWPjEhj
l+qc1rTgmQf2lFvMUXEsIQbl8b8m/UcWK2hrGj7Wq0qvD8CwP4wg0S8uRm+hDBX0
ZUk0lIqC1PBDZkVETkzNEpXI6eKeixaXYgr6jsCCFUZdBmeFJ/4m+Kbn5xCNObGJ
pwGkhSZceBABgGz/p/yfAS0RRlmfYotg4yRa0JHkVgfK2oqOtAl5QiQzN4fMyRkt
vAPrcTd61LCB4hiC31K3
=yX4c
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt64
Merge "arm64: tegra: Enable GM20B GPU on Tegra210" from Thierry Reding:
Complement the GM20B GPU device tree node on Tegra210 with missing
properties to make it usable.
* tag 'tegra-for-4.7-gm20b' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: Add IOMMU node to GM20B on Tegra210
arm64: tegra: Add reference clock to GM20B on Tegra210
dt-bindings: Add documentation for GM20B GPU
dt-bindings: gk20a: Document iommus property
dt-bindings: gk20a: Fix typo in compatible name
The operating system driver can take advantage of the IOMMU to remove
the need for physically contiguous memory buffers.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This clock is required for the GPU to operate.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Remove the "#power-domain-cells" property which was incorrectly
included by commit e53095857166 ("arm64: tegra: Add Tegra210
support").
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.
Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses with
more than one cell.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired
with four Cortex-A53 cores in a switched configuration. It features a
GPU using the Maxwell architecture with support for DX11, SM4, OpenGL
4.5, OpenGL ES 3.1 and providing 256 CUDA cores. It supports hardware
accelerated en- and decoding of various video standards including
H.265, H.264 and VP8 at 4K resolutions and up to 60 fps.
Besides the multimedia features it also comes with a variety of I/O
controllers such as GPIO, I2C, SPI, SDHCI, PCIe, SATA and XHCI, to
name only a few.
Add a SoC-level device tree file that describes most of the hardware
available on the SoC. This includes only hardware for which a device
tree binding already exists or which is trivial to describe.
Signed-off-by: Thierry Reding <treding@nvidia.com>
