Commit Graph

8 Commits

Author SHA1 Message Date
Barry Song
c1e3c1196b ARM: SIRF: make sirf irqchip driver optional since new SoCs will have GIC
New MARCO and POLO SoC use GIC, so make irq.c optional and enable it
only if we enable ARCH_PRIMA2 in Kconfig

Signed-off-by: Barry Song <Baohua.Song@csr.com>
2012-08-28 17:06:10 +08:00
Barry Song
d0ec63f852 ARM: PRIMA2: use DT_MACHINE_START and convert to generic board
we will have SiRFMarco and SiRFPolo, all of them will be in the
generic board.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
2012-08-28 17:06:10 +08:00
Barry Song
bc0e489eb0 clk: prima2: move from arch/arm/mach to drivers/clk
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2012-08-24 12:10:04 -07:00
Rongjun Ying
2558bd99cb ARM: CSR: PM: add sleep entry for SiRFprimaII
This patch adds suspend-to-mem support for prima2. It will make prima2
enter DEEPSLEEP mode while accepting PM_SUSPEND_MEM command.

Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <baohua.song@csr.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-09-21 23:25:59 +08:00
Zhiwu Song
684f741446 ARM: CSR: add rtc i/o bridge interface for SiRFprimaII
The module is a bridge between the RTC clock domain and the CPU interface
clock domain. ARM access the register of SYSRTC, GPSRTC and PWRC through
this module.

Signed-off-by: Zhiwu Song <zhiwu.song@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2011-09-11 09:17:53 +08:00
Rongjun Ying
89e162afd3 ARM: CSR: initializing L2 cache
Signed-off-by: Rongjun Ying <rongjun.ying@csr.com>
Signed-off-by: Barry Song <baohua.song@csr.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2011-07-09 07:21:53 +08:00
Barry Song
31adb06f9d ARM: CSR: mapping early DEBUG_LL uart
Signed-off-by: Barry Song <baohua.song@csr.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2011-07-09 07:20:51 +08:00
Binghua Duan
02c981c07b ARM: CSR: Adding CSR SiRFprimaII board support
SiRFprimaII is the latest generation application processor from CSR’s
Multifunction SoC product family. Designed around an ARM cortex A9 core,
high-speed memory bus, advanced 3D accelerator and full-HD multi-format
video decoder, SiRFprimaII is able to meet the needs of complicated
applications for modern multifunction devices that require heavy concurrent
applications and fluid user experience. Integrated with GPS baseband,
analog and PMU, this new platform is designed to provide a cost effective
solution for Automotive and Consumer markets.

This patch adds the basic support for this SoC and EVB board based on device
tree. It is following the ZYNQ of Xilinx in some degree.

Signed-off-by: Binghua Duan <Binghua.Duan@csr.com>
Signed-off-by: Rongjun Ying <Rongjun.Ying@csr.com>
Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com>
Signed-off-by: Yuping Luo <Yuping.Luo@csr.com>
Signed-off-by: Bin Shi <Bin.Shi@csr.com>
Signed-off-by: Huayi Li <Huayi.Li@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2011-07-09 07:19:28 +08:00